JP3158404B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a bipolar semiconductor device having improved high-frequency characteristics.

[Conventional technology]

2. Description of the Related Art Conventionally, there are the following techniques for forming a semiconductor device of this type.

4A and 4B are a pattern diagram showing a conventional semiconductor device and a longitudinal sectional view of a semiconductor chip.

This conventional example will be described along the manufacturing process. N-type buried diffusion layer 2 on P-type semiconductor substrate 1 made of single crystal silicon
And a P-type buried diffusion layer 2, on which an N-type epitaxial layer 4 is provided. Further, a P-type insulating separation / diffusion layer 5 extending from the surface of the N-type epitaxial layer 4 to the P-type buried diffusion layer 3 is provided, and the P-type buried diffusion layer 3 and the P-type insulating separation / diffusion layer 5 surround a transistor forming region. The insulation between them is performed. Further, on the surface of the N-type epitaxial layer 4, an insulator layer 6 such as silicon dioxide for selectively separating elements at the surface is provided. Further, a P-type intrinsic base region 7, a P-type external base region 8, and an N-type collector extraction region 9 are provided by selective diffusion from the surface of the N-type epitaxial layer 4, and the N-type impurity is removed through the polycrystalline silicon layer 10. By introduction, an N-type emitter region 11 is provided. Further, it is formed by connecting to an external metal wiring 14 such as aluminum through openings formed in the interlayer insulating layers 12 and 13.

FIGS. 5A and 5B are a plan view and a longitudinal sectional view, respectively, showing a structure in which the high-frequency characteristics are improved as compared with the above-described semiconductor device. It is called. That is, for the above configuration, P
First and second P-type external base regions 8, 8 'are provided on both sides of the mold intrinsic base region 7, and the first and second P-type external base regions 8, 8' are connected by external metal wiring 14. It has a structure consisting of: In this improved structure, the P-type intrinsic base region 7 immediately below the N-type emitter region 11 is removed from the P-type external base region.
The base resistance indicated by the resistance component of the P-type intrinsic base region 7 in the path extending to 8, 8 'is reduced to about half since the path changes from one place to two places (parallel) as compared with the above example. it can.

[Problems to be solved by the invention]

In the above-described conventional semiconductor device having a double base structure,
Although it is possible to reduce the base resistance, on the other hand,
The area required to form the base region including the intrinsic base region 7 and the external base regions 8, 8 'is about 1.
Since it is 5 times, the capacitance between the base and the collector is increased, and the improvement of the high frequency characteristics as a whole is relatively small. Further, since the element area of the transistor is increased, the degree of integration is reduced.

[Means for solving the problem]

A first method of manufacturing a semiconductor device according to the present invention includes the steps of forming a reverse conductivity type buried diffusion layer and a reverse conductivity type buried diffusion layer separated from the reverse conductivity type buried diffusion layer on a semiconductor substrate of one conductivity type. Selectively forming, forming a reverse conductivity type epitaxial layer on the semiconductor substrate, forming an oxidation resistant film pattern on a surface of an element formation region of the epitaxial layer, Forming a diffusion layer for isolation and a first external base diffusion layer by selectively introducing an impurity of one conductivity type into the surface of the epitaxial layer in a predetermined area of the area not covered by the conductive film pattern; Using the film as a mask, the epitaxial layer is thermally oxidized to form an insulator layer in the epitaxial layer, and the separation diffusion layer and the first external base diffusion layer are diffused into the epitaxial layer. A step of connecting at least the isolation diffusion region to the one conductivity type buried diffusion layer below the insulator layer as an isolation diffusion region and a first external base diffusion region, respectively; A first conductivity type second base region and a first conductivity type second base region having a higher impurity concentration and a deeper diffusion layer than the first base region are formed in predetermined regions, respectively. Making the second external base region overlap the intrinsic base region and surrounding the intrinsic base region, and connecting the first external base diffusion region and the second external base region around the intrinsic base region. Features. Further, the second aspect of the semiconductor device of the present invention
A method of selectively forming a reverse conductivity type buried diffusion layer and a reverse conductivity type buried diffusion layer and a conductivity type buried diffusion layer separately from each other on a semiconductor substrate of one conductivity type, Forming a reverse conductivity type epitaxial layer on the semiconductor substrate, and forming an oxidation-resistant film pattern on a surface of the element forming region of the epitaxial layer excluding a region where a first external base diffusion layer is to be formed; A diffusion layer for isolation by selectively introducing an impurity of one conductivity type into a surface of the epitaxial layer in a predetermined region of a region not including the region where the first external base diffusion layer is to be formed and not covered by the oxidation resistant film pattern; And the first
Forming an external base diffusion layer; thermally oxidizing the epitaxial layer using the oxidation resistant film pattern as a mask to form an insulator layer in the epitaxial layer; and forming the isolation diffusion layer and the first external layer. A base diffusion layer is diffused into the epitaxial layer to form an isolation diffusion region and a first external base diffusion region, respectively, and at least the isolation diffusion region below the insulator layer is connected to the one conductivity type buried diffusion layer. Forming a one-conductivity-type intrinsic base region and a one-conductivity-type second external base region having a higher impurity concentration and a deeper diffusion layer than the intrinsic base region in respective predetermined regions of the element formation region of the epitaxial layer. Then, the intrinsic base region is formed so that a part thereof is connected to the first external base diffusion region, and the element forming region is formed. Said intrinsic base region and the first
Forming at least the second external base region in a predetermined region other than the external base diffusion region, and connecting the first external base diffusion region and the second external base region.

〔Example〕

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1A is a pattern diagram showing a first embodiment of the present invention, and FIGS. 1B and 1C are lines II 'and II-II' in FIG. 1A, respectively. FIG. 3 is a vertical cross-sectional view of a semiconductor chip cut at a corresponding portion.

 This embodiment will be described along the manufacturing steps.

P-type single crystal silicon substrate 1 having a specific resistance of about 5 to 30 Ωcm
Is provided, and an N-type buried diffusion layer 2 and a P-type buried diffusion layer 3 are selectively provided thereon by ion implantation or impurity diffusion. The N-type buried diffusion layer 2 and the P-type buried diffusion layer 3 are, for example, 15 to 40 Ω / □ and 80 to 300 Ω, respectively.
/ □. Further, an N-type epitaxial layer 4 having a specific resistance of 0.3 to 2.0 Ωcm and a thickness of 1.5 to 4.0 μm is provided thereon. Further, a P-type insulating separation / diffusion layer 5 is provided by selective diffusion from the surface of the N-type epitaxial layer 4,
Along with the P-type buried diffusion layer 3, the element regions such as transistors and resistors are insulated and separated. The P-type isolation / diffusion layer 5 is, for example,
5.0 × 10 ^{13 to} 3.0 × 10 ¹⁴ cm ^-2 at energy of 100 to 150 keV
This is achieved by boron ion implantation at a dose and heat treatment in a nitrogen atmosphere at 980 to 1000 ° C.

Further, by selectively oxidizing the surface of the N-type epitaxial layer 4, an insulating layer 6 made of silicon dioxide having a thickness of 0.6 to 1.2 μm is provided. At this time, a P-type diffusion layer 20 is selectively provided below a part of the insulator layer 6 so as to be aligned with the insulator layer 6.

Further, a P-type intrinsic base region 7 and first and second P-type external base regions 8, 8 'are provided in an element region defined by the insulator layer 6. A P-type intrinsic base region 7 and a P-type external base region 8,
8 ′ is energy of 10 to 30 keV and 1.0 × 10 ^{13 to} 3.0
It is constituted by boron ion implantation at a dose of × 10 ¹³ cm ⁻² and 2.0 × 10 ^{15 to} 1.0 × 10 ¹⁶ cm ⁻² cm, and has a layer resistance and a junction depth of 2 to 6 kΩ / □, 0.15 to 0.3 μm. And 20-70Ω /
□, about 0.4 to 0.6 μm.

Similarly, ions of phosphorus or arsenic are implanted into the N-type collector extraction region 9 (dosage is 2.0 × 10 ^{15 to} 1.0 × 10 ¹⁶ cm ⁻² ).
Thereby, it is provided in the N-type epitaxial layer 4 so as to be isolated from the P-type intrinsic base region 7 and the P-type external base regions 8, 8 '.

Further, a P-type intrinsic base region 7 is formed through an opening provided in an interlayer insulating layer 12 made of silicon dioxide formed by a CVD method.
Then, an emitter electrode 10 made of polycrystalline silicon is adhered, arsenic is introduced into the P-type intrinsic base region via the emitter electrode, and an N-type emitter region 11 is provided.

Further, the P-type external base region 8, the emitter electrode 10 and the N-type collector extraction region 9 are connected to the external metal wiring 14 made of aluminum or the like through the opening provided in the interlayer insulating film 13.
Is provided.

A method for forming the P-type diffusion layer 20 in this embodiment will be described with reference to FIGS. First, FIG. 2 (A)
As shown in FIG. 7, a 50 nm-thick silicon dioxide film 32 is deposited on a single crystal silicon substrate 31, and a 100-130 nm silicon nitride film 33 is deposited thereon. Selectively deposit a photoresist layer 34 by photolithography to define the device area,
Next, the silicon nitride film 33 is selectively removed using the photoresist layer. Next, as shown in FIG. 2 (B), a second photoresist layer 35 having an opening larger than the photoresist layer 34 is selectively applied while the photoresist layer 34 is left. Next, using the photoresist layer 34 and the second photoresist layer 35 as masks, boron ions are implanted at an energy of 80 to 150 keV and at a dose of 1.0 × 10 ^{13 to} 3.0 × 10 ¹³ cm ⁻² . Next, as shown in FIG. 2 (C),
The photoresist layers 34 and 35 are removed, and H ₂ − at 960 ° C. to 1050 ° C.
The oxidation treatment in the O ₂ atmosphere forms the silicon dioxide film 36 and obtains the P-type diffusion layer 20 whose end is aligned with the silicon dioxide film 36. Under the conditions described above, the P-type diffusion layer has a junction depth of 0.6 μm to 0.8 μm with a layer resistance of 300 Ω to 1.5 kΩ / □.

As shown in FIG. 1A, the P-type diffusion layer 20 includes a P-type intrinsic base region 7 and first and second P-type external base regions 8, 8 '.
Formed in contact with Therefore, the second P-type external base region 8 ′ is connected to the first external base region 8 via the P-type diffusion layer 20.
The need for the contact hole 15 for connection with the external metal wiring for the second P-type external base region is eliminated, and the area can be reduced accordingly. Further, since the P-type diffusion layer 20 can be provided at the end of the insulator layer that defines the transistor formation region, the area does not increase.

In the experiment of the inventor, the shape shown in the first embodiment was changed to P
The emitter area is 1.2 μm with the width of the diffusion layer 20 being 1.8 μm.
With a × 12 μm sample, the base-collector capacitance has been confirmed to be 15% lower than the conventional double base structure. The width of the P-type diffusion layer 20 is 2.5 μm or less, preferably 0.8 μm to 2.0 μm from the viewpoint of reducing the base-collector capacitance.
It is effective to set it to μm.

3 (A) and 3 (B) are a pattern diagram and a longitudinal sectional view of a semiconductor chip showing a second embodiment of the present invention.

In the second embodiment, a P-type intrinsic base region 7, first and second P-type base regions 8, 8 'and an N-type collector extraction region 9 are provided.
Are separated by an insulator layer 6, and P
The structure in which the pattern intrinsic base region 7 is not directly in contact with the first and second P-type external base regions 8 and 8 ′ but is connected all around via the P-type diffusion layer 20 under the insulator layer 6. It has become.

In this embodiment, the first and second P-type external base regions 8,
Since the 8 'can be formed so as to be aligned by the insulator layer 6, the distance between the N-type emitter region 11 and the P-type external base regions 8, 8' which causes a decrease in the emitter-base breakdown voltage can be made constant. , N-type emitter region, and P-type external base region. Further, when the layer resistance of the P-type diffusion layer 20 can be set to a low value, there is an advantage that the second P-type external base region 8 'can be omitted.

〔The invention's effect〕

As described above, according to the present invention, by connecting the first and second external base regions at both ends of the intrinsic base region with the P-type diffusion layer below the insulator layer, the metal wiring is formed in the second external base region. Since it is not necessary to provide a contact hole with the base, the area can be reduced, so that the base-collector capacitance can be reduced by reducing the area of the base region while having the same base resistance reduction effect as the conventional double base structure. This has the effect of improving high frequency characteristics.

[Brief description of the drawings]

FIG. 1 (A) is a pattern diagram showing a first embodiment of the present invention, and FIGS. 1 (B) and 1 (C) are II 'of FIG. 1 (A).
2 (A) to 2 (C) are longitudinal sectional views of a semiconductor chip cut along a line and a portion corresponding to the line II-II '. FIGS. FIGS. 3 (A) and 3 (B) are pattern diagrams showing a second embodiment and a vertical sectional view of a semiconductor chip, and FIGS. 4 (A) and (B) are pattern diagrams showing a conventional example. FIGS. 5A and 5B are a longitudinal sectional view of a semiconductor chip and a pattern diagram showing another conventional example. DESCRIPTION OF SYMBOLS 1 ... P type single crystal silicon substrate, 2 ... N type buried diffusion layer, 3 ... P type buried diffusion layer, 4 ... N type epitaxial layer, 5 ... P type insulation separation diffusion layer, 6 ... Insulation Material layer, 7
... P-type intrinsic base region, 8 ... (first) P-type external base region, 8 '... second P-type external base region, 9 ...
Collector extraction area, 10 ... Emitter electrode, 11 ... N
Emitter regions, 12, 13 ... interlayer insulating film, 14 ... external metal wiring, 15 ... contact holes, 20 ... P-type diffusion layer, 31 ...
... Single-crystal silicon substrate, 32 ... Silicon dioxide film, 33 ...
... silicon nitride film, 34 ... photoresist layer, 35 ... second photoresist, 36 ... silicon dioxide film.

──────────────────────────────────────────────────の Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) H01L 21/33-21/331 H01L 21/8222-21/8228 H01L 21/8232 H01L 27/06-27 / 06 101 H01L 27/08-27/08 101 H01L 27/082 H01L 29/68-29/737

Claims (2)

(57) [Claims] A step of selectively forming a reverse conductivity type buried diffusion layer and one conductivity type buried diffusion layer separated from the reverse conductivity type buried diffusion layer on a semiconductor substrate of one conductivity type; Forming a reverse conductivity type epitaxial layer on the semiconductor substrate, forming an oxidation resistant film pattern on a surface of an element forming region of the epitaxial layer, and forming a region not covered by the oxidation resistant film pattern. Forming a diffusion layer for isolation and a first external base diffusion layer by selectively introducing an impurity of one conductivity type into the surface of the epitaxial layer in a predetermined region; and forming the epitaxial layer using the oxidation resistant film as a mask. Forming an insulator layer in the epitaxial layer by thermal oxidation, and diffusing the isolation diffusion layer and the first external base diffusion layer into the epitaxial layer to form an isolation diffusion region and a first diffusion layer, respectively; Connecting at least the isolation diffusion region to the one conductivity type buried diffusion layer below the insulator layer as a base diffusion region; Forming a second conductivity type second external base region having a higher impurity concentration and a deeper diffusion layer than the intrinsic base region, and forming the first external base diffusion region and the second external base region Forming a first base diffusion region and the second base base region around the intrinsic base region while providing an overlap around the intrinsic base region and a method of manufacturing the semiconductor device. . 2. A step of selectively forming a reverse conductivity type buried diffusion layer and one conductivity type buried diffusion layer separated from the reverse conductivity type buried diffusion layer on a semiconductor substrate of one conductivity type, respectively. Forming a reverse conductivity type epitaxial layer on the semiconductor substrate, and forming an oxidation-resistant film pattern on a surface of the element forming region of the epitaxial layer excluding a region where a first external base diffusion layer is to be formed; A diffusion layer for isolation by selectively introducing an impurity of one conductivity type into a surface of the epitaxial layer in a predetermined region of a region not including the region where the first external base diffusion layer is to be formed and not covered by the oxidation resistant film pattern; And forming a first external base diffusion layer, and thermally oxidizing the epitaxial layer using the oxidation-resistant film pattern as a mask to form an insulator layer in the epitaxial layer;
The separation diffusion layer and the first external base diffusion layer are diffused into the epitaxial layer to form a separation diffusion region and a first external base diffusion region, respectively, and at least the separation diffusion region below the insulator layer is formed under the insulator layer. A step of connecting to a buried diffusion layer of one conductivity type; and forming an intrinsic base region of one conductivity type and a deeper diffusion layer having a higher impurity concentration than the intrinsic base region in predetermined regions of the element formation region of the epitaxial layer. A second external base region of a conductivity type is formed, the intrinsic base region is formed to be partially connected to the first external base diffusion region, and the intrinsic base region and the second external base region of the element forming region are formed. (1) At least the second
Forming an external base region and connecting the first external base diffusion region and the second external base region.