JP3104275B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semi-custom semiconductor integrated circuit (hereinafter, referred to as a semi-custom LSI) in which a plurality of types of transistor elements can be selected by changing contacts and wiring patterns.

[0002]

2. Description of the Related Art In a conventional semi-custom LSI, an undersubstrate formed by arranging a plurality of basic elements such as transistors, resistors and capacitors is prepared in advance, and wiring design and wiring formation after a contact forming step are performed. Since only the steps need to be performed, an LSI having desired specifications can be obtained in a short delivery time.

In a conventional method of constructing a semi-custom LSI, a plurality of cells, each of which can constitute only one kind of element in one field, are arranged and formed in advance on a base, and a desired cell is formed after a contact step. In order to realize the circuit described above, cells necessary for realizing the circuit are selected and wired to form an LSI.

[0004]

However, in the above-described conventional semiconductor integrated circuit, since only cells that can form only one type of element in one field are arranged on the base, selection of an element in one cell is performed. Since the type of cell is determined and formed only in the base step without any property, after the contact step, only cells necessary to realize a desired circuit are selected from a plurality of types of cells already formed. Therefore, there is a limit in the degree of freedom of cell arrangement and wiring in the wiring design.

[0005]

The semiconductor integrated circuit of the present invention, in order to solve the problems] were provided on the surface including the N ⁺ -type buried layer provided on one principal surface of the P-type silicon substrate, said N ⁺ -type buried layer N ^A- type epitaxial layer, a field oxide film that partitions an element formation region provided on the surface of the N ^- type epitaxial layer, a gate electrode provided on the element formation region via a gate oxide film, and a gate electrode. the N aligned ^- the first and second P ⁺ -type diffusion layer provided on type epitaxial layer, said first
Third P ⁺ type diffusion layer provided apart from the second P ⁺ -type diffusion layer
And continuously provided between the second and third P ⁺ -type diffusion layers.
Between the P-type diffusion layer and the second and third P ⁺ -type diffusion layers.
Wherein the N ⁺ diffusion layer provided on the P-type diffusion layer, the N ^- provided -type epitaxial layer reaches the N ⁺ -type buried layer N ⁺
A diffusion layer. Here, the first P ⁺ type diffusion
Surrounding the layer and the gate electrode and the second P ⁺ type extension.
A scattering layer can be provided. Or of the present invention
The semiconductor integrated circuit is provided on one main surface of a P-type silicon substrate
An N ⁺ -type buried layer and a surface provided with the N ⁺ -type buried layer
N ^- -type epitaxial layer, the N ^- type epitaxial
Field acid that partitions the device formation area provided on the surface of the layer
Oxide film and a gate oxide film on the element formation region.
Only the gate electrode, wherein in alignment with the gate electrode N ^-
And second P-type diffusion layers provided in a p-type epitaxial layer
And an N ⁺ diffusion layer provided in the second P-type diffusion layer.
The N ⁺ type buried layer is provided on the N ⁻ type epitaxial layer.
An N ⁺ diffusion layer that reaches the first and second P-type diffusion layers.
The diffused layer is formed as a source region of a P-channel MOS transistor and
Drain region or lateral PNP transistor
The N ⁺ diffusion layer as a collector region and an emitter region.
The base take-out area of the lateral PNP transistor
And there.

[0006]

Next, the present invention will be described with reference to the drawings.

FIGS. 1A and 1B are a schematic plan view and a cross-sectional view taken along the line AA 'showing a first embodiment of the present invention.

[0008] FIG. 1 (a), (b), the the N ⁺ -type buried layer 2 formed on one principal surface of the P-type silicon substrate 1, N on the surface including the N ⁺ -type buried layer 2 ^- The type epitaxial layer 3 is formed. Next, N ^- -type epitaxial layer 3 P-channel M
An N ⁺ type diffusion layer 4a serving as an OS transistor region;
N-transistor collector extraction region and lateral PNP
An N ⁺ -type diffusion layer 4b serving as a base region of a transistor is provided, a P-type diffusion layer 6 serving as a base region of an NPN transistor is formed, and a P-channel MOS transistor is formed on the N ⁺ -type diffusion layer 4a via a gate oxide film. The gate electrode 8 is formed. Thereafter, the NPN transistor serving as the emitter of the NPN transistor
^{A +} type diffusion layer 10 is provided, and P ^{+ serving as} the source and drain regions of the P-channel MOS transistor, the collector region and the emitter region of the lateral PNP transistor, and the base region of the NPN transistor in alignment with the gate electrode 8.
By providing the mold diffusion layers 14a, 14b, 14c,
P-channel MOS transistor 15, NPN transistor 16, lateral PNP in one field oxide film 18
A cell in which three types of transistor elements of the transistor 17 can be formed can be formed. In this cell, a necessary element is selected from the above three kinds of elements after the contact step, a contact is provided at the contact position, and wiring can be performed.

FIGS. 2 (a) and 2 (b) are a schematic plan view and a sectional view taken along the line BB 'showing a second embodiment of the present invention.

As shown in FIGS. 2A and 2B, a composite transistor is formed as in the first embodiment, and a P-channel MOS transistor 1 in one field oxide film 18 is formed.
5, three types of transistor elements, an NPN transistor 16, and a lateral PNP transistor 17.
The configuration is the same as that of the first embodiment except that a gate electrode 8 and a P ⁺ type diffusion layer 14b serving as an emitter region of the lateral PNP transistor are provided so as to surround a P ⁺ type diffusion layer 14a serving as a collector of the lateral PNP transistor. This has the advantage of improving the electrical characteristics of the lateral PNP transistor 17.

[0011]

As described above, the present invention provides a composite cell in which one of two types of bipolar transistor elements and one type of MOS transistor element can be constituted by changing the contact and wiring pattern in one cell. , The above-mentioned 3 after the contact step.
Since a necessary element can be selected from various types of transistor elements, there is an effect that the degree of freedom of cell arrangement and wiring in wiring design is increased.

[Brief description of the drawings]

FIG. 1 is a schematic plan view and a cross-sectional view taken along the line AA ′ showing a first embodiment of the present invention.

FIG. 2 is a schematic plan view and a cross-sectional view taken along the line BB 'showing a second embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 1 P type silicon substrate 2 N ⁺ type buried layer 3 N ⁻ type epitaxial layer 4 a, 4 b N ⁺ type diffusion layer 6 P type diffusion layer 8 Gate electrode 10 N ⁺ type diffusion layer 14 a, 14 b, 14 c P ⁺ type diffusion layer 15 P-channel MOS transistor 16 NPN transistor 17 Lateral PNP transistor 18 Field oxide film

Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/8249 H01L 27/06 H01L 27/118

Claims (3)

(57) [Claims] 1. An N.sup. ⁺ Substrate provided on one main surface of a P-type silicon substrate.
Buried layer, and N ⁻ provided on the surface including the N ⁺ buried layer.
-Type epitaxial layer, a field oxide film that partitions an element formation region provided on the surface of the N ⁻ -type epitaxial layer, a gate electrode provided on the element formation region via a gate oxide film, and matching with the gate electrode. The first and second P ⁺ -type diffusion layers provided in the N ⁻ -type epitaxial layer and the third P ⁺ -type layer provided separately from the second P ⁺ -type diffusion layer.
⁺ Type diffusion layer and the second and third P ⁺ type diffusion layers.
A P-type diffusion layer provided continuously, and the second and third P ⁺ -type
Semiconductor, characterized in that a provided -type epitaxial layer reaches the N ⁺ -type buried layer N ⁺ diffusion layer ^- and the N ⁺ diffusion layer in which the provided P-type diffusion layer of the diffusion layer, the N Integrated circuit. (2) The first P ⁺  Around the mold diffusion layer
The gate electrode and the second P ⁺  Mold diffusion layer is provided
2. The semiconductor integrated circuit according to claim 1, wherein: (3) N provided on one main surface of a P-type silicon substrate ⁺
Mold buried layer and the N ⁺  N provided on the surface including the mold buried layer ^-
Type epitaxial layer and the N ^-  Type epitaxial layer
Field oxide film that partitions the device formation area provided on the surface
And provided on the element forming region via a gate oxide film.
A gate electrode and the N ^-  Type d
First and second P-type diffusion layers provided on the epitaxial layer;
N provided in the second P-type diffusion layer ⁺  A diffusion layer;
^-  N on the epitaxial layer ⁺  Reaches the mold buried layer
N ⁺  A diffusion layer, wherein the first and second P-type diffusion layers are provided.
Are the source region and drain of the P-channel MOS transistor.
In-region or lateral PNP transistor collector
And an emitter region, ⁺  Lateral diffusion layer
The base extraction area of the PNP transistor
Characteristic semiconductor integrated circuit.