JP3104275B2 - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JP3104275B2 JP3104275B2 JP03073520A JP7352091A JP3104275B2 JP 3104275 B2 JP3104275 B2 JP 3104275B2 JP 03073520 A JP03073520 A JP 03073520A JP 7352091 A JP7352091 A JP 7352091A JP 3104275 B2 JP3104275 B2 JP 3104275B2
- Authority
- JP
- Japan
- Prior art keywords
- type
- layer
- diffusion layer
- epitaxial layer
- diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000009792 diffusion process Methods 0.000 claims description 45
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000005192 partition Methods 0.000 claims description 4
- 238000000605 extraction Methods 0.000 claims description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11896—Masterslice integrated circuits using combined field effect/bipolar technology
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体集積回路に関し、
特に複数種のトランジスタ素子をコンタクト及び配線パ
ターンの変更により選択可能なセミカスタム半導体集積
回路(以下セミカスタムLSIと記す)に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semi-custom semiconductor integrated circuit (hereinafter, referred to as a semi-custom LSI) in which a plurality of types of transistor elements can be selected by changing contacts and wiring patterns.
【0002】[0002]
【従来の技術】従来のセミカスタムLSIでは、トラン
ジスタ,抵抗,容量等の各々の基本素子を複数個配置し
て形成した下地基板をあらかじめ用意しておき、コンタ
クト形成工程以降の配線設計及び配線形成工程のみを実
施すればよいので所望の仕様を備えたLSIを短納期で
得ることができる。2. Description of the Related Art In a conventional semi-custom LSI, an undersubstrate formed by arranging a plurality of basic elements such as transistors, resistors and capacitors is prepared in advance, and wiring design and wiring formation after a contact forming step are performed. Since only the steps need to be performed, an LSI having desired specifications can be obtained in a short delivery time.
【0003】従来のセミカスタムLSIの構成方法で
は、あらかじめ下地に1つのフィールド内で1種類の素
子だけを構成できるセルを複数種類,複数個ずつ配置し
て形成しておき、コンタクト工程以降で所望の回路を実
現するために必要なセルを選択して配線させ、LSIを
構成していた。In a conventional method of constructing a semi-custom LSI, a plurality of cells, each of which can constitute only one kind of element in one field, are arranged and formed in advance on a base, and a desired cell is formed after a contact step. In order to realize the circuit described above, cells necessary for realizing the circuit are selected and wired to form an LSI.
【0004】[0004]
【発明が解決しようとする課題】しかしながら、上述し
た従来の半導体集積回路では、下地に1つのフィールド
内で1種類の素子だけを構成できるセルだけを配置させ
るため、1つのセル内で素子の選択性がなく、下地工程
でのみセルの種類が決定され、形成させるため、コンタ
クト工程以降では、既に形成された複数種類のセルの中
から所望の回路を実現させるために必要なセルを選択す
るだけなので、配線設計におけるセルの配置配線の自由
度に限界があった。However, in the above-described conventional semiconductor integrated circuit, since only cells that can form only one type of element in one field are arranged on the base, selection of an element in one cell is performed. Since the type of cell is determined and formed only in the base step without any property, after the contact step, only cells necessary to realize a desired circuit are selected from a plurality of types of cells already formed. Therefore, there is a limit in the degree of freedom of cell arrangement and wiring in the wiring design.
【0005】[0005]
【課題を解決するための手段】本発明の半導体集積回路
は、P型シリコン基板の一主面に設けたN+ 型埋込層
と、前記N+ 型埋込層を含む表面に設けたN- 型エピタ
キシャル層と、前記N-型エピタキシャル層の表面に設
けた素子形成領域を区画するフィールド酸化膜と、前記
素子形成領域上にゲート酸化膜を介して設けたゲート電
極と、前記ゲート電極に整合して前記N- 型エピタキシ
ャル層に設けた第1及び第2のP+ 型拡散層と、前記第
2のP + 型拡散層と離間して設けた第3のP + 型拡散層
と、前記第2及び第3のP + 型拡散層間に連続的に設け
たP型拡散層と、前記第2及び第3のP + 型拡散層間の
前記P型拡散層内に設けたN+ 拡散層と、前記N- 型エ
ピタキシャル層に設けて前記N+ 型埋込層に達するN+
拡散層とを備えている。ここで、前記第1のP + 型拡散
層を取り囲んで前記ゲート電極及び前記第2のP + 型拡
散層が設けられていることができる。 あるいは本発明の
半導体集積回路は、P型シリコン基板の一主面に設けた
N + 型埋込層と、前記N + 型埋込層を含む表面に設けた
N - 型エピタキシャル層と、前記N - 型エピタキシャル
層の表面に設けた素子形成領域を区画するフィールド酸
化膜と、前記素子形成領域上にゲート酸化膜を介して設
けたゲート電極と、前記ゲート電極に整合して前記N -
型エピタキシャル層に設けた第1及び第2のP型拡散層
と、前記第2のP型拡散層内に設けたN + 拡散層と、前
記N - 型エピタキシャル層に設けて前記N + 型埋込層に
達するN + 拡散層とを備え、前記第1及び第2のP型拡
散層をPチャネルMOSトランジスタのソース領域及び
ドレイン領域もしくはラテラルPNPトランジスタのコ
レクタ領域及びエミッタ領域とし、前記N + 拡散層をラ
テラルPNPトランジスタのベース取出し領域としたこ
とにある。 The semiconductor integrated circuit of the present invention, in order to solve the problems] were provided on the surface including the N + -type buried layer provided on one principal surface of the P-type silicon substrate, said N + -type buried layer N A- type epitaxial layer, a field oxide film that partitions an element formation region provided on the surface of the N - type epitaxial layer, a gate electrode provided on the element formation region via a gate oxide film, and a gate electrode. the N aligned - the first and second P + -type diffusion layer provided on type epitaxial layer, said first
Third P + type diffusion layer provided apart from the second P + -type diffusion layer
And continuously provided between the second and third P + -type diffusion layers.
Between the P-type diffusion layer and the second and third P + -type diffusion layers.
Wherein the N + diffusion layer provided on the P-type diffusion layer, the N - provided -type epitaxial layer reaches the N + -type buried layer N +
A diffusion layer. Here, the first P + type diffusion
Surrounding the layer and the gate electrode and the second P + type extension.
A scattering layer can be provided. Or of the present invention
The semiconductor integrated circuit is provided on one main surface of a P-type silicon substrate
An N + -type buried layer and a surface provided with the N + -type buried layer
N - -type epitaxial layer, the N - type epitaxial
Field acid that partitions the device formation area provided on the surface of the layer
Oxide film and a gate oxide film on the element formation region.
Only the gate electrode, wherein in alignment with the gate electrode N -
And second P-type diffusion layers provided in a p-type epitaxial layer
And an N + diffusion layer provided in the second P-type diffusion layer.
The N + type buried layer is provided on the N − type epitaxial layer.
An N + diffusion layer that reaches the first and second P-type diffusion layers.
The diffused layer is formed as a source region of a P-channel MOS transistor and
Drain region or lateral PNP transistor
The N + diffusion layer as a collector region and an emitter region.
The base take-out area of the lateral PNP transistor
And there.
【0006】[0006]
【実施例】次に、本発明について図面を参照して説明す
る。Next, the present invention will be described with reference to the drawings.
【0007】図1(a),(b)は本発明の第1の実施
例を示す模式的平面図及びA−A′線断面図である。FIGS. 1A and 1B are a schematic plan view and a cross-sectional view taken along the line AA 'showing a first embodiment of the present invention.
【0008】図1(a),(b)に示すように、P型シ
リコン基板1の一主面にN+ 型埋込層2を設け、N+ 型
埋込層2を含む表面にN- 型エピタキシャル層3を形成
する。次に、N- 型エピタキシャル層3にPチャネルM
OSトランジスタ領域となるN+ 型拡散層4aと、NP
Nトランジスタのコレクタ引出領域及びラテラルPNP
トランジスタのベース領域となるN+ 型拡散層4bを設
け、NPNトランジスタのベース領域となるP型拡散層
6を形成し、N+ 型拡散層4a上にゲート酸化膜を介し
てPチャネルMOSトランジスタのゲート電極8を形成
する。この後、NPNトランジスタのエミッタとなるN
+ 型拡散層10を設け、さらにゲート電極8に整合して
PチャネルMOSトランジスタのソース,ドレイン領域
とラテラルPNPトランジスタのコレクタ領域,エミッ
タ領域及びNPNトランジスタのベース領域となるP+
型拡散層14a,14b,14cを設けることにより1
つのフィールド酸化膜18内にPチャネルMOSトラン
ジスタ15、NPNトランジスタ16、ラテラルPNP
トランジスタ17の3種類のトランジスタ素子を構成す
ることができるセルを形成することができる。このセル
は、コンタクト工程以降で前記3種類の素子から必要な
素子を選択し、そのコンタクト位置にコンタクトを設
け、配線させることができる。[0008] FIG. 1 (a), (b), the the N + -type buried layer 2 formed on one principal surface of the P-type silicon substrate 1, N on the surface including the N + -type buried layer 2 - The type epitaxial layer 3 is formed. Next, N - -type epitaxial layer 3 P-channel M
An N + type diffusion layer 4a serving as an OS transistor region;
N-transistor collector extraction region and lateral PNP
An N + -type diffusion layer 4b serving as a base region of a transistor is provided, a P-type diffusion layer 6 serving as a base region of an NPN transistor is formed, and a P-channel MOS transistor is formed on the N + -type diffusion layer 4a via a gate oxide film. The gate electrode 8 is formed. Thereafter, the NPN transistor serving as the emitter of the NPN transistor
A + type diffusion layer 10 is provided, and P + serving as the source and drain regions of the P-channel MOS transistor, the collector region and the emitter region of the lateral PNP transistor, and the base region of the NPN transistor in alignment with the gate electrode 8.
By providing the mold diffusion layers 14a, 14b, 14c,
P-channel MOS transistor 15, NPN transistor 16, lateral PNP in one field oxide film 18
A cell in which three types of transistor elements of the transistor 17 can be formed can be formed. In this cell, a necessary element is selected from the above three kinds of elements after the contact step, a contact is provided at the contact position, and wiring can be performed.
【0009】図2(a),(b)は本発明の第2の実施
例を示す模式的平面図及びB−B′線断面図である。FIGS. 2 (a) and 2 (b) are a schematic plan view and a sectional view taken along the line BB 'showing a second embodiment of the present invention.
【0010】図2(a),(b)に示すように、第1の
実施例と同様に複合トランジスタを形成し、1つのフィ
ールド酸化膜18内のPチャネルMOSトランジスタ1
5,NPNトランジスタ16,ラテラルPNPトランジ
スタ17の3種類のトランジスタ素子を構成している。
ラテラルPNPトランジスタのコレクタとなるP+ 型拡
散層14aを取り囲むようにゲート電極8及びラテラル
PNPトランジスタのエミッタ領域となるP+ 型拡散層
14bを設けた以外は第1の実施例と同様の構成を有し
ており、ラテラルPNPトランジスタ17の電気的特性
を向上させる利点がある。As shown in FIGS. 2A and 2B, a composite transistor is formed as in the first embodiment, and a P-channel MOS transistor 1 in one field oxide film 18 is formed.
5, three types of transistor elements, an NPN transistor 16, and a lateral PNP transistor 17.
The configuration is the same as that of the first embodiment except that a gate electrode 8 and a P + type diffusion layer 14b serving as an emitter region of the lateral PNP transistor are provided so as to surround a P + type diffusion layer 14a serving as a collector of the lateral PNP transistor. This has the advantage of improving the electrical characteristics of the lateral PNP transistor 17.
【0011】[0011]
【発明の効果】以上説明したように本発明は、コンタク
ト及び配線パターンを変更することにより2種類のバイ
ポーラトランジスタ素子と1種類のMOSトランジスタ
素子のいづれかが構成可能となる複合セルを1つのセル
内に構成することにより、コンタクト工程以降で上記3
種類のトランジスタ素子から必要な素子を選択できるた
め、配線設計におけるセルの配置,配線の自由度が増す
という効果を有する。As described above, the present invention provides a composite cell in which one of two types of bipolar transistor elements and one type of MOS transistor element can be constituted by changing the contact and wiring pattern in one cell. , The above-mentioned 3 after the contact step.
Since a necessary element can be selected from various types of transistor elements, there is an effect that the degree of freedom of cell arrangement and wiring in wiring design is increased.
【図1】本発明の第1の実施例を示す模式的平面図及び
A−A′線断面図である。FIG. 1 is a schematic plan view and a cross-sectional view taken along the line AA ′ showing a first embodiment of the present invention.
【図2】本発明の第2の実施例を示す模式的平面図及び
B−B′線断面図である。FIG. 2 is a schematic plan view and a cross-sectional view taken along the line BB 'showing a second embodiment of the present invention.
1 P型シリコン基板 2 N+ 型埋込層 3 N- 型エピタキシャル層 4a,4b N+ 型拡散層 6 P型拡散層 8 ゲート電極 10 N+ 型拡散層 14a,14b,14c P+ 型拡散層 15 PチャネルMOSトランジスタ 16 NPNトランジスタ 17 ラテラルPNPトランジスタ 18 フィールド酸化膜Reference Signs List 1 P type silicon substrate 2 N + type buried layer 3 N − type epitaxial layer 4 a, 4 b N + type diffusion layer 6 P type diffusion layer 8 Gate electrode 10 N + type diffusion layer 14 a, 14 b, 14 c P + type diffusion layer 15 P-channel MOS transistor 16 NPN transistor 17 Lateral PNP transistor 18 Field oxide film
フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 21/8249 H01L 27/06 H01L 27/118 Continued on the front page (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 21/8249 H01L 27/06 H01L 27/118
Claims (3)
型埋込層と、前記N+ 型埋込層を含む表面に設けたN-
型エピタキシャル層と、前記N- 型エピタキシャル層の
表面に設けた素子形成領域を区画するフィールド酸化膜
と、前記素子形成領域上にゲート酸化膜を介して設けた
ゲート電極と、前記ゲート電極に整合して前記N- 型エ
ピタキシャル層に設けた第1及び第2のP+ 型拡散層
と、前記第2のP + 型拡散層と離間して設けた第3のP
+ 型拡散層と、前記第2及び第3のP + 型拡散層間に連
続的に設けたP型拡散層と、前記第2及び第3のP + 型
拡散層間の前記P型拡散層内に設けたN+ 拡散層と、前
記N- 型エピタキシャル層に設けて前記N+ 型埋込層に
達するN+ 拡散層とを備えたことを特徴とする半導体集
積回路。1. An N.sup. + Substrate provided on one main surface of a P-type silicon substrate.
Buried layer, and N − provided on the surface including the N + buried layer.
-Type epitaxial layer, a field oxide film that partitions an element formation region provided on the surface of the N − -type epitaxial layer, a gate electrode provided on the element formation region via a gate oxide film, and matching with the gate electrode. The first and second P + -type diffusion layers provided in the N − -type epitaxial layer and the third P + -type layer provided separately from the second P + -type diffusion layer.
+ Type diffusion layer and the second and third P + type diffusion layers.
A P-type diffusion layer provided continuously, and the second and third P + -type
Semiconductor, characterized in that a provided -type epitaxial layer reaches the N + -type buried layer N + diffusion layer - and the N + diffusion layer in which the provided P-type diffusion layer of the diffusion layer, the N Integrated circuit.
記ゲート電極及び前記第2のPThe gate electrode and the second P ++ 型拡散層が設けられて Mold diffusion layer is provided
いることを特徴とする請求項1記載の半導体集積回路。2. The semiconductor integrated circuit according to claim 1, wherein:
型埋込層と、前記NMold buried layer and the N ++ 型埋込層を含む表面に設けたN N provided on the surface including the mold buried layer --
型エピタキシャル層と、前記NType epitaxial layer and the N -- 型エピタキシャル層の Type epitaxial layer
表面に設けた素子形成領域を区画するフィールド酸化膜Field oxide film that partitions the device formation area provided on the surface
と、前記素子形成領域上にゲート酸化膜を介して設けたAnd provided on the element forming region via a gate oxide film.
ゲート電極と、前記ゲート電極に整合して前記NA gate electrode and the N -- 型エ Type d
ピタキシャル層に設けた第1及び第2のP型拡散層と、First and second P-type diffusion layers provided on the epitaxial layer;
前記第2のP型拡散層内に設けたNN provided in the second P-type diffusion layer ++ 拡散層と、前記N A diffusion layer;
-- 型エピタキシャル層に設けて前記N N on the epitaxial layer ++ 型埋込層に達す Reaches the mold buried layer
るNN ++ 拡散層とを備え、前記第1及び第2のP型拡散層 A diffusion layer, wherein the first and second P-type diffusion layers are provided.
をPチャネルMOSトランジスタのソース領域及びドレAre the source region and drain of the P-channel MOS transistor.
イン領域もしくはラテラルPNPトランジスタのコレクIn-region or lateral PNP transistor collector
タ領域及びエミッタ領域とし、前記NAnd an emitter region, ++ 拡散層をラテラ Lateral diffusion layer
ルPNPトランジスタのベース取出し領域としたことをThe base extraction area of the PNP transistor
特徴とする半導体集積回路。Characteristic semiconductor integrated circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP03073520A JP3104275B2 (en) | 1991-04-08 | 1991-04-08 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP03073520A JP3104275B2 (en) | 1991-04-08 | 1991-04-08 | Semiconductor integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04309264A JPH04309264A (en) | 1992-10-30 |
JP3104275B2 true JP3104275B2 (en) | 2000-10-30 |
Family
ID=13520602
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP03073520A Expired - Fee Related JP3104275B2 (en) | 1991-04-08 | 1991-04-08 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3104275B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0575877U (en) * | 1992-03-11 | 1993-10-15 | 松下冷機株式会社 | Vending machine display equipment |
KR200487588Y1 (en) * | 2015-09-30 | 2018-10-10 | 민경옥 | Functional Cap |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100455694B1 (en) * | 2001-11-13 | 2004-11-15 | 주식회사 케이이씨 | Lateral transistor and its manufacturing method |
-
1991
- 1991-04-08 JP JP03073520A patent/JP3104275B2/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0575877U (en) * | 1992-03-11 | 1993-10-15 | 松下冷機株式会社 | Vending machine display equipment |
KR200487588Y1 (en) * | 2015-09-30 | 2018-10-10 | 민경옥 | Functional Cap |
Also Published As
Publication number | Publication date |
---|---|
JPH04309264A (en) | 1992-10-30 |
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