KR100520190B1 - Memory cell array - Google Patents
Memory cell array Download PDFInfo
- Publication number
- KR100520190B1 KR100520190B1 KR1019980020867A KR19980020867A KR100520190B1 KR 100520190 B1 KR100520190 B1 KR 100520190B1 KR 1019980020867 A KR1019980020867 A KR 1019980020867A KR 19980020867 A KR19980020867 A KR 19980020867A KR 100520190 B1 KR100520190 B1 KR 100520190B1
- Authority
- KR
- South Korea
- Prior art keywords
- memory cell
- cell array
- charge storage
- bit line
- active region
- Prior art date
Links
- 238000000034 method Methods 0.000 claims abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 238000002955 isolation Methods 0.000 abstract description 8
- 239000004065 semiconductor Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 230000000295 complement effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Semiconductor Memories (AREA)
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
본 발명은 메모리 셀 어레이에 관한 것으로서, 특히 공정 마진 및 콘택 접합부의 오버레이 마진을 향상시킬 수 있는 메모리 셀 어레이에 관한 것이다.The present invention relates to a memory cell array, and more particularly, to a memory cell array capable of improving process margins and overlay margins of contact junctions.
2. 발명이 해결하고자 하는 기술적 과제2. Technical problem to be solved by the invention
종래의 일자형 또는 T자형 셀 구조는 비트라인 및 전하저장 전극을 형성하기 위해서는 넓은 액티브 영역이 필요하거나 조밀하게 형성하기가 어려운 문제점이 발생되었다.Conventional straight or T-shaped cell structures require a large active area or difficult to form densely in order to form bit lines and charge storage electrodes.
3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention
본 발명은 소자분리 패턴(isolation patten)을 갈매기 날개 형상과 같이 형성하고 게이트 전극, 비트라인 및 저장 전극을 각각 수직방향, 수평방향 및 수직방향으로 서로 겹치지 않게 배치하므로서, 콘택 접합부의 오버레이 마진을 향상시키고자 한다.The present invention improves the overlay margin of the contact junction by forming an isolation pattern like a chevron wing shape and arranging the gate electrode, the bit line and the storage electrode so as not to overlap each other in the vertical, horizontal and vertical directions, respectively. I want to.
4. 발명의 중요한 용도4. Important uses of the invention
모든 반도체 소자의 메모리 셀 어레이.Memory cell array of all semiconductor devices.
Description
본 발명은 메모리 셀 어레이에 관한 것으로서, 특히 공정 마진 및 콘택 접합부의 오버레이 마진을 향상시킬 수 있는 메모리 셀 어레이에 관한 것이다.The present invention relates to a memory cell array, and more particularly, to a memory cell array capable of improving process margins and overlay margins of contact junctions.
종래의 메모리 셀 어레이에서 액티브 영역을 형성하기 위한 소자분리 패턴의 구조는 일자형 구조 또는 T자형 구조를 갖는데, 도 1을 통해 설명하면 다음과 같다.A device isolation pattern for forming an active region in a conventional memory cell array has a straight or T-shaped structure, which will be described below with reference to FIG. 1.
일자형 구조는 도 1(a)에 도시된 바와 같이 비트라인 콘택(13) 및 전하저장 전극용 콘택(12)이 일자형 구조의 액티브 영역(11)에 동시에 형성된다. 이와 같은 구조에서 상기 비트라인 콘택(13) 및 전하저장 전극용 콘택(12)이 일자형 구조의 액티브 영역에 동시에 형성되므로, 두 전극을 모두 형성하기 위해서는 넓은 액티브 영역이 필요하게 된다.In the straight structure, as shown in FIG. 1A, the bit line contact 13 and the charge storage electrode contact 12 are simultaneously formed in the active region 11 of the straight structure. In this structure, since the bit line contact 13 and the charge storage electrode contact 12 are simultaneously formed in the active region of the linear structure, a wide active region is required to form both electrodes.
따라서 도 1(b)에 도시된 바와 같이 상기 비트라인 콘택(13) 및 전하저장 전극용 콘택(12)이 서로 어긋나게 접합 영역을 형성하도록 배열된 T자형 구조의 메모리 셀이 상술한 일자형 구조의 단점을 보완할 수 있다. 그러나 T자형 구조의 메모리 셀은 반복적으로 배열할 때 조밀하게 배열하기 어려운 문제점이 도출되므로 한정된 면적에 많은 셀을 배열하여야 하는 고집적 소자에는 적합하지 않다.Therefore, as illustrated in FIG. 1B, the T-shaped memory cell arranged such that the bit line contact 13 and the charge storage electrode contact 12 are alternately formed to form a junction region is a disadvantage of the above-described straight structure. Can complement. However, the T-shaped memory cells are difficult to be densely arranged when repeatedly arranged, and thus are not suitable for highly integrated devices in which many cells must be arranged in a limited area.
따라서, 본 발명은 상술한 문제점을 해결하기 위해 소자분리 패턴(isolation patten)을 갈매기 날개 형상과 같이 형성하고 게이트 전극, 비트라인 및 전하저장 전극을 각각 수직방향, 수평방향 및 수직방향으로 서로 겹치지 않게 배치하므로서, 콘택 접합부의 오버레이 마진을 향상시키는데 그 목적이 있다.Therefore, in order to solve the above problems, the present invention forms an isolation pattern like a chevron wing shape and does not overlap the gate electrode, the bit line and the charge storage electrode with each other in the vertical, horizontal and vertical directions, respectively. The purpose is to improve the overlay margin of the contact junction.
상술한 목적을 달성하기 위한 본 발명은 갈매기 날개 형상을 이루며 실리콘 기판에 형성된 다수의 액티브 영역과, 상기 액티브 영역의 중심부에 형성된 다수의 비트라인 콘택과, 상기 액티브 영역의 양 가장자리에 형성된 다수의 전하저장 전극용 콘택과, 상기 다수의 액티브 영역상에 형성되며 종방향으로 연결되어 워드라인으로 사용되는 다수의 게이트 전극과, 상기 다수의 비트라인 콘택의 상부를 횡방향으로 연결하여 형성된 다수의 비트라인과, 상기 다수의 전하저장 전극용 콘택의 상부를 종방향으로 연결하여 형성된 다수의 전하저장 전극을 포함하여 구성된 것을 특징으로 한다.The present invention for achieving the above object has a plurality of active regions formed in the silicon substrate in the shape of a seagull wing, a plurality of bit line contacts formed in the center of the active region, a plurality of charges formed on both edges of the active region A plurality of bit lines formed on the storage electrode contacts, a plurality of gate electrodes formed on the plurality of active regions and connected in a longitudinal direction to serve as word lines, and a plurality of bit lines formed by connecting upper portions of the plurality of bit line contacts in a transverse direction; And a plurality of charge storage electrodes formed by connecting upper portions of the plurality of charge storage electrode contacts in a longitudinal direction.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2는 본 발명에 따른 메모리 셀 어레이를 설명하기 위한 레이아웃도이다.2 is a layout diagram illustrating a memory cell array according to the present invention.
본 발명에 따른 메모리 셀 어레이는 실리콘 기판 상에 다수의 갈매기 날개 형상의 소자분리 패턴(21)을 형성하여 액티브 영역을 정의하며, 상기 다수의 액티브 영역(21)은 서로 인접하는 액티브 영역(21)과 반대방향으로 일정한 규칙에 따라 지그재그로 엇갈리게 배열된다.The memory cell array according to the present invention defines an active region by forming a plurality of chevron-shaped device isolation patterns 21 on a silicon substrate, and the plurality of active regions 21 are adjacent to each other. They are staggered and staggered according to a certain rule in the opposite direction.
비트라인(24)은 다수의 액티브 영역(21)의 중심부에 다수의 비트라인 콘택(23)를 통해 드레인 영역과 연결되도록 형성되는데, 하나의 비트라인(24)은 상기 다수의 비트라인 콘택(23) 중 횡방향으로 배열된 비트라인 콘택들(23) 윗쪽에 형성되며, 전체 메모리 셀 어레이 영역에 다수개 형성된다.The bit line 24 is formed to be connected to the drain region through a plurality of bit line contacts 23 at the center of the plurality of active regions 21, and one bit line 24 is connected to the plurality of bit line contacts 23. ) Is formed above the bit line contacts 23 arranged in the horizontal direction, and a plurality of the plurality of contact lines are formed in the entire memory cell array region.
게이트 전극(25)은 액티브 영역(21)에 종방향으로 수직되게 배열되면서 단위 셀과 단위 셀 사이를 약간 꺽이게 배열되어 다수개가 형성되는데, 상기 다수의 게이트 전극(25)은 워드라인으로 사용된다.The gate electrodes 25 are arranged vertically perpendicular to the active region 21 while being slightly bent between the unit cells and the unit cells, and a plurality of gate electrodes 25 are formed. The plurality of gate electrodes 25 are used as word lines. .
전하저장 전극(26)은 다수의 액티브 영역(21)의 양쪽 끝부분에 형성된 전하저장 전극용 콘택(22)을 통해 소오스 영역과 연결되도록 형성되는데, 상기 전하저장 전극(26)은 상기 게이트 전극(25)과 평행되게 종방향으로 배열되며, 직사각형 형태로 다수개가 배열된다.The charge storage electrode 26 is formed to be connected to the source region through the charge storage electrode contacts 22 formed at both ends of the plurality of active regions 21, and the charge storage electrode 26 is the gate electrode ( It is arranged in the longitudinal direction parallel to 25), and a plurality is arranged in a rectangular shape.
이와 같이 본 발명은 액티브 영역을 갈매기 날개 형상 또는 V자 형태로 반복적으로 형성하여 주어진 칩 면적에 최대한 조밀하게 배열하므로서 게이트 전극, 비트라인 및 전하저장 전극을 종방향/횡방향/종방향으로 각각 서로 전기적으로 분리되게 배열할 수 있으므로 콘택 오버랩(contact overlap) 마진을 향상할 수 있다.As described above, the present invention repeatedly forms the active region in the shape of a chevron or V-shape, and arranges the gate electrode, the bit line, and the charge storage electrode in the longitudinal direction, the horizontal direction, and the longitudinal direction, respectively, as closely as possible. It can be arranged electrically separated to improve contact overlap margin.
또한, 액티브 영역을 형성하기 위한 소자분리 패턴(31)을 도시된 도 3과 같이 중심부와 끝부분을 사각형 형태로 형성하여 소자분리 패턴 노광 작업시 마진을 향상시킬 수 있다. In addition, the device isolation pattern 31 for forming the active region may be formed in the center and the end portion in the shape of a quadrangle as shown in FIG. 3 to improve the margin during the device isolation pattern exposure operation.
상술한 바와 같이, 본 발명에 의하면 액티브 영역을 갈매기 날개 형상 또는 V자 형태로 반복적으로 형성하여 주어진 칩 면적에 최대한 조밀하게 배열하므로서 게이트 전극, 비트라인 및 전하저장 전극을 종방향/횡방향/종방향으로 각각 서로 전기적으로 분리되게 배열할 수 있으므로 공정 진행시 오버레이 마진을 향상시키고, 정해진 면적에 최대한 셀을 집적할 수 있는 반복적인 구조를 가질수 있으므로 고집적 소자의 셀 구조로서 탁월한 효과를 발휘한다.As described above, according to the present invention, the gate electrode, the bit line, and the charge storage electrode are longitudinally / laterally / vertically formed by repeatedly forming the active region in the shape of a chevron or V-shape to arrange as compactly as possible in a given chip area. Each of them can be arranged to be electrically separated from each other in the direction to improve the overlay margin during the process, it can have a repetitive structure that can be integrated into the cell in a predetermined area as the cell structure of the highly integrated device has an excellent effect.
도 1(a)는 종래의 일자형 셀 구조를 나타낸 도면.1 (a) is a diagram showing a conventional straight cell structure.
도 1(b)는 종래의 T자형 셀 구조를 나타낸 도면.Figure 1 (b) is a diagram showing a conventional T-shaped cell structure.
도 2는 본 발명에 따른 메모리 셀 어레이의 레이아웃도.2 is a layout diagram of a memory cell array in accordance with the present invention.
도 3은 본 발명에 적용되는 또다른 소자분리 패턴을 나타낸 도면.Figure 3 is a view showing another device isolation pattern applied to the present invention.
〈도면의 주요 부분에 대한 부호 설명〉<Description of Signs of Major Parts of Drawings>
11, 21 및 31 : 소자분리 패턴(액티브 영역)11, 21, and 31: device isolation pattern (active area)
12 및 22 : 전하저장 전극용 콘택 13 및 23 : 비트라인 콘택12 and 22: contacts for charge storage electrodes 13 and 23: bitline contacts
24 : 비트라인 25 : 게이트 전극24: bit line 25: gate electrode
26 : 전하저장 전극26: charge storage electrode
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980020867A KR100520190B1 (en) | 1998-06-05 | 1998-06-05 | Memory cell array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980020867A KR100520190B1 (en) | 1998-06-05 | 1998-06-05 | Memory cell array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20000000925A KR20000000925A (en) | 2000-01-15 |
| KR100520190B1 true KR100520190B1 (en) | 2006-05-03 |
Family
ID=19538462
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980020867A KR100520190B1 (en) | 1998-06-05 | 1998-06-05 | Memory cell array |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100520190B1 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000020762A (en) * | 1998-09-23 | 2000-04-15 | 윤종용 | Semiconductor memory device |
| KR20030073875A (en) * | 2002-03-13 | 2003-09-19 | 주식회사 하이닉스반도체 | Method for forming isolation pattern of semiconductor device |
| US7208373B2 (en) * | 2005-05-27 | 2007-04-24 | Infineon Technologies Ag | Method of forming a memory cell array and a memory cell array |
| KR100706817B1 (en) * | 2006-03-13 | 2007-04-12 | 삼성전자주식회사 | Nonvolatile memory device and method for forming the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950000851A (en) * | 1993-06-19 | 1995-01-03 | 베르너 발데크 | Resorption Inhibition Method of Mobile Dye in Washing Liquid |
| KR950011636A (en) * | 1993-10-06 | 1995-05-15 | 전성원 | Alloy composition for automobile valve seat |
| KR970018246A (en) * | 1995-09-21 | 1997-04-30 | 김광호 | Manufacturing Method of Semiconductor Memory Cell |
| US5734184A (en) * | 1995-12-21 | 1998-03-31 | Texas Instruments Incorporated | DRAM COB bit line and moat arrangement |
-
1998
- 1998-06-05 KR KR1019980020867A patent/KR100520190B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950000851A (en) * | 1993-06-19 | 1995-01-03 | 베르너 발데크 | Resorption Inhibition Method of Mobile Dye in Washing Liquid |
| KR950011636A (en) * | 1993-10-06 | 1995-05-15 | 전성원 | Alloy composition for automobile valve seat |
| KR970018246A (en) * | 1995-09-21 | 1997-04-30 | 김광호 | Manufacturing Method of Semiconductor Memory Cell |
| US5734184A (en) * | 1995-12-21 | 1998-03-31 | Texas Instruments Incorporated | DRAM COB bit line and moat arrangement |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20000000925A (en) | 2000-01-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100566774B1 (en) | Serial MRAM Device | |
| US6026010A (en) | Semiconductor memory device with bit line contact areas and storage capacitor contact areas | |
| KR100299879B1 (en) | Ultra-high density alternating metal virtual ground ROM | |
| KR950012576A (en) | Semiconductor memory | |
| US4631705A (en) | Semiconductor integrated circuit memory device | |
| JP2638487B2 (en) | Semiconductor storage device | |
| JPH0372675A (en) | Semiconductor storage device | |
| KR980012556A (en) | All CMOS SRAM cells containing Vcc and Vss buses on both sides of each complementary data line on a single level | |
| KR940012634A (en) | Semiconductor memory device | |
| KR100520190B1 (en) | Memory cell array | |
| KR100258345B1 (en) | Semiconductor memory device having improved power line architecture | |
| EP0156135A2 (en) | Preconditioned memory cell | |
| KR930010083B1 (en) | Semiconductor integrated circuit of standard cell system | |
| KR920010848B1 (en) | Semiconductor memory device | |
| WO2001099152A2 (en) | Buried bit line-field plate isolation defined dram cell active areas | |
| KR100440410B1 (en) | Texas instruments incorporated | |
| KR20110093434A (en) | Semiconductor cell structure, semiconductor device comprising the semiconductor cell structure, and semiconductor module comprising the semiconductor device | |
| KR910001767A (en) | Semiconductor memory | |
| KR910001186B1 (en) | High density high speed read only semiconductor memory device | |
| KR100390976B1 (en) | Memory device | |
| US5748549A (en) | Semiconductor memory device | |
| KR100237628B1 (en) | Semiconductor device | |
| KR0172841B1 (en) | Semiconductor device | |
| KR970018577A (en) | Open bit line semiconductor device | |
| JPH05291521A (en) | Manufacture of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20100825 Year of fee payment: 6 |
|
| LAPS | Lapse due to unpaid annual fee |