KR940012634A

KR940012634A - Semiconductor memory device

Info

Publication number: KR940012634A
Application number: KR1019930025743A
Authority: KR
Inventors: 요시노리 오까지마
Original assignee: 세끼자와 다다시; 후지쓰 가부시끼가이샤
Priority date: 1992-11-30
Filing date: 1993-11-30
Publication date: 1994-06-24
Also published as: US5526303A; JPH06169071A; KR0153786B1

Abstract

본 발명의 반도체 메모리장치는 SRAM에 관한 것으로 메모리셀에 의해 점유되는 면적을 소정 범위내로 유지시키면서 전송트랜지스터의 포화드레인 전류를 위해 구동트랜지스터의 포화드레인 전류를 충분히 크게 확보하는데 목적이 있고, 제1트랜지스터의 게이트 전극을 포함하며, 반도체 기판상의 정해진 방향으로 연장되며 또한 정해진 방향의 대각선으로 굽혀져 제1트랜지스터 영역에서 넓어진 띠형 워드라인과, 상기 제1트랜지스터의 소오스/드레인영역을 가지며 또한 소오스/드레인 영역들간에 형성되어 워드라인들과 교차하는 능동영역으로 된 메모리셀을 갖는다.The semiconductor memory device of the present invention relates to an SRAM, and has an object of ensuring a saturation drain current of a driving transistor sufficiently large for a saturation drain current of a transfer transistor while maintaining an area occupied by a memory cell within a predetermined range. And a band word line extending in a predetermined direction on the semiconductor substrate and bent diagonally in a predetermined direction on the semiconductor substrate to be widened in the first transistor region, and having a source / drain region of the first transistor and a source / drain region. It has a memory cell formed between the two active regions that intersect the word lines.

Description

Semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 일실시예의 SRAM의 메모리셀의 전송 및 구동트랜지스터들의 채널 영역 및 소오스/드레인 영역이 형성된 능동영역, 띠형 워드라인 및 게이트 전극의 배치도.2 is a layout view of an active region, a band-shaped word line, and a gate electrode in which channel regions and source / drain regions of transfer and driving transistors of a memory cell of an SRAM according to an embodiment of the present invention are formed.

제3도는 본 발명의 일실시예의 SRAM의 메모리셀의 제1전원라인과 각 비트라인을 접속하는 각 접속부와 그들의 비트라인의 배치도.3 is a layout view of each connection portion and their bit lines connecting the first power supply line and each bit line of the memory cell of the SRAM according to the embodiment of the present invention.

제4도는 본 발명의 일실시예의 SRAM의 메모리셀의 제1부하소자, 제2부하소자 및 제2전원라인의 배치도.4 is a layout view of a first load element, a second load element, and a second power supply line of a memory cell of an SRAM of an embodiment of the present invention.

제5도는 제2∼4도의 패턴배치가 겹칠때의 본 발명의 상기 실시예의 SRAM의 메모리셀의 선 A-A를 따라 취한 단면도.5 is a cross-sectional view taken along line A-A of the memory cell of the SRAM of the embodiment of the present invention when the pattern arrangements of FIGS.

제6A는 제1 및 제2부하로서 전계효과 트랜지스터를 사용하는 본 발명의 상기 실시예의 SRAM의 메모리셀의 회로 개통도.6A is a circuit opening diagram of a memory cell of the SRAM of the embodiment of the present invention using the field effect transistor as the first and second loads.

제6B도는 제1 및 제2부하로서 저항을 사용하는 본 발명의 상기 실시예의 SRAM의 메모리셀의 회로 개통도.Fig. 6B is a circuit opening diagram of a memory cell of an SRAM of the embodiment of the present invention using resistors as first and second loads.

Claims

A band-shaped first word line including a gate electrode of the first transistor and extending in a predetermined direction on the semiconductor substrate and bent diagonally in a predetermined direction and widening in the first transistor region, and a source / drain region of the first transistor; And a memory cell having an active region intersecting a word line formed between the source / drain regions.

The transistor of claim 1, wherein the active region extends to a second transistor region, has a source / drain region of the second transistor, and crosses the gate electrode of the second transistor formed between the source / drain regions of the second transistor. And a width of an active region perpendicular to an extension direction in the first transistor region is narrower than a width of the second transistor region.

A band-shaped first word line including a first gate electrode of the first transistor and extending in a predetermined direction on the semiconductor substrate and bent diagonally in a predetermined direction and widening in the first transistor region, and a second gate of the third transistor; A second word line including an electrode, disposed parallel to the first word line and bent diagonally in a predetermined direction and widening in the third transistor region, and a source / drain region of the first transistor; A band-shaped first active region crossing the first word line formed between the source / drain regions of the first transistor and extending from the first word line toward the second word line, and the source / drain of the third transistor; Intersect the second word line formed between the drain regions, and extend from the second word line toward the first word line; The second active region from the first active region to cross the first active region and to contact the second active region in the second transistor region between the band-shaped second active region and the first and second word lines. The first active region from the second active region to cross the second active region and to contact the first active region in a fourth transistor region extending toward the second gate electrode and the first and second word lines; And a memory cell comprising a fourth gate electrode extending toward the surface of the semiconductor memory device.

4. The width of the first active region crossing the first word line is smaller than the width of the first active region crossing the first gate electrode, and wherein the second crosses the second word line. The width of the active region is narrower than the width of the second active region crossing the second gate electrode.

4. The first power supply line of claim 3, wherein the first power supply line extends in a predetermined direction within an area between the first and second word lines, and a source / drain area of the second transistor is disposed in a central portion of the memory cell. And a second opening for connecting the source / drain region of the fourth transistor to the first power supply line.

6. The semiconductor memory device of claim 5, wherein the memory cell is point symmetrical about an axis perpendicular to its central portion.

The method of claim 3, wherein the second power supply line is connected through the source / drain region and the first load of the second transistor, and the third power supply line is connected through the source / drain area and the second load of the fourth transistor. And each of the second and third power lines is shared between adjacent memory cells.

4. The semiconductor device of claim 3, further comprising: a first load element comprising a field effect transistor connected to a source / drain region of the second transistor, and a second load element comprising a field effect transistor connected to a source / drain region of the fourth transistor; And the second load element is formed on the insulating film on the semiconductor substrate, bent in an area intersecting the fourth gate electrode, and serves as a channel region under the fourth gate electrode, and both sides of the channel region are source / drain regions. The band-like first active layer and the first load element are formed on the insulating film on the semiconductor substrate, bent in a region crossing the third gate electrode, and serve as a channel region under the third gate electrode. Both sides of the region further include a band-shaped second active layer serving as a source / drain region.

4. The method of claim 3, wherein first and second resistors are respectively connected to source / drain regions of the second and fourth transistors, and the first and second resistors are formed on an insulating film on a semiconductor substrate and bent. Semiconductor memory device.

4. The semiconductor memory device of claim 3, wherein the first and second transistors are transfer transistors, the second and fourth transistors are drive transistors, and the memory cells are SRAM memocells.

※ Note: The disclosure is based on the initial application.