KR970023449A - Nonvolatile Semiconductor Memory with Readline Select Transistor - Google Patents

Abstract

A semiconductor memory cell according to the present invention includes a first bit line, a second bit line and a third bit line formed in parallel, a word line formed perpendicularly to the first to third bit lines, and between one end of the first node and the first bit line. A first selection transistor having a source-drain path formed therein and a gate connected to the first selection line, a source-drain path formed between one end of the first node and the second bit line and a gate connected to the second selection line A second select transistor, a third select transistor having a source-drain path formed between the second node and the other end of the second bit line and having a gate connected to the third select line, and the other side of the second node and the third bit line And a fourth selection transistor having a source-drain path formed between the ends and a gate connected to the fourth selection line. At least the direction of the source-drain path of the second and third selection transistors is parallel to the word line.

Description

Nonvolatile Semiconductor Memory with Readline Select Transistor

Since this is an open matter, no full text was included.

3 is a circuit diagram showing a first embodiment of the present invention;

5 is a circuit diagram showing a second embodiment of the present invention;

Claims (7)

A semiconductor memory comprising: a first bit line, a second bit line and a third bit line formed in parallel with each other, and a word line formed perpendicular to the first to third bit lines; A first memory transistor having a source-drain path formed between the first bit line and the second bit line and having a gate connected to the word line, and a source-drain path between the second bit line and the third bit line; A second memory transistor having a gate connected to the word line; And a first selection transistor having a source-drain path formed between a first node and one end of the first bit line, and having a gate connected to the first selection line, and a source between one end of the first node and the second bit line. A second selection transistor having a drain path formed therein and a gate connected to the second selection line, a third selection transistor having a source-drain path formed between the second node and the other end of the second bit line, and the second node And a fourth select transistor having a source-drain path formed between the other end of the third bit line and a gate connected to a fourth select line, wherein at least the second select transistor and the source of the third select transistor are connected. -The direction of the drain path is parallel to the word line. The semiconductor memory of claim 1, wherein a direction of the source-drain path of the first and fourth selection transistors is parallel to the word line. A semiconductor memory, comprising: a semiconductor substrate of a first conductivity type; A first conductive region, a second conductive line region, and a third conductive region formed on the semiconductor substrate in parallel in one direction and of opposite conductivity type; A plurality of word lines formed perpendicular to the first to third conductive regions; A first type of opposite conductivity formed near an end on one side of the first conductive region and the second conductive region and formed in parallel with a first portion having a specific length including an end on one side of the second conductive region Auxiliary conductive region; A second conductivity type formed near an end on the other side of the second conductive region and the third conductive region, the second conductive region being parallel to a second portion having a particular length including an end on the other side of the second conductive region Auxiliary conductive region; A first selection line formed perpendicular to the first portion and the first auxiliary conductive region; And a second selection line formed perpendicular to the second portion and the second auxiliary conductive region. 4. The semiconductor device of claim 3, wherein the first conductive region has a third portion parallel to the first auxiliary conductive region, and the third conductive region has a fourth portion parallel to the second auxiliary conductive region, and the semiconductor The memory further comprises a third selection line formed perpendicular to the third portion and the first auxiliary conductive region, and a fourth selection line formed in parallel with the fourth portion and the second auxiliary conductive region. Semiconductor memory. A semiconductor memory, comprising: a semiconductor substrate of one conductivity type; A plurality of conductive regions of opposite conductivity type formed by repeatedly arranging a group consisting of four parallel members of the first to fourth conductive regions as a unit on a surface portion of the semiconductor substrate; First auxiliary conductive regions of opposite conductivity type arranged adjacent to an end portion in one direction of the first, second and third conductive regions of the unit group; A second auxiliary conductive region of opposite conductivity type arranged adjacent to an end in a reverse direction of the third and fourth conductive regions of the unit group and the first conductive region of the next unit group; A plurality of gate electrodes arranged perpendicular to the plurality of conductive regions; First select lines extending on one end of the first and third conductive regions and the first auxiliary conductive region adjacent thereto and arranged in parallel with the plurality of gate electrodes; A second selection line extending over one end of the second conductive region and the first auxiliary conductive region adjacent thereto and arranged in parallel with the plurality of gate electrodes; A third selection line across the end in the reverse direction of the fourth conductive region and the second auxiliary conductive region adjacent thereto and arranged in parallel with the plurality of gate electrodes; A fourth selection line disposed on the end in the opposite direction of the third conductive region and the first conductive region of the next unit group and the second auxiliary conductive region adjacent thereto and arranged in parallel with the plurality of gate electrodes; And conductive wires arranged on the gate electrode and the selection line and separately electrically connected to the auxiliary conductive region, the conductive wirings being formed by the respective conductive regions, the respective auxiliary conductive regions adjacent thereto and the respective selection lines. And the channel length direction of at least the selection transistor formed by the first and fourth selection lines among the selection transistors is in the extending direction of the selection line. 6. The semiconductor memory according to claim 5, wherein an end portion of each auxiliary conductive region is formed adjacent to at least one side of the end portion in one direction of the second or fourth conductive region. 6. The semiconductor memory according to claim 5, wherein the channel length direction of the selection transistor formed by the second and third selection lines is also parallel to the extending direction of the selection line. ※ Note: The disclosure is based on the initial application.