JPH09107076A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the area of selection transistors, by forming a selection transistor made of first and fourth selection gate electrodes in a way that the transistor has a channel length in the same direction as the elongated side of the selection gate electrode. SOLUTION: A part of an auxiliary diffusion layer 4 is put in parallel with a part of diffusion layer 2 in a selection transistor region. These transistors S1, S2, S3, S4 and S6 made up of selection gate electrodes 5 and 8 have their channel length in a forward current direction in accordance with the length of the electrodes 5 and 8. At the same time, selection transistors S2 and S5 made up of selection electrodes 6 and 7 have their channel length in accordance with a crosswise direction of selection gate electrodes 6 and 7. In the selection transistors S1, S2, S3, S4 and S6, marginal spaces of the selection gate electrodes 5 and 8 for the diffusion layer 2 and the auxiliary diffusion layer 4 are made small, and an area for the chip can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a read-only memory device (mask RO
M) relates to the structure of the memory cell.

[0002]

2. Description of the Related Art As an example of a memory cell structure of a large-capacity mask ROM, a NOR in which a source and a drain of a memory cell transistor are arranged by an N type diffusion layer and a gate electrode is arranged so as to be orthogonal to the N type diffusion layer. Type flat cell is used (JP-A-5-167042).

FIG. 3 shows a plan view of a memory cell array of such a mask ROM.

On the surface of the P type silicon substrate 31, N serving as the source and drain of the memory cell transistor is formed.
A plurality of mold diffusion layers 32 are arranged in parallel. The gate electrode 33 of the memory cell transistor is arranged so as to be orthogonal to the diffusion layer 32 and forms a memory cell transistor region. Each memory cell transistor has a plurality of memory transistors connected in series with each diffusion layer 32 as a source / drain path. Select transistors S31, S32, S33, S34, S3 are provided in the select transistor region adjacent to the memory cell transistor region.
5 and S36 are formed. Each select transistor is composed of select gate electrodes 35, 36, 37, and 38 using the diffusion layer 32 and the auxiliary diffusion layer 34 as sources and drains. Each of these selection transistors selectively connects the auxiliary diffusion layer 34 and a predetermined diffusion layer of the plurality of diffusion layers 32. Each select transistor is formed such that the channel length direction (current flow direction) matches the width direction of each select gate electrode. The auxiliary diffusion layer 34 is connected to the metal conductive line 40 through the contact 39.

[0005]

In the conventional example, the channel directions of all the selection transistors (S31 to S36) are formed in the width direction of the selection gate electrodes (35 to 38).
It was necessary to design a large alignment margin of the gate electrode with respect to the diffusion layers to be the source and the drain. Therefore, it is difficult to reduce the area of the select transistor region because the width of the gate electrode is increased.

[0006]

A nonvolatile semiconductor memory device of the present invention includes a semiconductor substrate of one conductivity type, and a plurality of reverse conductivity semiconductors that are repeatedly arranged in a unit group of four parallel to the surface portion of the semiconductor substrate. Type conductive region, a plurality of reverse conductive type auxiliary conductive regions arranged adjacent to one direction side ends of the first, second and third conductive regions of the unit group, and a plurality of unit group first conductive regions. A plurality of reverse conductive type auxiliary conductive regions arranged adjacent to opposite side ends of the first conductive regions of the third, fourth and next unit groups, and a plurality of auxiliary conductive regions arranged orthogonal to the conductive regions. A gate electrode, one direction side end of the first and third conductive regions, a first select gate electrode straddling the auxiliary conductive region adjacent thereto, and one direction side end of the second conductive region And the auxiliary conductive region adjacent to A second selection gate electrode, and the third selection gate electrode spanning the auxiliary conductive region adjacent the thereto opposite direction side end portion of the fourth conductive region, said third
And a fourth select gate electrode extending over the opposite side end of the first conductive region of the next unit group and the auxiliary conductive region adjacent thereto, and arranged on the gate electrode and each select gate electrode. And a conductive line electrically connected to each auxiliary conductive region.

[0007]

1 is a plan view showing a first embodiment of the present invention. Since the memory cell transistor region has the same structure as that of the conventional example, description thereof will be omitted. The select transistor region is arranged adjacent to the memory cell transistor region. In the selection transistor area, the selection transistor S1,
S2, S3, S4, S5 and S6 are formed. Each selection transistor uses the N-type diffusion layer 2 and the N-type auxiliary diffusion layer 4 as sources and drains, and selects gate electrodes 5, 6, and 7.
And 8. Here, a part of the auxiliary diffusion layer 4 is in parallel with a part of the diffusion layer 2 in the selection transistor region. Therefore, select transistors S1, S3, S4 and S6 formed by select gate electrodes 5 and 8
Are formed such that the channel length direction (direction of current flow) matches the length direction of the select gate electrodes 5 and 8.
On the other hand, the select transistors S2 and S5 formed by the select gate electrodes 6 and 7 are formed such that the channel length direction is aligned with the width direction of the select gate electrodes 6 and 7. Therefore, the selection transistors S1, S3, S4, and S6 have the diffusion layer 2 and the auxiliary diffusion layer 4 which are different from those of the conventional example.
It is possible to design the alignment margin of the select gate electrodes 5 and 8 with respect to the above. That is, the width of the select gate electrodes 5 and 8 can be made smaller than that of the conventional example,
The chip area can be reduced. Further, the area of the auxiliary diffusion layer 4 can be reduced to about 60% of the conventional example, and the junction capacitance of the auxiliary diffusion layer 4 added to the metal conductive line 10 connected through the contact 9 can be reduced.

FIG. 2 is a plan view showing a second embodiment of the present invention. Since the memory cell transistor region has the same structure as that of the conventional example, description thereof will be omitted. The select transistor region is arranged adjacent to the memory cell transistor region. Select transistors S11, S12,
S13, S14, S15 and S16 are formed. Each select transistor uses the N-type diffusion layer 12 and the N-type auxiliary diffusion layer 14 as a source and a drain, and the selection gate electrode 1
5, 16, 17, and 18. The select transistors S11, S12, S13, S14, S15 and S16 are formed such that the channel length direction (direction of current flow) matches the length direction of the select gate electrodes 15, 16, 17 and 18. Therefore, the select transistors S11, S12, S13, S14, S15, and S16 have select gate electrodes 15, 16, 17, and 1 for the diffusion layer 12 and the auxiliary diffusion layer 14 as compared with the conventional example.
It is possible to design the alignment margin of 8 to be small. That is, the width of the select gate electrodes 15, 16, 17 and 18 can be made smaller than that of the conventional example, and the chip area can be reduced. Further, the area of the auxiliary diffusion layer 14 can be reduced to about 80% of the conventional example, and the junction capacitance of the auxiliary diffusion layer 14 added to the metal conductive line 20 connected through the contact 19 can be reduced.

[0009]

According to the present invention, since the channel length direction of the select transistor is formed so as to coincide with the length direction of the select gate electrode, the N type diffusion layer and the N type diffusion layer of the select gate electrode are formed.
The alignment margin with respect to the type auxiliary diffusion layer, that is, the width of the select gate electrode can be designed to be small, and the area of the select transistor region can be reduced. Further, since the area of the N-type auxiliary diffusion layer can be reduced, the junction capacitance of the auxiliary diffusion layer added to the metal conductive line can be suppressed to be low, and higher speed operation can be supported.

[Brief description of the drawings]

FIG. 1 is a plan view of a first embodiment of the present invention.

FIG. 2 is a plan view of a second embodiment of the present invention.

FIG. 3 is a plan view showing a conventional technique.

[Explanation of symbols]

 1, 11, 31 P-type semiconductor substrate 2, 12, 32 N-type diffusion layer 3, 13, 33 Gate electrode 4, 14, 34 N-type auxiliary diffusion layer 5, 15, 35 First selection gate electrode 6, 16, 36 Second selection gate electrode 7, 17, 37 Third selection gate electrode 8, 18, 38 Fourth selection gate electrode 9, 19, 39 Contact 10, 20, 40 Metal conductive wire

Claims (3)

[Claims] 1. A plurality of conductive regions of opposite conductivity type, which are repeatedly arranged in a unit group of four semiconductor substrates of one conductivity type and first to fourth conductive regions parallel to a surface portion of the semiconductor substrate. An auxiliary conductive region of opposite conductivity type disposed adjacent to one side end of the first, second and third conductive regions of the unit group, and the third, fourth and next conductive regions of the unit group. A reverse conductive type auxiliary conductive region arranged adjacent to a reverse side end of the first conductive region of the unit group; a plurality of gate electrodes arranged orthogonal to the plurality of conductive regions; A first gate electrode which is arranged in parallel with the plurality of gate electrodes and extends over one side end portions of the first and third conductive regions and the auxiliary conductive region adjacent thereto; and the second conductive region. On one side end of the auxiliary guide A second select gate electrode that is arranged in parallel with the plurality of gate electrodes over the charge region;
A third select gate electrode disposed on the opposite side end of the fourth conductive region and on the auxiliary conductive region adjacent to the opposite side end in parallel to the plurality of gate electrodes; A fourth select gate electrode which is arranged in parallel with the plurality of gate electrodes, on the opposite side end of the first conductive region of the unit group and on the auxiliary conductive region adjacent thereto; A conductive line arranged on each of the select gate electrodes and electrically connected to each of the auxiliary conductive regions, each conductive region end portion, each of the auxiliary conductive regions adjacent thereto, and each of the select gate electrodes. That the channel length direction of the select transistor formed by at least the first and fourth select gate electrodes among the select transistors formed by the above is the length direction of the select gate electrode. The nonvolatile semiconductor memory device according to symptoms. 2. The side end portion of the conductive region is provided in parallel with and adjacent to at least one side surface portion of one side end portion of the second and fourth conductive regions. 1
14. The nonvolatile semiconductor memory device according to claim 1. 3. The nonvolatile semiconductor memory device according to claim 1, wherein the channel length direction of the select transistor formed by the second and third select gate electrodes is also the length direction of the select gate electrode. .