JP4024910B2 - Nonvolatile semiconductor memory device and manufacturing method thereof - Google Patents

Description

【００４１】
ところで，多値情報を容易に読み出すためには，各ソース・ドレイン電流ＩｄｓＨＨ，ＩｄｓＨ，ＩｄｓＬ，ＩｄｓＬＬの電流値差が明確にならねばならない。そのために寸法を規定する必要のある形状を，図９に示したメモリセルトランジスタ１２において説明する。図９において，ａ，ｂは，ドレイン８ａからソース７ａに流れ込むソース・ドレイン電流ＩｄｓＡの電流経路におけるゲート長ＬＡ（チャネル長）とゲート幅ＷＡ（チャネル幅）に相当する。又，ドレイン８ｂからソース７ａに流れ込むソース・ドレイン電流ＩｄｓＢの電流経路を例えば図中の実線矢印のように取れば，その電流経路におけるゲート長ＬＢ（チャネル長）とゲート幅ＷＢ（チャネル幅）はそれぞれａ＋２ｂ，ｘとなる。ｘはアクティブ領域の形成時に決まる寸法であり，必ずａよりも短い。この時，ＩｄｓＨＨはＩｄｓＨとＩｄｓＬの和であることから，
ＩｄｓＨ ＝ ２×ＩｄｓＬ
であれば，ＩｄｓＨＨ，ＩｄｓＨ，ＩｄｓＬ，ＩｄｓＬＬの電流値それぞれの間に，ＩｄｓＬに相当する電流値差が発生する。
【００４２】
すなわち，
（ＷＡ／ＬＡ） ＝ ２×（ＷＢ／ＬＢ）
となる必要がある。従って，
（ｂ／ａ） ＝ ２×｛ｘ／（ａ＋２ｂ）｝
という関係が成立する。これより，ｘはａ，ｂを用いて，
ｘ ＝ （ｂ／２ａ）×（ａ＋２ｂ）
と表すことが出来る。例えば，ｂ＝ａ／２とすれば，ｘ＝ａ／２となり，ｂ＝ａ／３とすれば，ｘ＝５ａ／１８を得る。すなわち，ａとｂの簡単な寸法比率からｘを想定し，電流値差を明確にすることが出来る。
【００４３】
以上，本発明の好ましい実施の形態を説明したが，本発明は以上の形態に限定されないことは勿論であり，当業者の想到し得る範囲において適宜変更することが可能である。
【００４４】
【発明の効果】
本発明によれば，ＲＯＭデータの書き込みをソース・ドレインの不純物注入工程にて行うので，特別なホトリソグラフィー工程や特別なエッチング又はイオン注入工程を，新たに設ける必要がない。従って，ウエハープロセス全般に費やすＴＡＴを短く，かつコストを安くできる。また，メモリセル領域及びその周辺へソース・ドレインの不純物注入を同時に行えば，トランジスタの形成は終了する。加えて，その後の配線工程が１層配線なので，ＲＯＭデータ書き込み後のＴＡＴも短くできる。
【００４５】
また，４値の多値情報を記憶するのであれば，ＲＯＭデータの書き込みはわずか１回のソース・ドレインの不純物注入で良い。従って，書き込むＲＯＭデータを多値情報とするために，複数回のホトリソグラフィー工程やエッチング又はイオン注入工程などを必要とせず，ＴＡＴを短くかつコストを安くできる。簡単な寸法比率によって，メモリセルトランジスタから読み出されるソース・ドレイン電流Ｉｄｓの電流値差を明確にすることができるため，多値情報の読み出しが容易である。また，このＩｄｓの相対的な電流値差は，メモリセルトランジスタのチャネル領域やＳ／Ｄ拡散層の不純物濃度に依存しないため，ＲＯＭデータ書き込み後のウエハープロセス処理条件，特に熱処理条件の変更等による影響を受けない。
【図面の簡単な説明】
【図１】本発明の実施の形態にかかる不揮発性半導体記憶装置としてのマスクＲＯＭを製造するシリコン基板の部分的な平面図である。
【図２】ワード線を形成したシリコン基板の部分的な平面図である。
【図３】図２のＡ−Ａ’断面矢視図であり，ポリシリコン膜をパターニングする前の状態を示している。
【図４】図２のＡ‐Ａ’断面矢視図であり，ボリシリコン膜をパターニングしてワード線を形成した後の状態を示している。
【図５】各メモリセルトランジスタを形成するためのレジスト開ロ部の説明図である。
【図６】図５のＢ−Ｂ’断面の一部を拡大して示した図面である。
【図７】各金属配線を形成したシリコン基板の部分的な平面図である。
【図８】メモリセルトランジスタから多値情報を読み出す様子を説明するための等価回路図である。
【図９】多値情報を記憶するためのメモリセルトランジスタの拡大図である。
【符号の説明】
２ フィールド絶縁膜
３ アクティブ領域
６ ゲート電極
Ｗ ワード線
１Ｃ，２Ｃ，３Ｃ，４Ｃ メモリセル[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device capable of storing multi-value information and a manufacturing method thereof.
[0002]
[Prior art]
The nonvolatile semiconductor memory device is used only for reading and is called a ROM (Read Only Memory). Among them, a mask ROM in which information is written as a circuit at the stage of a mask process of manufacturing a memory device is widely used because it can be highly integrated and can easily realize low cost. A technique for multivalued information stored in the mask ROM has been conventionally known.
[0003]
As a first example, in a mask ROM having a NAND-type or NOR-type memory cell structure, a threshold voltage Vt of a MISFET (Metal Insulator Semiconductor Effect Transistor) before and after the step of forming the gate electrode of the memory cell transistor ( (Hereinafter simply referred to as “Vt”), the ion implantation process and the photolithography process thereof are changed a plurality of times, and the Vt is changed for each memory cell transistor due to the difference in impurity concentration, so that multi-value information can be stored. How to do is known. For example, the channel region has four p-type impurity concentrations, and four nch memory cell transistors having different Vt are formed. As a result, four-value information can be stored.
[0004]
As a second example, in magazine electronics (Electronics, March 24, 1983, p121 to p123), by changing the gate length (channel length) and gate width (channel width) of a memory cell transistor, that is, MISFET, for each memory cell transistor, Means enabling multi-value storage are disclosed. That is, a method for storing information when forming a field insulating film and a method for storing information when forming a polysilicon word line have been proposed.
[0005]
As a third example, Japanese Patent Laid-Open No. 62-287661 discloses a method of forming a high-concentration impurity diffusion region having the same conductivity type as that of the substrate at the gate electrode side end after forming a source / drain region of a memory cell transistor, or By not forming such a region, multi-value information can be stored.
[0006]
[Problems to be solved by the invention]
However, these conventional multi-value information storage technologies have the following problems. First, there is a problem of TAT (turnaround time: time from designating program data to completion). In the mask ROM, it is desired to shorten TAT, which is the time spent in the whole wafer process and the time from final data writing to product shipment, due to the nature of the product. However, in the method for controlling the impurity concentration of the channel region shown in the first example and the method for forming the high concentration impurity layer at the gate electrode side end shown in the third example, a special ion implantation process for writing information is performed. That photolithography process is required. For this reason, the time spent for the entire wafer process becomes longer, and a cost burden is required to write information. Further, in the method of changing the gate length and gate width for each memory cell transistor shown in the second example, multi-value information must be written when the gate electrode is formed before the formation of the memory cell transistor. Thus, if the final information is written in the middle of the formation of the memory cell transistor, the time from writing to product shipment (TAT) cannot be shortened.
[0007]
  The second point is a problem in reading multi-value information. To distinguish multi-value information as an electrical signal, the source / drain current value (for each memory cell transistor (IdsValue) needs to be clear. Here, in the first example, the memory cell transistorIdsThe value depends on the impurity concentration ion-implanted into the channel region of the transistor. However, if the ion implantation process continues multiple times,Proximity effectDue to the deformation of the resist mask due to the above and the misalignment of the mask, the effective area of ion implantation is reduced, and the insufficient amount of implantation becomes remarkable. Therefore, each memory cell transistorIdsThe value difference becomes unstable, making it difficult to read out multi-value information. This difficulty in reading hindered the commercialization of multilevel information storage devices.
[0008]
It is an object of the present invention to shorten the manufacturing process of a semiconductor memory device that stores multi-value information, and in particular, to shorten the TAT required from information writing to product completion, and to read multi-value information. Another object of the present invention is to provide a non-volatile semiconductor memory device and a method for manufacturing the same.
[0009]
[Means for Solving the Problems]
  In order to solve this problem, the non-volatile property of claim 1semiconductorThe memory device divides the active region of the memory cell transistor into four regions by arranging a pair of field insulating films crossing the word line direction on both sides of the gate electrode provided below the word line. A source diffusion layer is formed by diffusing impurities in any one of the four separated regions, and a field insulating film and a region facing the source diffusion layer with a word line interposed therebetween are formed. When a drain diffusion layer is formed by diffusing impurities in one of the opposed regions and a drain diffusion layer is formed in the opposed region across the word line, the opposite region is sandwiched between the field insulating films The length of the current path from the drain diffusion layer to the source diffusion layer is different from that when the drain diffusion layer is formed in the region. The non-volatile semiconductor memory device according to claim 1 has a source / drain current value that flows into the source diffusion layer from the drain diffusion layer formed in a region facing each other across the word line due to the difference in the length of the current path.IdsValue) and the source / drain current value flowing from the drain diffusion layer formed in the opposite region across the field insulating film into the source diffusion layer (IdsValue) will be different.IdsMulti-value information can be distinguished as an electrical signal by the difference in value.
[0010]
  Non-volatile of claim 2semiconductorThe memory device divides the active region of the memory cell transistor into four regions by arranging a pair of field insulating films crossing the word line direction on both sides of the gate electrode provided below the word line. A source diffusion layer is formed by diffusing impurities in any one of the four separated regions, and a field insulating film and a region facing the source diffusion layer with a word line interposed therebetween are formed. A feature is that a drain diffusion layer is formed by diffusing impurities in both regions facing each other, and a channel region under the gate electrode is shared. According to another aspect of the nonvolatile semiconductor memory device of the present invention, a source diffusion layer is formed from both a drain diffusion layer formed in a region opposed to a word line and a drain diffusion layer formed in a region opposed to a field insulating film. The source / drain current flows into the non-volatile memory according to claim 1.semiconductorCompared with the memory device, the source / drain current value (IdsValue) increases. In the nonvolatile semiconductor memory device according to claim 2, the length of the current path from the two or more drain diffusion layers formed in the channel region under the gate electrode to the source diffusion layer as described in claim 3 However, the length may be set to be different for each drain diffusion layer.
[0011]
   According to a fourth aspect of the present invention, a pair of field insulating films are arranged on both sides of the gate electrode provided below the word line so as to cross the word line direction, thereby providing four active regions of the memory cell transistor. Separating into regions,
  Of these four separate areasA source diffusion layer forming region which is an arbitrary region, and two drain diffusion layers which are regions corresponding to the source diffusion layer forming region with a word line interposed therebetween and a field insulating film therebetween A resist mask that exposes at least one of the source diffusion layer formation region and the two drain diffusion layer formation regions with respect to the formation region, or the source diffusion layer formation region and the two drain diffusion layers Do not expose all of the formation areaForming a resist mask;
  And a step of diffusing impurities from above the resist mask.
[0012]
According to the manufacturing method of the fourth aspect, the nonvolatile semiconductor memory device according to the first to third aspects can be manufactured with a short TAT. When the resist mask is formed so as not to expose only one of the four regions, one source diffusion layer and two drain diffusion layers can be formed. When a resist mask is formed so as not to expose two of the four regions, one source diffusion layer and one drain diffusion layer can be formed. On the other hand, when the resist mask is formed so as not to expose all the four regions, the impurity diffusion layer is not formed in those regions. According to the present invention, since the impurity implantation for forming the source / drain diffusion layer in the memory cell transistor also becomes a ROM data writing / storing process for the memory cell / transistor, the TAT spent on the entire process can be reduced. Can be shortened. That is, in a conventional mask ROM, impurities are usually implanted into the channel region just for writing ROM data from directly above the gate electrode of the memory cell transistor that has been formed. At that time, a resist mask is required for a memory cell transistor that does not want to write data, and a photolithography process is also required for that purpose. On the other hand, in the present invention, since the source / drain impurity implantation, which is the ROM data writing process, is not an extra process just for writing, there is no need to add a special process and the entire process is spent. TAT can be shortened and no extra cost is incurred.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a nonvolatile semiconductor memory device according to a preferred embodiment of the present invention will be described based on its manufacturing process. FIG. 1 is a partial plan view of a silicon substrate (P-type single crystal silicon wafer) 1 for manufacturing a mask ROM as a nonvolatile semiconductor memory device according to an embodiment of the present invention.
[0014]
  First, by selective oxidation using a silicon nitride film as a mask, a large number of discontinuous field insulating films 2 having a shape as shown in FIG. 1 are provided on the surface of the silicon substrate 1 to perform element isolation. The four memory cells 1C, 2C, 3C, and 4C that will be formed will be described as specific examples, and the description will be made based on them. In practice, however, other memory cells besides the memory cells 1C to 4C are simultaneously formed on the surface of the silicon substrate 1 by the same process. For example, another memory cell 5C is formed at the center of these memory cells 1C to 4C (in addition, another memory cell is formed adjacently around the memory cells 1C to 4C. Those memory cells are not shown). The portion of the surface of the silicon substrate 1 without the field insulating film 2 formed in this way becomes the active region 3 of each memory cell 1C,. In the illustrated example, the field insulating film 2 has a shape in which rectangular insulating film portions 2a each having a smaller area than the insulating film portion 2b are disposed on both sides of the octagonal insulating film portion 2b. Each field insulating film 2 has a predetermined interval in the x direction (lateral direction in FIG. 1) in FIG. 1 so that the insulating film portions 2a are adjacent to each other.OpenIn the y direction (vertical direction in FIG. 1), the insulating film portions 2b, the insulating film portions 2a, 2a of the field insulating films 2 adjacent to each other, the insulating film portions 2b,... Is arranged. Further, each memory cell 1C,... Formed on the surface of the silicon substrate 1 is arranged so as to be adjacent to the four field insulating films 2 on the upper, lower, left and right sides. The upper part of the field insulating film 2 located above, the lower part of the field insulating film 2 located on the left, the upper part of the field insulating film 2 located on the lower side, the upper part of the field insulating film 2 located below, The left insulating film portion 2a of the field insulating film 2 located in the direction surrounds each of the memory cells 1C,.positionIs formed.
[0015]
  Next, after removing the silicon nitride film used as a mask, the entire surface of the silicon substrate 1 is thermally oxidized to form a gate oxide film 4 in the active region 3. Thereafter, a polysilicon film is formed on the surface of the silicon substrate 1 by, for example, a CVD method, and phosphorus of n-type impurity is removed.PolysiliconThermally diffuses into the membrane. Then, the polysilicon film is patterned by photolithography and etching techniques to form word lines W (W0, W1, W2, W3, W4) shown in FIG.
[0016]
  In this case, each word line W (W0 to W4) moves each memory cell formed on the surface of the silicon substrate 1 in the vertical direction.(In Fig. 2Extending in the y direction). More specifically, for example, the word line W1 extends so as to connect the memory cell 1C and the memory cell 3C, and the word line W3 extends so as to connect the memory cell 2C and the memory cell 4C. The width of each word line W (W0 to W4) is set so as to straddle the insulating film portions 2a and 2a of the field insulating film 2 arranged adjacent to each other in each memory cell. Here, the memory cell 1C will be described in cross section. FIGS. 3 and 4 are both AA ′ cross-sectional views of FIG. 2, FIG. 3 shows a state before patterning the polysilicon film, and FIG. A state after the polysilicon film is patterned to form the word line W1 is shown. As shown in FIG. 4, the width of the word line W1 is set adjacent to the memory cell 1C.TogetherThe field insulating film 2 is set to be wider than the distance between the insulating film portions 2a and 2a so that both edge portions of the word line W1 straddle both insulating film portions 2a and 2a of the adjacent field insulating film 2. Deploy.
[0017]
4, a part of the word line W1 (that is, the word line) formed on the surface of the silicon substrate 1 exposed between the insulating film portions 2a and 2a through the gate oxide film 4 as described above. A portion of W1 in contact with the surface of the silicon substrate 1 exposed between the insulating film portions 2a and 2a) becomes the gate electrode 6 of the memory cell 1C. The portion of the surface of the silicon substrate 1 located below the gate electrode 6 is the channel region 5 of the memory cell 1C. In this way, the word line W1 extends in the y direction in FIG. 2, and the insulating film portions 2a of the field insulating film 2 adjacent to each other on both sides of the gate electrode 6 formed in a part of the word line W1. By arranging 2a so as to intersect the word line W1 (in the illustrated example, in the x direction in FIG. 2), the active region 3 of the memory cell 1C has an insulating film portion between the word line W1 and the field insulating film 2. By 2a and 2a, the gate electrode 6 (channel region 5) is centered and the four regions 1C1, 1C2, 1C3 and 1C4 are separated.
[0018]
Similarly, the gate electrode 6 and the channel region 5 are formed in the memory cell 3C by forming the word line W1, and the active region 3 of the memory cell 3C is also centered on the gate electrode 6 (channel region 5). The four regions 3C1, 3C2, 3C3 and 3C4 are separated. Further, for example, by forming the word line W3, the gate electrode 6 and the channel region 5 are also formed in the memory cells 2C and 4C, respectively, and the active region 3 of these memory cells 2C and 4C is also the gate electrode 6 (channel region 5). 4 are separated into four regions 2C1, 2C2, 2C3 and 2C4 and regions 4C1, 4C2, 4C3 and 4C4, respectively.
[0019]
Next, for example, arsenic of an n-type impurity is ion-implanted into each memory cell 1C,... On the surface of the silicon substrate 1 to appropriately form source diffusion layers 7a and 7b and drain diffusion layers 8a and 8b. As described above, the memory cells 1C,... Are centered on the gate electrode 6 by disposing the pair of field insulating films 2 on both sides of the word line W (W0 to W4). Since it is divided into four regions (for example, regions 1C1, 1C2, 1C3 and 1C4), two sets of source diffusion layers 7a and 7b and drain diffusion layers 8a and 8b can be formed for each memory cell. It becomes possible. In this case, for example, for the memory cell 1C, the region 1C1 is the source diffusion layer 7a, the region 1C2 is the drain diffusion layer 8a, the region 1C3 is the source diffusion layer 7b, and the region 1C4 is the drain diffusion layer 8b. The drain diffusion layer 8a is disposed on the opposite side of the gate electrode 6 (word line W1), and the drain diffusion layer 8b is disposed on the opposite side of the insulating film portion 2a. In addition, with respect to the source diffusion layer 7b, a drain diffusion layer 8b is disposed on the opposite side of the gate electrode 6 (word line W1), and the drain diffusion layer is disposed on the opposite side of the insulating film portion 2a. 8a is arranged. Thereby, in each memory cell 1C,..., One source diffusion layer 7a or 7b and two drain diffusion layers 8a and 8b can form a structure sharing the channel region 5 under the gate electrode 6, respectively. it can.
[0020]
  Thus, the process of forming the source diffusion layers 7a and 7b and the drain diffusion layers 8a and 8b in the memory cell C is as follows:MISFETAt the same time, the ROM data is written into the silicon substrate 1 and the multi-value information is stored. Here, as shown in FIG. 5, the case where multi-value information is stored for four memory cells 1C, 2C, 3C and 4C formed on the surface of the silicon substrate 1 will be described as an example.
become.
[0021]
First, after a resist film is applied to the surface of the silicon substrate 1, a resist mask having resist openings 9, 10, and 11 corresponding to the memory cells 1C, 2C, and 3C is formed by a photolithography technique. In this case, by forming a resist mask, at least any one of the regions 1C1, 1C2, 1C3, and 1C4 separated into four by the word line W1 and the insulating film portions 2a, 2a of the field insulating film 2 is formed. A resist mask is formed so as not to expose the two regions. In this example, the memory cell 1C is configured such that the three regions 1C1, 1C2, and 1C4 are exposed from the resist opening 9, and the memory cell 2C includes the two regions 2C1 and 2C2 from the resist opening 10. The memory cell 3C is configured such that the two regions 3C1 and 3C4 are exposed from the resist opening 10. Further, the resist opening corresponding to the memory cell 4C is not formed.
[0022]
Next, S / D (source / drain) ion implantation is performed, and the gate electrode 6 (word line W) and the insulating film portions 2a and 2b of the field insulating film 2 are used as masks in the openings 9, 10, and 11, respectively. An n + diffusion layer is formed by self-alignment. Thus, the memory cell transistor 12 having the source 7a and the drains 8a and 8b is formed in the memory cell 1C, the memory cell transistor 13 having the source 7a and the drain 8a is formed in the memory cell 2C, and the memory cell 3C A memory cell transistor 14 having a source 7a and a drain 8b is formed. Since the memory cell 4C has no resist opening and the resist mask is still applied, the memory cell transistor 15 formed in the memory cell 4C does not have an n + diffusion layer.
[0023]
Thus, after the S / D ion implantation for writing multi-value information, the resist mask is removed. Next, an interlayer insulating film 16 such as a BPSG film is formed on the surface of the silicon substrate 1 by, for example, a CVD method. Here, FIG. 6 is an enlarged view showing a part of the B-B ′ cross section of FIG. 5. As shown in FIG. 6, it is further communicated with four regions (for example, regions 1C1, 1C2, 1C3, and 1C4 for the memory cell 1C) of each memory cell 1C,... By photolithography and etching techniques. A connection hole 17 is formed in the interlayer insulating film 16. In this case, for example, one connection hole 17 can be connected to the region 1C1 of the memory cell 1C and the region 5C3 of the memory cell 5C to be shared (the description is omitted, but other adjacent ones). Similarly, it is possible to share one connection hole between adjacent memory cells in the memory cell regions).
[0024]
  Next, an aluminum film is formed on the surface of the silicon substrate 1 by sputtering. Then, the aluminum film is selectively removed by photolithography and etching techniques, and the memory cell transistors 12 to 15 formed in each of the memory cells 1C,... Are electrically connected as shown in FIG. Metal wiring M (M0, M1,M 2 , M ThreeAnd M4). However, each metal wiring M (M0 to M4) extends in a zigzag manner in a direction perpendicular to the word line W (W0 to W4) while obliquely intersecting the gate electrode 6 of each memory cell 1C,. To be provided. Thereby, the metal wiring M0 electrically connects the region 1C3 of the memory cell 1C and the region 2C3 of the memory cell 2C, and the metal wiring M1 is connected to the regions 1C2, 1C4 of the memory cell 1C and the regions 2C2, 2C4 of the memory cell 2C. The metal wiring M2 electrically connects the region 3C3 of the memory cell 3C, the region 1C1 of the memory cell 1C, the region 4C3 of the memory cell 4C and the region 2C1 of the memory cell 2C, and the metal wiring M3 The regions 3C2, 3C4 of the memory cell 3C and the regions 4C2, 4C4 of the memory cell 4C are electrically connected, and the metal wiring M4 electrically connects the region 3C1 of the memory cell 3C and the region 4C1 of the memory cell 4C.
[0025]
FIG. 8 is an equivalent circuit diagram for explaining a state in which multi-value information is read from each of the memory cell transistors 12 to 15 configured as described above. A square A in the figure indicates a memory cell region on the surface of the silicon substrate 1. In the memory cell region A, the memory cell transistors 12 to 15 described above are formed. FIG. 8 also shows a memory cell transistor 29 formed in the memory cell 5C.
[0026]
As shown in FIG. 8, each of the metal wirings M (M0, M1, M2,...) Extended outside the memory cell region A has switching transistors SW / B (SW / B0, SW / B1, SW). / B2,..., And switching transistors SW / F (SW / F1, SW / F2,...) Are connected. As described above with reference to FIG. 7, each metal wiring M (M0 to M4) is appropriately electrically connected to each region of each memory cell 1C,.
[0027]
The gates of the switching transistors SW / B connected to the even-numbered metal wiring M2m (m = 0, 1, 2,...) Are connected to the even-numbered word lines W2n (n = 0, 1, 2 ...). On the other hand, the odd-numbered metal wiring M2m + 1 (m = 0, 1, 2,...) Is further extended from the other connection end of the switching transistor SW / B, and the even-numbered metal wiring M2m (one less in number) ( (m = 0, 1, 2,...) to form a metal wiring MM (MM0, MM1, MM2,...) (that is, the metal wiring M2m + 1 and the metal wiring M2m having the same m are connected. Metal wiring MMm).
[0028]
  Each gate of the switching transistor SW / F (SW / F1, SW / F2,...) Connected to the metal wiring M2m, M2m + 1 (m = 0, 1, 2,...) Is connected to the metal wiring MG22 or metal. Metal wiring via wiring MG23M 2m +1 or M 2m(M = 0, 1, 2,...). However, the metal wiring M (M0, M1, M2,...) Is extended outside the memory cell region A to connect the switching transistors SW / B (SW / B0, SW / B1, SW / B2,... It is set until it is connected to ().
[0029]
  Further, the metal wirings (M0, M1, M2,...) Further extended from the other connection ends of the switching transistors SW / F (SW / F1, SW / F2,...) Are connected to each other. Thus, the metal wiring MMM24 and the metal wiring MMM25 are provided. These metal wirings MMM24 and MMM25 are further extended to form switching transistors.SW / G 2 , SW / G 1It is connected to the. The gates of the switching transistors SW / G1, SW / G2 are connected to word lines W2n, W2n + 1 (n = 0, 1, 2,...), Respectively. The other connection ends of the switching transistor transistors SW / G1 and SW / G2 are grounded.
[0030]
  In FIG. 8, the switching transistor SW / B, the switching transistors SW / G1, and SW / G2 form, for example, a Poly Si gate nchMISFET, and the switching transistor SW / F includes, for example,Al gateIt can be realized by forming an nch MISFET.
[0031]
Next, the operation of reading the written data will be described based on the equivalent circuit diagram shown in FIG. For example, in order to read data written in the memory cell transistor 12, in FIG. 8, the word line W1 is first selected and the gate voltage Vgs is applied. This Vgs is transmitted to the switching transistor SW / B2n + 1 (n = 0, 1, 2,...) And opens it. Accordingly, only M2m + 1 (m = 0, 1, 2,...) Of the metal wiring M (M0, M1, M2...) Is used as the bit line B2m + 1 (m = 0, 1, 2,...). Become functional. Therefore, if the metal wiring MM0 is selected, the drain voltage Vds is applied to the memory cell transistor 12 through the bit line B1.
[0032]
Further, this Vds is transmitted through the metal wiring MG22, and only the switching transistor SW / F connected to the metal wiring M2 is opened. Further, the switching gate SW / G2 is opened by applying Vgs to the word line W1. As a result, the metal wiring M2 is grounded to the ground with the switching transistor SW / B2 closed, and becomes the grounding line G1.
[0033]
For example, in order to read data written in the memory cell transistor 29, the word line W2 is first selected in FIG. 8 and the gate voltage Vgs is applied. This Vgs is transmitted to the switching transistor SW / B2n (n = 0, 1, 2,...) And opens it. Accordingly, only M2m (m = 0, 1, 2,...) Of the metal wiring M (M0, M1, M2...) Is used as the bit line B2m (m = 0, 1, 2,...). Become functional.
[0034]
Therefore, if the metal wiring MM1 is selected, the drain voltage Vds is applied to the memory cell transistor 29 through the bit line B2. Further, this Vds is transmitted through the metal wiring MG23, and only the switching transistor SW / F connected to the metal wiring M3 is opened. Further, the switching gate SW / G1 is opened by applying Vgs to the word line W2. As a result, the metal wiring M3 is connected to the ground with the switching transistor SW / B3 closed, and becomes the ground line G2.
[0035]
  The operation of reading data from each memory cell transistor in the equivalent circuit of FIG. 8 with reference to the operation described above is generally described as follows. That is, when the word line W2n + 1 is selected, the metal wiring M2m + 1 functions as the bit line B2m + 1 (m = 0, 1, 2,...), And the metal wiring M2m + 2 (m = 0, 1, 2,...) It functions as a ground line G2m + 1 (m = 0, 1, 2,...). When the word line W2n is selected, the metal wiring M2m functions as the bit line B2m (m = 0, 1, 2,...), And the metal wiring M2m + 1 isGround wireIt functions as G2m (m = 0, 1, 2,...). Therefore, the word lines W correspond to row (row) data lines, and the metal wiring MM corresponds to column (column) data lines. In addition, as can be seen from FIG. 7, whether the row number of the selected word line W (W0, W1, W2,...) Is an even number 2n or an odd number 2n + 1 (n = 0, 1, 2,. ..) Allows the same metal wiring M to function as both a bit line and a ground line.
[0036]
  Here, it will be described that data read from each memory cell transistor is multi-value information. As described above with reference to FIG. 5, the memory cell transistor 12 has an n + diffusion layer formed in the source 7a and the drains 8a and 8b. Word line W1
Is selected, the gate voltage Vgs is applied to the gate electrode 6, and when the bit line B1 is selected, the drain voltage Vds is simultaneously applied to the drains 8a and 8b. Then, the source / drain current from the drain 8a intersects the gate electrode 6 at a right angle.IdsA also passes under the gate electrode 6 halfway and intersects with it, and the source / drain current flows from the drain 8b.IdsB is the source / drain current in the source 7a.IdsIt flows as HH. thisIdsHH goes to the ground line G1 through the connection hole 17. At this time, the drain voltage Vds is also applied between the source 7b and the drain, but since the n + diffusion layer is not formed here, the source / drain current does not flow. The source 7b is connected to the metal wiring M0 through the connection hole 17. At this time, since M0 is in a high resistance (floating) state, it does not work as a ground line.
[0037]
  As described above with reference to FIG. 5, the memory cell transistor 13 has an n + diffusion layer formed only in the source 7a and the drain 8a. When the word line W3 is selected, the gate voltage Vgs is applied to the gate electrode 6.Bit line B 1If you select,drainThe voltage Vds is applied to the drain 8a. Then, source / drain current from the drain 8aIdsSource-drain current in source 7aIdsIt flows as H. thisIdsH goes to the ground line G 1 through the connection hole 17.
[0038]
  Further, as described above with reference to FIG. 5, the memory cell transistor 14 has an n + diffusion layer formed only in the source 7a and the drain 8b.Word line W 1Is selected, the gate voltage Vgs is applied to the gate electrode 6, and when the bit line B3 is selected, the drain voltage Vds is applied to the drain 8b. Then, source / drain current flows from the drain 8b.IdsSource-drain current to source 7aIdsIt flows as L. thisIdsL goes to the ground line G3 through the connection hole 17. However, this source-drain currentIdsL is the distance corresponding to the channel length is the source / drain currentIdsSince it is longer than H, the current value becomes smaller.
[0039]
  In addition, as described above with reference to FIG.ApertureNo n + diffusion layer is formed. In FIG. 8, even if the word line W3 and the bit line B3 are selected, the source / drain currentIdsLL takes a very small value. Therefore, the source / drain current read from the memory cell transistors 12, 13, 14, 15IdsThe value of isIdsHH,IdsH,IdsL,IdsMulti-value information corresponding to the data HH, H, L, and LL can be given in the order of LL. These are summarized in Table 1.
[0040]
[Table 1]

[0041]
  By the way, in order to easily read out multi-value information, each source-drain currentIdsHH,IdsH,IdsL,IdsThe LL current value difference must be clear. For this purpose, a shape whose size needs to be defined will be described in the memory cell transistor 12 shown in FIG. In FIG. 9, a and b are source / drain currents flowing from the drain 8a to the source 7a.IdsThis corresponds to the gate length LA (channel length) and the gate width WA (channel width) in the current path A. Also, source / drain current flowing from the drain 8b to the source 7aIdsIf the current path of B is taken as indicated by a solid line arrow in the figure, for example, the gate length LB (channel length) and the gate width WB (channel width) in the current path are a + 2b and x, respectively. x is a dimension determined when the active region is formed, and is always shorter than a. At this time,IdsHHIdsH andIdsSince it is the sum of L,
      IdsH = 2 ×IdsL
Then, IdsHH, IdsH,IdsA current value difference corresponding to IdsL is generated between the current values of L and IdsLL.
[0042]
That is,
(WA / LA) = 2 × (WB / LB)
It is necessary to become. Therefore,
(B / a) = 2 × {x / (a + 2b)}
The relationship is established. From this, x uses a and b,
x = (b / 2a) × (a + 2b)
Can be expressed as For example, if b = a / 2, x = a / 2, and if b = a / 3, x = 5a / 18 is obtained. That is, the current value difference can be clarified by assuming x from a simple dimensional ratio of a and b.
[0043]
The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and can be appropriately changed within a range conceivable by those skilled in the art.
[0044]
【The invention's effect】
According to the present invention, since ROM data is written in the source / drain impurity implantation process, it is not necessary to newly provide a special photolithography process or a special etching or ion implantation process. Therefore, the TAT spent for the entire wafer process can be shortened and the cost can be reduced. If the source / drain impurity implantation is simultaneously performed in the memory cell region and its periphery, the formation of the transistor is completed. In addition, since the subsequent wiring process is a one-layer wiring, the TAT after writing ROM data can be shortened.
[0045]
  If four-level multi-value information is stored, ROM data can be written by only one source / drain impurity implantation. Therefore, since the ROM data to be written is multivalued information, a plurality of photolithography processes, etching or ion implantation processes are not required, and TAT can be shortened and the cost can be reduced. simpleDimension ratioSource / drain current read from memory cell transistor byIdsTherefore, it is easy to read out the multi-value information. Also thisIdsThe relative current value difference between the two does not depend on the impurity concentration of the channel region of the memory cell transistor or the S / D diffusion layer, and therefore is not affected by the change of the wafer process conditions after writing the ROM data, especially the heat treatment conditions. .
[Brief description of the drawings]
FIG. 1 is a partial plan view of a silicon substrate for manufacturing a mask ROM as a nonvolatile semiconductor memory device according to an embodiment of the present invention.
FIG. 2 is a partial plan view of a silicon substrate on which word lines are formed.
FIG. 3 is a cross-sectional view taken along the line A-A ′ of FIG. 2 and shows a state before patterning a polysilicon film.
4 is a cross-sectional view taken along the line A-A ′ of FIG. 2 and shows a state after a poly silicon film is patterned to form a word line.
FIG. 5 is an explanatory diagram of a resist opening portion for forming each memory cell transistor.
6 is an enlarged view of a part of a B-B ′ cross section of FIG. 5;
FIG. 7 is a partial plan view of a silicon substrate on which each metal wiring is formed.
FIG. 8 is an equivalent circuit diagram for explaining a state in which multi-value information is read from a memory cell transistor.
FIG. 9 is an enlarged view of a memory cell transistor for storing multi-value information.
[Explanation of symbols]
2 Field insulation film
3 Active area
6 Gate electrode
W Word line
1C, 2C, 3C, 4C memory cell

Claims (4)

By disposing a pair of field insulating films on both sides of the gate electrode provided below the word line so as to cross the word line direction, the active region of the memory cell transistor is separated into four regions,
A source diffusion layer is formed by diffusing impurities in any one of the four separated regions, and a field insulating film and a region facing the source diffusion layer with a word line interposed therebetween A drain diffusion layer is formed by diffusing impurities in either one of the regions facing each other,
In addition, a current from the drain diffusion layer to the source diffusion layer is formed when the drain diffusion layer is formed in the region facing the word line and when the drain diffusion layer is formed in the region facing the field insulating film. A non-volatile semiconductor memory device, wherein the lengths of the paths are different from each other. By disposing a pair of field insulating films on both sides of the gate electrode provided below the word line so as to cross the word line direction, the active region of the memory cell transistor is separated into four regions,
A source diffusion layer is formed by diffusing impurities in any one of the four separated regions, and a field insulating film and a region facing the source diffusion layer with a word line interposed therebetween A nonvolatile semiconductor memory device characterized in that a drain diffusion layer is formed by diffusing impurities in both regions facing each other with a channel region under the gate electrode shared.     3. The nonvolatile semiconductor memory device according to claim 2, wherein the lengths of current paths from the two drain diffusion layers to the source diffusion layer formed in the channel region under the gate electrode are different from each other. Separating the active region of the memory cell transistor into four regions by disposing a pair of field insulating films crossing the word line direction on both sides of the gate electrode provided below the word line;
A source diffusion layer forming region, which is any one of the four separated regions, and a corresponding region and a field insulating film sandwiched between the source diffusion layer forming region and the word line, respectively. A resist mask that exposes the source diffusion layer formation region and at least one drain diffusion layer formation region of the two drain diffusion layer formation regions with respect to the two drain diffusion layer formation regions that are opposed to each other, or Forming a resist mask that does not expose all of the source diffusion layer formation region and the two drain diffusion layer formation regions ;
And a step of diffusing impurities from above the resist mask.

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