KR960014464B1 - Semiconductor memory device having a static memory cell - Google Patents
Semiconductor memory device having a static memory cell Download PDFInfo
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- KR960014464B1 KR960014464B1 KR1019930005331A KR930005331A KR960014464B1 KR 960014464 B1 KR960014464 B1 KR 960014464B1 KR 1019930005331 A KR1019930005331 A KR 1019930005331A KR 930005331 A KR930005331 A KR 930005331A KR 960014464 B1 KR960014464 B1 KR 960014464B1
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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Abstract
Description
제1도는 일반적인 씨모오스형 스태틱 메모리셀의 구조를 나타내는 회로도.1 is a circuit diagram showing the structure of a general SIMOS type static memory cell.
제2도는 종래의 스태틱 메모리셀의 회로배치를 보이는 도면으로, 액티브영역과 전송트랜지스터 및 구동트랜지스터의 회로배치도.2 is a diagram showing a circuit arrangement of a conventional static memory cell, and shows a circuit arrangement of an active region, a transfer transistor, and a driving transistor.
제3도는 본 발명에 따른 스태틱 메모리셀 구조의 제1실시예를 보이는 도면으로, 액티브영역과 전송트랜지스터 및 구동트랜지스터의 회로배치도.3 is a diagram showing a first embodiment of the static memory cell structure according to the present invention, wherein a circuit arrangement diagram of an active region, a transfer transistor, and a driving transistor is shown.
게4도는 본 발명에 따른 스태틱 메모리셀 구조의 제2실시예를 보이는 도면으로, 액티브영역과 전송트랜지스터 및 구동트랜지스터의 회로배치를 도시한회로배치도.4 is a circuit arrangement diagram showing a circuit arrangement of an active region, a transfer transistor, and a driving transistor, showing a second embodiment of the static memory cell structure according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10, 23, 36, 37 : 액티브 영역 T1, T2 : 전송트랜지스터10, 23, 36, 37: active area T1, T2: transfer transistor
12, 14, 40, 42 : 전송게이트 전극 T3, T4 : 구동트랜지스터12, 14, 40, 42: transfer gate electrode T3, T4: drive transistor
16, 18, 28, 30, 44, 46 : 구동게이트전극 T5, T6 : 부하저항소자16, 18, 28, 30, 44, 46: driving gate electrodes T5, T6: load resistance elements
20, 22, 32, 34, 48, 50 : 컨텍홀 24, 26 : 워드라인20, 22, 32, 34, 48, 50: contact hole 24, 26: word line
본 발명은 스태틱 메모리셀을 가지는 반도체 메모리장치에 관한 것으로, 특히 스태틱 메모리셀 구조에 관한 것이다.The present invention relates to a semiconductor memory device having a static memory cell, and more particularly to a static memory cell structure.
스택틱 랜덤 액세스 메모리(Static Random Access Memory : SRAM)에서 사용되는 스태틱 메모리셀은, 제1도에 보인바와 같이, 2개의 전송트랜지스터(T1, T2)와 2개의 구동트랜지스터(T3, T4) 및 2개의 부하저항소자(load resistance) T5, T6로 구성된다. 상기 구동트랜지스터 T3, T4와 부하저항소자 T5, T6으로 구성된 부위가 데이타를 래치하는 메모리셀로 동작한다. 상기 전송게이트 T1, T2는 비트라인을 통하여 메모리셀에 데이타를 저장하거나 또는 메모리셀에 저장된 데이타를 비트라인으로 전달하는 통로로서, 게이트단자가 워드라인에 접속되고 채널의 일단이 비트라인에 접속된다. 상기한 스태틱 메모리셀의 기본구조가 ISSCC 1992 DIGEST OF TECHNICAL PAPERS vol. 36의 209페이지에 개시되어 있으며, 제2도에 이를 도시하였다.The static memory cells used in the static random access memory (SRAM) include two transfer transistors T1 and T2 and two driving transistors T3 and T4 and 2, as shown in FIG. Load resistance elements T5 and T6. The portion consisting of the driving transistors T3 and T4 and the load resistance elements T5 and T6 acts as a memory cell for latching data. The transfer gates T1 and T2 are passages for storing data in the memory cells or transferring data stored in the memory cells to the bit lines through bit lines. The gate terminals are connected to the word lines and one end of the channel is connected to the bit lines. . The basic structure of the static memory cell described above is ISSCC 1992 DIGEST OF TECHNICAL PAPERS vol. 36, page 209, shown in FIG.
제2도를 살펴보면, 기판상에 형성된 액티브영역(10)(점선으로 도시한 영역의 내부)과, 상기 액티브영역(10)의 상부에서 교차방향으로 선정하는 전송게이트전극(12, 14) 및 구동게이트전극(16, 18)으로 이루어져 있다. 각 게이트전극(12, 14, 16, 18)은 액티브영역(10)과 게이트절연막에 의해 이격되어 있으며, 그에 따라 전송게이트전극(12, 14)과 액티브영역(10)과의 교차부위가 각각 전송트랜지스터 T1, T2로 동작하고, 구동게이트전극(16, 18)과 액티브영역(10)과의 교차부위가 각각 구동트랜지스터 T3, T4로 동작하게 되며, 전송트랜지스터 T1 및 T2의 각각의 일단은 컨텍홀(20, 22)을 통하여 후속공정에서 도시하지 아니한 비트라인에 접속된다.Referring to FIG. 2, the active region 10 (inside the region shown by the dotted lines) formed on the substrate, the transfer gate electrodes 12 and 14 selected in the cross direction from the upper portion of the active region 10, and the driving It consists of gate electrodes 16 and 18. Each of the gate electrodes 12, 14, 16, and 18 is spaced apart from the active region 10 by the gate insulating layer, and thus the intersections between the transfer gate electrodes 12 and 14 and the active region 10 are transferred. The transistors T1 and T2 operate, and the intersections between the driving gate electrodes 16 and 18 and the active region 10 operate as the driving transistors T3 and T4, respectively, and one end of each of the transfer transistors T1 and T2 is connected to the contact hole. Through (20, 22) is connected to the bit line not shown in the subsequent process.
그러나 상기 제2도에 도시한 스태틱 메모리셀의 구조에서는 비트라인과전송트랜지스터(T1, T2)를 접속하기 위한 컨텍홀(20, 22)의 형성이 전송트랜지스터 T1, T2에 인접하여 형성되기 때문에, 컨텍공정시 공정마진이 작아 공정상의 어려움이 따르게 된다. 이러한 문제점을 극복하기 위해서 전송트랜지스터 T1, T2의 게이트전극의 길이를 줄여 컨텍 형성을 용이하게 할 수도 있으나, 이 경우 전송트랜지스터의 전류 구동능력이 증가되어 메모리셀 동작의 안정도측면에서 바람직하지 못하다.However, in the structure of the static memory cell shown in FIG. 2, since the contact holes 20 and 22 for connecting the bit lines and the transfer transistors T1 and T2 are formed adjacent to the transfer transistors T1 and T2, Due to the small process margin in the contact process, process difficulties will follow. In order to overcome this problem, the gate electrodes of the transfer transistors T1 and T2 may be shortened to facilitate contact formation. However, in this case, the current driving capability of the transfer transistor is increased, which is undesirable in terms of stability of memory cell operation.
따라서 본 발명의 목적은, 메모리셀 동작의 안정도를 유지하면서 비트라인 컨텍공정이 공정마진을 확보할 수 있는 반도체 스태틱셀 메모리장치를 제공하는데 있다.Accordingly, an object of the present invention is to provide a semiconductor static cell memory device in which a bit line contact process can secure a process margin while maintaining the stability of a memory cell operation.
상기한 목적을 달성하기 위한 본 발명은, 반도체 기판의 주 표면상에 형성되며 소정의 폭을 갖고 제1방향으로 신장하는 액티브영역과 ; 상기 액티브영역상부에 절연막을 개재하며 상기 제1방향과 교차하는 제2방향으로 신장하는 게이트전극과, 상기 절연막 하부의 액티브영역상에 제1방향의 소정길이와 제2방향의 소정폭을 갖도록 형성되며 상기 게이트전극에 인가되는 제어신호에 응답하여 턴온 또는 턴오프되는 채널영역을 가지는 전송트랜지스터와; 상기 전송트랜지스터의 채널영역을 매개로 데이타를 수수하는 데이타라인과; 상기 데이타라인을 상기 액티브영역에 접속하기 위한 컨텍홀을 구비하는 반도체 스태틱 메모리장치에 있어서 : 상기 액티브영역이 상기 채널영역의 길이방향과 교차하는 좌측 또는 우측방향으로 확장되어 형성되고, 상기 컨텍홀이 상기 확장된 액티브영역상에 형성됨을 특징으로 한다. 따라서 전송트랜지스터와 컨텍홀 사이의 이격거리를 충분히 확보할 수 있으므로, 비트라인 컨텍공정의 얼라인마진이 커지게 된다.The present invention for achieving the above object is an active region formed on the main surface of the semiconductor substrate and having a predetermined width and extending in the first direction; A gate electrode extending in a second direction intersecting the first direction with an insulating film on the active region, and having a predetermined length in a first direction and a predetermined width in a second direction on the active region below the insulating film; A transfer transistor having a channel region turned on or off in response to a control signal applied to the gate electrode; A data line for receiving data through a channel region of the transmission transistor; A semiconductor static memory device having a contact hole for connecting the data line to the active region, the semiconductor static memory device comprising: the active region extending in a left or right direction crossing the length direction of the channel region, wherein the contact hole It is formed on the extended active region. Therefore, since the separation distance between the transmission transistor and the contact hole can be sufficiently secured, the alignment margin of the bit line contact process is increased.
이하 첨부된 도면 제3도 내지 제4도를 참조하여 본 발명에 따라 형성되는 스태틱 메모리셀의 실시예들이 설명할 것이다. 하술되는 실시예는 전술한 본 발명의 목적에 부합하는 여러가지 실시예들 중에서 바람직한 것을 제시한 것으로서, 본 명세서에 기술된 실시예 이외에도 본 발명의 기술적사상의 범위내에서 통상의 지식을 가진 자가 구현가능한 것이라면 본 발명의 범주에 속함에 유의하기 바란다.Hereinafter, exemplary embodiments of a static memory cell formed according to the present invention will be described with reference to FIGS. 3 to 4. The embodiments described below are presented as preferred among the various embodiments in accordance with the object of the present invention described above, and can be implemented by those skilled in the art within the scope of the technical spirit of the present invention in addition to the embodiments described herein. Note that it belongs to the scope of the present invention.
제3도는 본 발명에 따른 스태틱 메모리셀 구조의 제1실시예로, 액티브영역상에 전송트랜지스터 및 구동트랜지스터가 형성되어 잇는 회로배치들 도시하고 있다. 제3도의 구성을 살펴보면, 반도체 기판의 주표면상에 형성된 액티브영역(23)과, 상기 액티브영역(23)과 교차하도록 그 상부에 형성된 두개의 워드라인(26, 24) 및 상기 워드라인(24, 26) 사이에 형성된 두개의 구동게이트전극(28, 30)으로 이루어져 있다. 상기 워드라인(24, 26) 및 구동게이트전극(28, 30)이 액티브영역(23)과 교차하는 부위는 트랜지스터의 채널로 동작하기 위하여 게이트절연막으로 이격되고, 그 결과로 워드라인(24, 26)과 액티브영역(23)의 교차부위는 전송트랜지스터 T1 및 T2로 동작하고 구동게이트전극(28, 30)과 액티브영역(23)의 교차부위는 구동게이트전극 T3 및 T4로 동작하게 된다. 또한 각각의 전송트랜지스터 T1 및 T2의 채널의 일단은 후속 공정에서 각각 비트라인과 접속되는데, 이 접속을 위하여 컨텍홀(32, 34)이 형성되어 있다. 상기 컨텍홀(32, 34)은 전송트랜지스터 T1 및 T2의 채널길이방향과 교차하는 좌측 또는 우측방향으로 확장된 액티브영역(23a)상에 형성됨에 특히 유의하기 바란다. 상기 확장된액티브영역(23a)의 형성에 따라 상기 전송트랜지스터 T1 및 T2와 각각의 컨텍홀(32, 34)이 서로 충분한 이격거리를 갖도록 하여 컨텍형성시의 공정마진을 크게 할 수 있고, 아울러 채널영역과 컨텍홀 사이에 위치하는 확장된 액티브영역(23b)이 갖는 저항성분을 비트라인과 전송트랜지스터 T1 또는 T2 사이의 오프(off-set) 저항으로 활용하여 메모리셀의 동작마진을 증가시킬 수 있다.3 illustrates a circuit arrangement in which a transfer transistor and a driving transistor are formed in an active region as a first embodiment of the static memory cell structure according to the present invention. Referring to the configuration of FIG. 3, the active region 23 formed on the main surface of the semiconductor substrate, two word lines 26 and 24 formed thereon so as to intersect the active region 23, and the word line 24 are formed. And two driving gate electrodes 28 and 30 formed therebetween. The portion where the word lines 24 and 26 and the driving gate electrodes 28 and 30 intersect the active region 23 is spaced apart by a gate insulating film to operate as a channel of a transistor, and as a result, word lines 24 and 26. ), The intersection of the active region 23 with the transfer transistors T1 and T2, and the intersection of the driving gate electrodes 28, 30 and the active region 23 with the driving gate electrodes T3, T4. In addition, one end of the channel of each of the transmission transistors T1 and T2 is connected to the bit line in a subsequent process, and contact holes 32 and 34 are formed for this connection. Note that the contact holes 32 and 34 are formed on the active region 23a extending in the left or right direction crossing the channel length directions of the transmission transistors T1 and T2. According to the formation of the extended active region 23a, the transmission transistors T1 and T2 and the respective contact holes 32 and 34 have sufficient separation distances from each other, thereby increasing the process margin at the time of forming the contact, and the channel The operating margin of the memory cell can be increased by utilizing the resistance component of the extended active region 23b located between the region and the contact hole as an off-set resistance between the bit line and the transfer transistor T1 or T2. .
제4도는 본 발명에 따른 스태틱 메모리셀 구조의 제2실시예로, 제4a도와 제4b도로 구성된다. 제4a도는 반도체 기판 주표면상에 제1 및 제2액티브영역(36, 37)과 소자분리막(38)이 형성되어 있는 회로배치도이다. 상기 제4a도의 중앙에 도시한 A-A축을 중심으로 좌반부 또는 우반부에 각각 하나의 스태틱 메모리셀이 형성되므로, 하나의 스태틱 메모리셀은 서로 분리된 제1 및 제2액티브영역(36, 37) 상에 걸쳐 형성된다. 또한 상기 제1 및 제2액티브영역(36, 37)의 일부위가 확장되어 패드 형태로 형성되어 있으며, 이 확장된 액티브영역(36a, 37a)이 후속되는 비트라인 컨텍공정에서 비트라인과 전송트랜지스터 채널의 일단 사이의 컨텍이 이루어지는 컨텍홀 위치이다.4 is a second embodiment of the static memory cell structure according to the present invention, and is composed of FIGS. 4A and 4B. 4A is a circuit arrangement diagram in which the first and second active regions 36 and 37 and the device isolation film 38 are formed on the main surface of the semiconductor substrate. Since one static memory cell is formed at each of the left half and the right half around the AA axis shown in the center of FIG. 4A, one static memory cell is formed on the first and second active regions 36 and 37 separated from each other. Formed over. In addition, portions of the first and second active regions 36 and 37 are extended to form pads, and the bit lines and the transfer transistors are formed in the bit line contact process followed by the extended active regions 36a and 37a. It is the contact hole position where the contact between one end of the channel is made.
제4b도는 제4a도에 도시한 회로배치도의 상부에 전송게이트전극(40, 42)과 구동게이트전극(44, 46)을형성한 레이아웃도이다. 제1액티브영역(36)과 교차하는 전송 게이트전극(40) 그리고 제2액티브영역(37)과 교차하는 전송게이트전극(42)은 각각의 게이트절연막으로 하부의 액티브영역(36, 37)과 이격되고 상기 게이트절연막의 하부는 채널영역을 형성하여, 상기 각 교차부위가 제1 및 제2전송트랜지스터(T1, T2)로 동작하도록 한다. 또한 제1액티브영역(36)과 교차하는 구동게이트전극(44) 그리고 제2액티브영역(37)과 교차하는 구동게이트전극(46)은 각각의 게이트절연막으로 하부의 액티브영역(36, 37)과 이격되고 상기 게이트절연막의 하부는 채널영역을 형성하여, 상기 각 교차부위가 제1 및 제2구동트랜지스터(T3, T4)로 동작하도록 한다. 상기 제4b도에는 도시하지 아니하였으나, 후속되는 공정에서 제1액티브영역(36)상에 형성된 구동게이트전극(44)은제2액티브영역(37)에 접속되고 제2액티브영역(37)상에 형성된 구동게이트전극(46)은 제1액티브영역(36)에 접속된다. 상기 전송트랜지스터 T1 및 T2의 채널길이방향과 교차하는 좌측 또는 우측방향으로 확장된 액티브영역(36a, 36b)상에는 후속공정에서 컨텍홀(48, 50)이 형성된다. 그 결과로, 제4b도에 도시한 바와 같이, 상기 채널영역의 폭을 그 길이방향으로 신장하였을 때에 정의되는 영역을 벗어나 위치에 건택홀이 형성되므로, 전송트랜지스터 T1 및 T2와 각각의 컨텍홀(48, 50)과의 이격거리가 충분히 확보된다. 따라서 후속되는 컨텍공정시 얼라인마진이 커지게 된다. 또한 컨텍홀이 형성되는 확장된 액티브영역(36a, 37a)과 전송트랜지스터 T1 및 T2 사이의 액티브영역(36b, 37b)이 가지는 저항성분을 비트라인과 전송트랜지스터 T1, T2 사이의 오프저항으로 이용하게 되면 메모리셀의 동작마진을 크게 할 수 있는 장점도 갖는다.FIG. 4B is a layout diagram in which the transfer gate electrodes 40, 42 and the drive gate electrodes 44, 46 are formed on the circuit arrangement diagram shown in FIG. 4A. The transfer gate electrode 40 crossing the first active region 36 and the transfer gate electrode 42 crossing the second active region 37 are spaced apart from the lower active regions 36 and 37 by respective gate insulating layers. The lower portion of the gate insulating layer forms a channel region so that each of the crossing portions operates as the first and second transfer transistors T1 and T2. In addition, the driving gate electrode 44 crossing the first active region 36 and the driving gate electrode 46 crossing the second active region 37 are formed as gate insulating films, respectively. The lower portion of the gate insulating layer is spaced apart from each other to form a channel region so that each of the crossing portions operates as the first and second driving transistors T3 and T4. Although not shown in FIG. 4B, the driving gate electrode 44 formed on the first active region 36 is connected to the second active region 37 and formed on the second active region 37 in a subsequent process. The driving gate electrode 46 is connected to the first active region 36. Contact holes 48 and 50 are formed in subsequent steps on active regions 36a and 36b extending in the left or right direction crossing the channel length directions of the transmission transistors T1 and T2. As a result, as shown in Fig. 4B, since the keyhole is formed at a position beyond the area defined when the width of the channel region is extended in the longitudinal direction thereof, the transfer transistors T1 and T2 and the respective contact holes ( 48, 50) is sufficiently separated. Therefore, the alignment margin increases during the subsequent contact process. In addition, the resistance components of the extended active regions 36a and 37a where the contact holes are formed and the active regions 36b and 37b between the transfer transistors T1 and T2 are used as the off-resistance between the bit line and the transfer transistors T1 and T2. In addition, the operating margin of the memory cell can be increased.
상술한 바와 같이 본 발명에 따른 스태틱 메모리셀은 비트라인과 전송트랜지스터의 채널 일단을 접속하기 위한 컨텍홀이 상기 채널의 길이방향에 교차하는 좌측 또는 우측 방향으로 확장된 액티브영역상에 형성하여 컨텍공장의 공정마진을 높이고, 상기 컨텍홀과 전송트랜지스터 채널 사이의 액티브영역이 가지는 저항성분을 비트라인과 전송트랜지스터 사이의 오프셋저항으로 사용하므로써 메모리셀의 동작마진을 증가시킬 수 있는 장점을 갖는다.As described above, in the static memory cell according to the present invention, a contact hole for connecting a bit line and one end of a channel of a transmission transistor is formed on an active region extending in a left or right direction crossing the length direction of the channel. It is possible to increase the operating margin of the memory cell by increasing the process margin of the transistor and using the resistance component of the active region between the contact hole and the transfer transistor channel as an offset resistance between the bit line and the transfer transistor.
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