JP2876665B2 - Semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is called a stack type CMOS-SRAM, in which a load transistor of a flip-flop constituting a memory cell is formed by a semiconductor layer on a semiconductor substrate. The present invention relates to a formed semiconductor memory.

[Summary of the Invention]

According to the present invention, in a semiconductor memory as described above, a power supply line connected to a load transistor is extended above a boundary between memory cells, so that the degree of integration can be increased. is there.

[Conventional technology]

In the resistance load type MOS-SRAM which has been generally used as the MOS-SRAM, it has become difficult to keep the memory retention ability sufficiently high while keeping the standby current low.

As a countermeasure, in a complete CMOS-SRAM having a memory cell as shown in FIG. 2, PMOS transistors 12, 13 for loading the flip-flop 11 constituting the memory cell are used.
A stack-type CMOS-SRAM in which is stacked on NMOS transistors 14 and 15 for driving is considered (for example, “Nikkei Micro Devices” (1988.9) p.123-13
0).

FIG. 3 shows a conventional example of such a stacked CMOS-SRAM. In this conventional example, the impurity diffusion regions 21 a to 2 serving as source / drain regions of the driving NMOS transistors 14 and 15 and the transfer NMOS transistors 16 and 17 are used.
1 g is formed in the semiconductor substrate.

On an insulating film (not shown) on a semiconductor substrate, gate electrodes 14a to 17a of transistors 14 to 17 are formed of a first layer of polycrystalline silicon.
It is formed by a Si layer. However, gate electrodes 16a, 17a
Is a part of the word line 22.

The gate electrode 14a is connected to the impurity diffusion region 21d, and the gate electrode 15a is connected to the impurity diffusion regions 21b and 21f.

The surfaces of the gate electrodes 14a, 15a, the word lines 22, and the semiconductor substrate are covered with an interlayer insulating film (not shown), and the gate electrodes 12 of the PMOS transistors 12, 13 are formed on the interlayer insulating film.
a and 13a are formed by the second polycrystalline Si layer.

In this manner, the gate electrodes 12a and 13a are
The gate lengths can be made different from each other by using a polycrystalline Si layer different from layers a and 15a, as is clear from FIG.

The gate electrodes 12a and 13a are connected to the gate electrodes 14 through contact holes 23 and 24 formed in the underlying interlayer insulating film.
a and 15a, respectively.

The gate electrodes 12a and 13a are covered with a gate insulating film (not shown). On the gate insulating film, a power supply line 25 and an active layer 26 of the PMOS transistors 12 and 13 connected to the power supply line 25 are provided. , 27 are formed by the third polycrystalline Si layer.

The drain regions of the active layers 26 and 27 are connected to the gate electrodes 15a and 12a via contact holes 31 and 32 formed in the underlying insulating film.

The power supply line 25 and the active layers 26 and 27 are covered with an interlayer insulating film (not shown).
Is formed by the first Al layer.

The ground line 33 is connected to the impurity diffusion region 21c and the like via a contact hole 34 and the like formed in an insulating film therebelow.

The ground line 33 and the like are covered with an interlayer insulating film (not shown), and the bit lines 35 and 36 are formed on the interlayer insulating film by a second-layer Al layer.

The bit lines 35 and 36 are connected to the impurity diffusion regions 21g and 2g through contact holes 37 and 38 formed in the insulating film thereunder.
Connected to 1e respectively.

Incidentally, the impurity diffusion regions 21g and 21e and the contact holes 37,
38 is shared by two memory cells adjacent to each other in a direction perpendicular to the direction in which the word lines 22 extend,
It is arranged on the boundary between these memory cells.

As is clear from the above description, the stacked CMOS-SRA
In the case of M, the active layers 26 and 27 of the PMOS transistors 12 and 13 and the power supply line 25 are formed of the same polycrystalline Si layer, but this is the most efficient in the manufacturing process.

[Problems to be solved by the invention]

However, the active layers 26 and 27 and the power line 25 are
In order to form with a Si layer, it is necessary to secure an interval S between them that is at least the limit of lithography.

Therefore, in order to enable the layout of the active layers 26 and 27 and the power supply line 25, it is necessary to secure a corresponding memory cell area, and in the conventional example shown in FIG. It was not easy.

[Means for solving the problem]

In the semiconductor memory according to the present invention, the load transistor
A power supply line 25 connected to 12 and 13 extends above this boundary along the boundary between the memory cells, and transfer transistors 16 and 17 to be connected to bit lines 35 and 36.
Conductive layers 41, 42 connected to the contact portions 21g, 21e of
Are connected to the bit lines 35 and 36 at positions separated from the boundary line.

[Action]

In the semiconductor memory according to the present invention, since the power supply line 25 extends above this boundary line along the boundary line between the memory cells, the load transistors 12, 13 and the power supply line 25 are in the same semiconductor layer. , The load transistors 12 and 13 can be laid out in the region above the memory cell without being disturbed by the power supply line 25. Therefore, there is room in the layout of the load transistors 12 and 13.

Moreover, even if the contact portions 21g and 21e of the transfer transistors 16 and 17 to be connected to the bit lines 35 and 36 are arranged on the boundary between the memory cells,
g, 21e and the bit lines 35, 36 are connected via the conductive layers 41, 42 at positions separated from the boundary lines, so that the bit lines 3
Even if the layers 5 and 36 are arranged above the power supply line 25, the connection between the transfer transistors 16 and 17 and the bit lines 35 and 36 will not be affected.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to FIG. 1. However, the same components as those of the conventional example shown in FIG.

In the present embodiment, the ground line 33 is formed by the second polycrystalline Si layer, and the conductive layers 4 alternately extend from the impurity diffusion regions 21g and 21e to the word line 22.
Reference numerals 1 and 42 are formed by the second polycrystalline Si layer.

The contact holes 37 and 38 are formed in an insulating film below the conductive layers 41 and 42, and the conductive layers 41 and 42 are formed in these contact holes.
It is connected to the impurity diffusion regions 21g and 21e via 37 and 38, respectively.

Also, the gate electrodes 12a, 13a of the PMOS transistors 12, 13
Is formed by a third polycrystalline Si layer, and the power supply line 25 and the active layers 26 and 27 of the PMOS transistors 26 and 27 are
It is formed by a fourth polycrystalline Si layer.

However, in the present embodiment, the power supply line 25 does not extend above the word line 22 as in the conventional example shown in FIG. , 21e
And extends above the boundary between two adjacent memory cells. Therefore, this power supply line 25 is also shared by two adjacent memory cells.

Note that the contact hole 31 is formed in the insulating film between the drain region of the active layer 26 and the gate electrode 13a.
The drain region 6 is connected to the gate electrode 13a via the contact hole 31.

Bit lines 35 and 36 are formed of an Al layer, and contact holes 43 and 44 formed in an interlayer insulating film thereunder.
, The bit lines 35 and 36 and the conductive layers 41 and 42 are connected above the word line 22 respectively. Therefore, bit line 3
5, 36 are impurity diffusion regions 21g, 21 via conductive layers 41, 42.
e is connected to each.

In this embodiment as described above, since the power supply line 25 extends above the boundary between the two memory cells, the interval S is sufficiently large and there is room. Accordingly, the area of the memory cell can be reduced corresponding to the reduction of the interval S,
The degree of integration can be increased.

〔The invention's effect〕

In the semiconductor memory according to the present invention, although there is no problem in connection between the transfer transistor and the bit line, there is a margin in the layout of the load transistor, so that the area of the memory cell can be reduced, and The degree can be increased.

[Brief description of the drawings]

FIG. 1 is a plan view of one embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of a complete CMOS-SRAM memory cell to which the present invention can be applied,
FIG. 3 is a plan view of a conventional example of the present invention. In the reference numerals used in the drawings, 11: flip-flop 12, 13, PMOS transistor 16, 17: NMOS transistor 21e, 21g: impurity diffusion region 25: power supply line 35, 36 ... bit line 41, 42 ... It is a conductive layer.

Claims (1)

(57) [Claims] 1. A memory cell comprises a flip-flop and a pair of transfer transistors, wherein a load transistor of the flip-flop is formed by a semiconductor layer on a semiconductor substrate and is connected to a bit line. In a semiconductor memory in which a contact portion of the transfer transistor to be arranged is disposed on a boundary between the memory cells, a power supply line connected to the load transistor is disposed above the boundary so as to be along the boundary. And a conductive layer connected to the contact portion is connected to the bit line at a position separated from the boundary line.