JPH03185858A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To improve the degree of integration of the title memory by extending power supply lines connected with load transistors upward along boundaries between memory cells. CONSTITUTION:Since power supply lines 25 are extended upward along boundaries between memory cells, the layout of transistors 12 and 13 can be decided freely from the obstruction of the lines 25 at areas above the memory cells even when the power supply lines 25 and transistors 12 and 13 are formed in the same semiconductor layer. Accordingly, the layout of the transistors 12 and 13 has margins. Even when the contact sections 21g and 21e of transistors 16 and 17 to be connected respectively with bit lines 35 and 36 are arranged on the boundary lines between memory cells, the contact sections 21g and 21e are connected with the bit lines 35 and 36 through conductive layers 41 and 42 at locations separated from the boundary lines and, even when the bit lines 35 and 36 are arranged at a higher level than the power supply lines 25, the transistors 16 and 17 can be connected with the lines 35 and 36 without hindrance.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention is referred to as a stacked CMO3-3RAM, in which a load transistor of a flip-flop constituting a memory cell is connected by a semiconductor layer on a semiconductor substrate. The present invention relates to a semiconductor memory formed therein.

[Summary of the invention]

The present invention makes it possible to increase the degree of integration in the semiconductor memory described above by extending the power supply line connected to the load transistor above the boundary line between memory cells. be.

[Conventional technology]

In the resistive load type MO3-3RAM that has been commonly used as a MOS-3RAM, it has become difficult to maintain a sufficiently high memory retention capacity while keeping the standby current low.

As a countermeasure for the second problem, in a complete CMO 3-3 RAM having memory cells as shown in FIG.
．． The so-called stacked CMO3 stacked on top of 15
-3RAM is being considered (for example, "Nikkei Microdevice" (1988, 9) p. 123-130).

Figure 3 shows such a stacked CMOS-S RAM.
A conventional example of this is shown. In this conventional example, the drive NMO3I transistor 14,15 and the transfer NMO
3) Impurity diffusion regions 21a to 21g, which serve as source/drain regions of transistors 16 and 17, are formed in a semiconductor substrate.

Gate electrodes 14a to 17a of transistors 14 to 17 are formed of a first polycrystalline Si layer on an insulating film (not shown) on a semiconductor substrate. However, the gate electrodes 16a and 17a are part of the word line 22.

The gate electrode 14a is connected to the impurity diffusion regions 21d, and the gate electrode 15a is connected to the impurity diffusion regions 21b, 21.
connected to f.

The gate electrodes 14a, 15a, the word line 22, and the surface of the semiconductor substrate are covered with an interlayer insulating film (not shown), and on this glabellar insulating film are PMO3) transistors 12, 13.
The gate electrodes 12a and 13a are made of a second layer of polycrystalline Si.
It is formed by layers.

Note that by forming the gate electrodes 12a and 13a in this way from a polycrystalline Si layer different from that of the gate electrodes 14a and 15a, it is possible to make the gate lengths different from each other, as is clear from FIG. can.

Gate electrodes 12a and 13a are connected to gate electrodes 14a and 15a, respectively, through contact holes 23 and 24 formed in the interlayer insulating film below them.

The gate electrodes 12a, 13a, etc. are covered with a gate insulator S (not shown), and a power line 2 is connected above the gate insulator.
5 and active layers 26 and 27 of the PMO transistors 12 and 13 connected to the power supply line 25 are formed of 3N-th polycrystalline Si layers.

The drain regions of the active layers 26 and 27 are connected to the gate electrodes 15a and 12a, respectively, through contact holes 31 and 32 formed in the underlying insulating film.

The power supply line 25, the active layers 26, 27, etc. are covered with an interlayer insulating film (not shown), and the ground line 33 is formed from the 1Nth layer on this interlayer insulating film.

The ground line 33 is connected to the impurity diffusion region 21c and the like via a contact hole 34 and the like formed in the underlying insulating film.

ground! The tlA33 and the like are covered with an interlayer insulating film (not shown), and bit lines 35 and 36 are formed on the interlayer insulating film by the second A1 layer.

Bit lines 35 and 36 are connected to impurity diffusion regions 21g and 21e, respectively, through contact holes 37 and 38 formed in the underlying insulating film.

Note that the impurity diffusion regions 21g and 21e and the contact holes 37 and 38 are shared by two memory cells that are adjacent to each other in a direction perpendicular to the extending direction of the word line 22. is located on the border of

As is clear from the above explanation, stack type CMO3-
In the 3RAM, the most efficient manufacturing process is to form the active layers 26, 27 of the PMO3) transistors 12, 13 and the power supply line 25 from the same polycrystalline St layer.

[Problems to be Solved by the Invention] However, in order to form the active layers 26 and 27 and the power supply line 25 from the same polycrystalline Si layer, it is necessary to ensure at least a spacing S between them that is greater than the limit of lithography. There is a need to.

Therefore, in order to enable the layout of the active layers 26 and 27 and the power supply line 25, it is necessary to secure the area of the memory cell correspondingly, and in the conventional example shown in FIG. 3, the degree of integration is increased. It wasn't easy.

[Means to solve the problem]

In the semiconductor memory according to the present invention, the load transistor 1
A power line 25 connected to 2.13 extends above the boundary line between the memory cells, and extends above the boundary line between the memory cells.
A conductive layer 41.42 connected to the contact portions 21g and 21e of the transfer transistor 16.17 to be connected to the bit line 35.36 is connected to the bit line 35.36 at a position apart from the boundary line. ing.

[Effect]

In the semiconductor memory according to the present invention, the power supply line 25 extends above the boundary line between memory cells, so that the load transistor 12.13 and the power supply line 25
Even if they are formed of the same semiconductor layer, the load transistors 12 and 13 can be laid out in the region above the memory cell without being obstructed by the power supply line 25.

Therefore, there is some leeway in the layout of the load transistors 12 and 13.

Moreover, even if the contact portions 2tg and 21e of the transfer transistors 16.17 to be connected to the bit line 35.36 are arranged on the boundary line between memory cells, the contact portions 2tg and 21e and the bit line 35.36 Since the bit lines 35 and 36 are connected to each other through the conductive wires 41 and 42 at a position apart from the boundary line, even if the bit lines 35 and 36 are arranged above the power supply line 25, the transfer transistor 16
, I7 and the bit lines 35 and 36.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to FIG. 1, but the same components as those of the conventional example shown in FIG.

In this embodiment, the ground line 33 is formed by the second polycrystalline Si layer, and the impurity diffusion regions 21g, 21
Conductive conductors 41 and 42 extending alternately from above e to above word line 22 are formed by a second polycrystalline Si layer.

The contact holes 37.38 are formed in the insulating film below the conductive layer 41.42, and the conductive layer 41.42 connects the impurity diffusion region 21g through these contact holes 37.38.
21e, respectively.

In addition, gate electrode 1 of PMO3) transistor 12.13
2a and 13a are formed of a third layer of polycrystalline Si, and are connected to the power supply line 25 and the PMOS transistor 26.
．． Active layers 26 and 27 of No. 27 are formed of a fourth polycrystalline Si layer.

However, in this embodiment, the power supply line 25 does not extend above the word line 22 as in the conventional example shown in FIG.
g and 21e and extend above the boundary line between two adjacent memory cells. Therefore, this power supply vA2
5 is also shared by two adjacent memory cells.

The contact hole 31 is formed in the insulating film between the drain region of the active layer 26 and the gate electrode 13a, and the train region of the active layer 26 is connected to the gate electrode 13a through the contact hole 31.

The bit lines 35 and 36 are formed by the A1 layer,
Contact hole 4 formed in the glabella insulating film below
3.44 above word line 22, bit line 3
5.36 and conductive layers 41.42 are connected to each other.

Therefore, bit lines 35 and 36 are connected to impurity diffusion regions 21g and 21e through conductive layers 41 and 42, respectively.

In this embodiment as described above, since the power supply line 25 extends above the boundary line between the two memory cells, the interval S is sufficiently large and there is a margin. Therefore, the area of the memory cell can be reduced in accordance with the reduction of the interval S.
The degree of integration can be increased.

〔Effect of the invention〕

In the semiconductor memory according to the present invention, although there is no problem in connection between the transfer transistor and the bit line, there is ample space in the layout of the load transistor, so the area of the memory cell can be reduced, and integration is possible. You can increase the degree.

[Brief explanation of drawings]

FIG. 1 is a plan view of an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of a complete CMO3-3 RAM memory cell to which the present invention can be applied, and FIG. 3 is a plan view of a conventional example of the present invention. be. In addition, in the reference numerals used in the drawings, 11...--...----1---Flip-flop 12.13--...PMOS transistor 16, l'l- --------NMO3) Transistors 21e, 21g -------Impurity diffusion region 2
5・・・・・・−・・・・・・・・・・・・Power wire 35
．． 36-...Bit line 41.42 - A conductive layer. Agent Masaru Tsuchiya Figure 2

Claims (1)

[Claims] A memory cell is composed of a flip-flop and a pair of transfer transistors, and a load transistor of the flip-flop is formed of a semiconductor layer on a semiconductor substrate, and is connected to a bit line. In a semiconductor memory in which the contact portion of the transfer transistor to be transferred is arranged on the boundary line between the memory cells, the contact part of the transfer transistor is arranged on the boundary line so that the power supply line connected to the load transistor A semiconductor memory, wherein a conductive layer extending upward and connected to the contact portion is connected to the bit line at a position spaced apart from the boundary line.