JP2672810B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention has a semiconductor integrated circuit element formed by an SOI (Semiconactor On Insulator) structure, and a semiconductor layer laminated structure of two or more layers formed by the SOI structure. The present invention relates to a semiconductor integrated circuit device having a three-dimensional stacked structure, which efficiently uses a boundary semiconductor region including a grain boundary part between recrystallized single crystal semiconductor regions formed on an SOI structure, The present invention relates to a semiconductor integrated circuit element having an element structure capable of improving the degree of integration of elements per semiconductor layer to a level close to that of a conventional single crystal semiconductor substrate. <Prior Art> In recent years, active research has been conducted on circuit elements having a three-dimensional structure of a semiconductor layer laminated structure, and various techniques for forming a recrystallized active element region by melting and growing polycrystalline silicon by beam irradiation in an SOI structure. Is being considered. <Problems to be Solved by the Invention> However, at present, the entire surface of the device cannot be formed in a uniform recrystallizing active region in the same plane orientation as in the single crystal silicon substrate, and a partial surface is partially formed by the single crystal forming method. A grain boundary is formed where single crystal regions having different orientations come into contact with each other. Here, FIG. 4 shows a schematic diagram thereof. Figure 4 shows SO
It is a conceptual diagram of the semiconductor layer formed by I structure. 4 (a) is a plan view, FIG. 4 (b) is a sectional view thereof (AA 'section), and FIG. 4 (c) is a three-dimensional view. 1, 2, and 3 are recrystallized single crystal semiconductor regions (hereinafter "Recrystallized active element region"). In addition, 4 is an insulating layer. Reference numerals 1, 2, and 3 are recrystallization active element regions formed by melting and growing polycrystalline silicon by beam irradiation, and they are not necessarily the same in plane orientation because they solidify from the center of the irradiation beam. Therefore, the crystal grain boundary 5 is generated at the boundary between the 1, 2 and 2, 3 recrystallized regions. Boundary semiconductor regions 6, 7, 8, 9 shown in FIG.
Is a region where grain boundaries are considered to exist. This boundary semiconductor region is a region where it is not preferable to dispose the channel region of the MOS transistor due to the existence of crystal grain boundaries. Therefore, it is ideal to dispose the channel of the MOS transistor in the recrystallized active element region. However, the region in which the transistor can be disposed is limited and the integration degree of the element is restricted. In particular, this is a very inconvenient condition for semiconductor memory devices, which are becoming ever larger in capacity. In view of the above problems, the present invention effectively utilizes a boundary semiconductor region including a crystal grain boundary portion in an SOI structure, and improves integration by arranging a channel region of a MOS transistor in a recrystallization active element region, The purpose of the present invention is to provide a semiconductor integrated circuit device having a small leak current and good characteristics. <Means for Solving the Problems> In order to achieve this object, the present invention provides a plurality of recrystallized single crystal semiconductor regions (recrystallized active element regions, which have not necessarily the same plane orientation) on an insulating layer. The region is located between the plurality of recrystallized single crystal semiconductor regions formed on the insulating layer, for example, by melting and growing polycrystalline silicon by beam irradiation, and the crystal grain boundary portion In the semiconductor integrated circuit element having a boundary semiconductor region including a semiconductor element, a component of an active element such as a transistor (channel region of a MOS transistor) is formed in the recrystallized single crystal semiconductor region, In the boundary semiconductor region including the crystal grain boundary portion, a constituent element of a passive element such as a capacitor or a wiring portion is formed. The present invention
The insulating layer is formed on a single crystal semiconductor substrate (single crystal silicon substrate or the like) on which active elements and passive elements are formed, and the single crystal semiconductor substrate and the semiconductor layer on the insulating layer are formed. It may be a semiconductor integrated circuit element which is connected through a through hole or the like. An insulating layer is further formed on the semiconductor layer on the insulating layer, a semiconductor layer is further formed on the insulating layer, and the semiconductor layers have a laminated structure in which they are connected by through holes. Good. <Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings. FIG. 1 (a) is a mask pattern diagram of an embodiment when the present invention is applied to a storage element, and FIG. 1 (b) is
It is the cross-section structural drawing (BB 'cross section). Here, the mask pattern and the cross-sectional structure show the cell array of the memory cells of the dynamic semiconductor memory element on the SOI structure. In the figure, 11, 12, and 13 are recrystallization active element regions, and 14, 15
Is a boundary semiconductor region including a grain boundary (hereinafter referred to as “inactive element region”), 16 is an insulating layer, 17 is a storage capacitor,
Reference numeral 18 is a single layer polysilicon (cell plate), 19 is a double layer gate polysilicon (word line), 20 is a metal (bit line), and 21 is a contact. As shown in FIGS. 1 (a) and 1 (b), the MOS transistor 22 of the memory cell is composed of a single crystal silicon 23 and a gate 19 of two-layer polysilicon, and the channel region of the transistor is a recrystallized active element. The cell capacitors of the memory cells are arranged so as to be formed in the region, and are arranged in the inactive element region by the cell plate made of single crystal silicon and single-layer polysilicon. FIG. 2 (a) is a mask pattern diagram of another embodiment when the present invention is applied to a memory element, and FIG.
FIG. 3 is a cross-sectional structure diagram (cross section CC ′). In the figure, 31 is a recrystallized active element region, 32 and 33 are inactive element regions, 34 is an insulating layer, 35 is single crystal silicon, 36 is a word line, 37 is a bit line, and 38 and 39 are polysilicon. 2 (a) and 2 (b), as in FIGS. 1 (a) and 1 (b), the MOS transistor 40 is provided in the recrystallization active element region and the cell is provided in the inactive element region. The capacitor 41 is arranged. The pattern of the memory cell is different from that of the memory cell of FIGS. 1A and 1B, of course, but in this example, the cell capacitor is formed of a two-layer poly-silicon without using single crystal silicon in the inactive element region. It is made of silicon. However, here again, FIG.
As in the case of FIG. 3B, active elements such as transistors are not arranged in the non-active element region, and they are fully utilized as the cell capacitor region. In fact, in the pattern of FIG. 2A, as shown in the sectional structure diagram of FIG. 2B, the non-active element region of single crystal silicon in which crystal grain boundaries are considered to exist is the element isolation region. Will be removed as. FIG. 3 shows another embodiment in which the present invention is applied to a logic circuit element. FIG. 3A is a conceptual diagram of a mask pattern and its structure when the inverter element shown in the logic diagram of FIG. 3B is realized by a laminated structure of two semiconductor layers. In the figure, 51 and 52 are semiconductor layers, 53 and 54 are recrystallized active element regions 55, 56, 57 and 58 are inactive element regions, 59 is a gate input, 60 is an output, 61 is a power source, and 62 is a power source 2. Is. If the semiconductor layer 51 is a PMOS transistor having an SOI structure, the semiconductor layer 52 is an NMOS transistor having an SOI structure, and vice versa. Here, when the semiconductor layer 51 is a PMOS and the semiconductor layer 52 is an NMOS, the input / output of the inverter element is an OMOS which is interlayer-coupled by through holes 63 and 64.
The power source 1 of the semiconductor layer 51 corresponds to the power source voltage Vc of the element, and the power source 2 of the semiconductor layer 52 corresponds to GND (ground). As shown in FIG. 3 (a), the recrystallized active element region is arranged so that the channel region of the MOS transistor is formed, and the inactive element region where the crystal grain boundaries are considered to exist has wiring and through holes. It is used as an area for arranging holes. Although not shown, it is of course possible to arrange the contact between the gate polysilicon and the metal and the contact between the drain and the source single crystal silicon and the metal in the inactive element region. Similarly, other transistor elements can be formed with the same structure. <Effects of the Invention> As described above, in the semiconductor integrated circuit device of the present invention, the plurality of recrystallized single crystal semiconductor regions having the same plane orientation on the insulating layer and the plurality of recrystallized single crystal regions are not necessarily the same. A boundary semiconductor region including a crystal grain boundary portion, which is located between the crystalline semiconductor regions, and a constituent element of an active element such as a transistor is formed in the recrystallized single crystal semiconductor region. In addition, the reliability of the device is ensured, while the boundary semiconductor region including the crystal grain boundary is effectively used as a capacitor, a through hole, a contact, or a wiring region. The degree of integration can be improved to a level close to that on a crystalline semiconductor substrate. Furthermore, in a semiconductor integrated circuit device having a three-dimensional laminated structure of a plurality of semiconductor layer laminated structures, the degree of integration is much higher in the same device area than a two-dimensional semiconductor integrated circuit device formed on a conventional single crystal semiconductor substrate. A semiconductor integrated circuit device can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 (a) is a mask pattern diagram of a memory cell array when a dynamic semiconductor memory element is formed in a semiconductor layer having an SOI structure, and FIG. 1 (b) is a sectional structure diagram thereof. is there. 2 (a) and 2 (b) are other mask patterns of the memory cell array when a dynamic semiconductor memory element is formed in the semiconductor layer on the SOI structure as in FIGS. 1 (a) and 1 (b). It is a figure and its sectional construction drawing. FIG. 3 (a) is a conceptual diagram of a mask pattern and structure of a device having a three-dimensional structure in which a semiconductor layer having an SOI structure has a laminated structure, and FIG. 3 (b) is a logic diagram of FIG. 3 (a). FIG. 4 is a conceptual diagram showing a state in which crystal grain boundaries are generated in a semiconductor layer having an SOI structure obtained by melting and growing polycrystalline silicon on an insulating layer by beam irradiation. [Explanation of symbols] 1,2,3: Recrystallization active element region, 4: Insulating layer, 5: Crystal grain boundary, 6,
7,8,9: Inactive element area, 11,12,13: Recrystallized active element area, 14,15: Inactive element area, 16: Insulating layer, 17: Storage capacitor, 18: 1 layer polysilicon ( Cell plate), 19: 2-layer gate polysilicon (word line), 20: Metal (bit line), 21: Contact, 22: MOS transistor, 23: Single crystal silicon, 31: Recrystallized active element region, 32, 33 : Inactive element region, 34: Insulating layer, 35: Single crystal silicon, 36: Word line, 3
7: bit line, 38, 39: polysilicon, 40: MOS transistor, 41: cell capacitor, 51, 52: semiconductor layer, 53, 54: recrystallized active element region, 55, 56, 57, 58: inactive element Area, 59: Gate input, 60: Output, 61: Power supply 1, 62: Power supply 2, 63, 64: Through hole.

   ────────────────────────────────────────────────── ─── Continuation of front page    (56) References JP-A-59-222959 (JP, A)                 JP-A-60-160646 (JP, A)                 JP-A-51-95742 (JP, A)                 JP-A-60-236261 (JP, A)

Claims (1)

(57) [Claims] A plurality of recrystallized single crystal semiconductor regions whose plane orientations are not necessarily the same on the insulating layer, and a boundary semiconductor region which is located between the plurality of recrystallized single crystal semiconductor regions and includes a crystal grain boundary portion. In a semiconductor integrated circuit element provided with a semiconductor layer comprising: a recrystallization single crystal semiconductor region, a constituent element of an active element such as a transistor is formed, while a boundary including the crystal grain boundary portion is formed. A semiconductor integrated circuit element, characterized in that a constituent element of a passive element such as a capacitor or a wiring portion is formed in the partial semiconductor region. 2. In the semiconductor integrated circuit element according to claim 1, on the semiconductor layer, further, via an insulating layer,
It has a plurality of recrystallized single crystal semiconductor regions whose plane orientations are not necessarily the same, and a boundary semiconductor region located between the plurality of recrystallized single crystal semiconductor regions and including a crystal grain boundary portion. A semiconductor integrated circuit device comprising a semiconductor layer, and a through hole for connecting the semiconductor layers to each other is formed in the boundary semiconductor region.