JP3058948B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and, more particularly, to a memory device such as a dynamic RAM (DRAM).
The present invention relates to a crystal direction of a semiconductor substrate used for improving retention characteristics of a memory and reducing power consumption by reducing a leak current of an SFET.

[0002]

2. Description of the Related Art In recent years, semiconductor memory devices have been steadily becoming higher in integration and larger in capacity.
In a MOS dynamic RAM (DRAM) composed of a plurality of MOS capacitors, research on miniaturization of the memory cell is progressing.

Conventionally, in a semiconductor memory, a silicon (100) surface is often used as an element formation surface. At this time, a cut surface called an orientation flat is formed in the 110 direction of the disc-shaped silicon wafer due to the crystallinity of the crystal. Therefore, the MOSFETs in both the memory cell portion and the peripheral circuit portion constituting the memory integrated circuit portion are formed on the silicon surface in the 110 direction and have a dicing surface in the 110 direction.

However, as described above, with the miniaturization and high integration of integrated circuits, the leakage current of transistors becomes remarkable, and power consumption has become a major problem.

Further, when an integrated circuit includes a memory, the problem that accumulated electric charge escapes has become apparent.

In order to prevent this problem, a method of reducing the impurity concentration of the drain is conceivable. However, this leads to an increase in parasitic resistance of the transistor, resulting in current deterioration.

[0007]

As described above, in a semiconductor integrated circuit, despite the demand for an element having extremely low power consumption and excellent charge retention characteristics, recently, in a miniaturized MOSFET, the distance between the drain and the substrate has been increased. The current flowing through the tunnel mechanism has become a major obstacle to the memory retention characteristics as a leak current due to the new mechanism.

The present invention has been made in view of the above circumstances, and has as its object to provide a highly reliable semiconductor device which reduces a leak current between a substrate and a drain in miniaturization.

[0009]

Therefore, according to the present invention, in the MOSFET in the memory cell region, the channel direction, that is, the direction from the source to the drain is (100).
It is formed so as to avoid the 110 direction on the surface, while the peripheral circuit portion is configured to coincide with the 110 direction.

[0010] In this specification, the "110 direction" is a general term for four directions parallel and perpendicular to the <110> direction.

[0011]

The present inventors have found from various experiments that the leakage current between the substrate and the drain largely depends on the channel direction.

The present invention has been made in view of this point.
0) By configuring the channel so as to avoid the 110 direction on the plane, the leakage current of the transistor in the memory cell region can be reduced and the charge retention characteristics can be improved.

And a MOSFET constituting a peripheral circuit.
Is formed in parallel or perpendicular to the orientation flat along the cut-out side of the chip, so that dicing can be easily performed with good area efficiency.

Preferably, the MOSFE in the memory cell region is
The leakage current can be minimized by configuring the channel such that the channel is directed at 45 degrees from the 110 direction on the (100) plane with respect to T.

Further, in the above structure, when the thickness of the gate insulating film is 15 nm or less and the depth of the diffusion layer constituting the source / drain is 0.15 μm or less, the leakage current between the substrate and the drain is particularly small. The present invention exerts a particularly remarkable effect in such a dimensional region.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a diagram showing an arrangement of MOSFETs in a memory cell of a DRAM integrated circuit according to one embodiment of the present invention.

This DRAM integrated circuit is formed on a p-type silicon substrate 1 having a (100) plane of a silicon slice as a substrate surface, and is formed so that a channel is directed at 45 degrees with respect to the 110 direction. .. Constituting the respective memory cell sections 5 and MOSFETs C1, C2... Constituting the peripheral circuit section 6 formed so that the channel is directed in the direction of 110. Things.

Here, the memory cell is a one-transistor / one-capacitor type. The gate of a MOS transistor is connected to a word line, one of a source and a drain is connected to a MOS capacitor, and the other is connected to a bit line. The figure shows the arrangement of MOSFETs in the memory cell. 2 was a gate electrode, 3 was an n-type source region, and 4 was an n-type drain region.

Here, the gate insulating film has a thickness of 15 nm.
Hereinafter, the impurity concentration of the diffusion layer constituting the source / drain was set to 5 × 10 ²⁰ cm ⁻³ and the depth was set to 0.15 μm or less.

According to this DRAM integrated circuit, the leak current is greatly reduced, and the charge retention characteristics are extremely good.

Next, the direction of the MOSFET is changed so that the channel direction is 0 degree, 30 degree,
At 45 degrees, the change in drain current-drain voltage characteristics was measured using the gate voltage as a parameter. The result is shown in FIG. Here, curve A is for a gate voltage of 6 V, B is for a gate voltage of 5 V, C is for a gate voltage of 4 V, D is for a gate voltage of 3 V, and E is a gate voltage of 2 V.
, F is the measurement result when the gate voltage is 1V.

As a result, there is no variation in the characteristics depending on the crystal direction, and there is no difference in the characteristics depending on the directions of 0 °, 30 ° and 45 °.

Similarly, the dependence of the current flowing into the substrate on the gate voltage when the direction was changed was measured using the drain voltage as a parameter. The result is shown in FIG. Here, curve a (a ₀ a ₃₀ a ₄₅ ) is at a drain voltage of 6 V, b (b ₀ b ₃₀ b ₄₅ ) is at a drain voltage of 5 V, c
Is a measurement result when the drain voltage is 4 V, d is a measurement result when the drain voltage is 3 V, and e is a measurement result when the drain voltage is 2 V. In the left part of the figure, for example, a ₀ a ₃₀ a ₄₅ , b ₀ b ₃₀ b ₄₅
While it is divided into three, the right part is one.

As is apparent from this figure, the current flowing into the substrate differs according to each angle, and the current value when tilted by 45 degrees is reduced by about one digit as compared with the case of 0 degree. You can see that. That is, this current is a current flowing between the drain and the substrate at the time of off, which means that the power at the time of off can be reduced by about one digit, and in the case of a memory cell such as a DRAM, If other leaks can be removed, it means that the charge holding characteristic can be extended by one digit.

In the peripheral circuit section, dicing is easy (that is, the dicing surface does not form a zigzag).
Because the channel is formed so that it goes in the 0 direction,
A cut surface can be formed easily with good area efficiency without generating unnecessary portions. FIG. 4 is a layout of a DRAM integrated circuit, and 6 indicates a chip. The sides of the chip are 110 directions. Reference numeral 5 denotes a memory cell unit. One block has a 256K configuration, which is arranged in a 16 × 4 array. A sense amplifier circuit section 7 is provided between the memory cell sections 5, and four column decoders 8 are provided at the center of the chip.
In the center, two row decoder sections 9 are arranged in the longitudinal direction.
However, input / output circuits such as an address buffer and an output buffer and control circuits such as a clock are arranged in the belt-shaped region 10 around and at the center of the chip.

In this embodiment, the arrangement direction of the MOSFETs is changed between the memory cell section 5 and the peripheral circuit sections 7 to 10 for driving the same.

In the above embodiment, the case where a sliced silicon substrate surface is used has been described. However, the M (100) plane obtained by etching the silicon substrate is
Needless to say, the present invention can be applied to the case of forming an OSFET. Although the channel direction of the MOSFET of the memory cell is avoided in the 110 direction, it is particularly preferable to incline by 30 to 60 degrees from the 110 direction.

The present invention is not limited to the embodiments, but can be appropriately modified without departing from the gist of the invention.

[0030]

As described above, according to the present invention, the channel direction, that is, the direction from the source to the drain, of at least a part of the MOSFET in the memory cell region is the 110 direction on the (100) plane. , The leakage current of the transistor can be reduced, and a memory with good charge retention characteristics can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a DRAM integrated circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a result of measuring drain current-drain voltage characteristics using a gate voltage when a channel direction of a MOSFET is changed as a parameter.

FIG. 3 is a view showing the results of measuring the gate voltage dependence of the substrate current using the drain voltage when the channel direction of the MOSFET is changed as a parameter.

FIG. 4 is a diagram showing a memory cell portion and a peripheral circuit portion forming a sense amplifier of the DRAM integrated circuit according to the embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Gate electrode 3 Source 4 Drain 5 Memory cell part 6 Peripheral circuit part 7 Sense amplifier circuit part 8 Column decoder part 9 Row decoder part 10 Strip area

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/8242

Claims (1)

(57) [Claims] 1. A semiconductor device comprising a memory cell of a memory integrated circuit, wherein the direction between the source and the drain of the MOSFET is inclined from the 110 direction on the (100) plane, and the direction of the source and the drain of the MOSFET of the peripheral circuit for driving the memory cell is 1
A semiconductor device having ten directions.