JP3022058B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to a structure of a memory cell of a read only memory.

[0002]

2. Description of the Related Art A read-only memory such as a mask ROM corresponds to a plurality of memory cells arranged in a matrix.
A plurality of bit lines and word lines are arranged to cross each other. Generally, in the case of a ROM, one MOS transistor is associated with one memory cell, and data is determined based on whether or not a transistor specified based on address data is turned on.
In such read-only memory, for example,
As disclosed in Japanese Patent Application Laid-Open No. 179775, there has been proposed a structure called a flat cell in which there is no separation region for separating memory cells, and a bit line is formed by a diffusion layer.

FIG. 5 is a plan view of a memory cell portion of a conventional NOR type mask ROM, and FIG. 6 is a cross-sectional view taken along line XX. A plurality of conductive regions 2 in which N-type impurities serving as bit lines are diffused are formed on the surface of P-type silicon substrate 1.
Are arranged in parallel with each other at regular intervals. This conductive region 2 is made of N-type impurity ions, for example, arsenic (As).
It is formed by implanting ions and is configured to function as a source and a drain of a transistor forming a memory cell.
On the silicon substrate 1 on which the conductive region 2 is formed, a plurality of gate electrodes 3 serving as word lines are arranged so as to intersect with the conductive region 2 via a gate insulating film 4. The MOS transistor T1 of the type is constituted. In the channel region of the transistor T1 (substrate region below the gate electrode 3), an impurity implantation region 5 for selectively implanting a P-type impurity at a high concentration in association with write data is formed. As a result, the threshold voltage of the specific transistor T1 can be changed.
It becomes possible to store data associated with the difference in the operation characteristics of each transistor T1.

[0004] In the above memory device, there is no isolation region such as LOCOS between the transistors constituting the memory cell, and the size of the memory cell can be reduced, which is suitable for increasing the capacity. However, N
Since the bit line is formed by the conductive region 2 formed by diffusing the impurity of the mold, the resistance value and the parasitic capacitance of the bit line itself become large, and there is a problem that high-speed operation cannot be supported.

Accordingly, the applicant has proposed a semiconductor memory device for reducing the resistance value and the parasitic capacitance of the bit line in Japanese Patent Application No. 4-184.
No. 015. 7 and 8 are a plan view and a circuit diagram of the semiconductor memory device. The transistor T1 of the memory cell is the same as that of FIG. 5, and includes an N-type conductive region 2 formed in parallel with the surface of a P-type substrate;
It is constituted by gate electrodes 3 arranged in parallel with each other so as to intersect with the conductive region 2. Then, data is written by selectively forming an impurity implantation region 5 into which a P-type impurity is implanted in the channel region of the transistor T1.

The conductive region 2 is arranged so as to cross the memory cell region, and the odd columns are extended to one end and the even columns are extended to the other end. An auxiliary conductive region 6 is formed between these extended portions so as to be adjacent to each conductive region 2, and is made of polycrystalline silicon so as to intersect with the extended portion of conductive region 2 and auxiliary conductive region 6. Select gate electrodes 7 are arranged two by two. Thus, a selection transistor T2 having the source and drain with the extension of the auxiliary conductive region 6 and the conductive region 2 on both sides thereof is formed. In addition, on both sides of the auxiliary conductive region 6,
Four transistors are formed by the two select gate electrodes 7, and two of the four transistors are formed in the channel region.
A high-concentration impurity-implanted region 7 of the mold is formed so as not to operate.

On the gate electrode 3 and the selection gate electrode 7, an aluminum wiring 9 serving as a bit line is formed on the conductive region 2.
And is connected to the auxiliary conductive region 6 through the contact hole 10 at the gap between the gate electrode 3 and the select gate electrode 7. Therefore, the selection operation of the selection gate electrode 7, that is, by raising the voltage of one of the pair of selection gate electrodes 7, the selection transistor T
2 is selectively turned on, conductive region 2 is connected to aluminum wiring 9 (bit line) via auxiliary conductive region 6.

[0008]

In the above-mentioned semiconductor memory device, the main bit line is formed of aluminum wiring 9.
Therefore, the resistance and capacitance of the bit line are reduced as compared with the case where the conductive region 2 is a bit line. However, since the conductive region 2 as the sub-bit line is connected to the aluminum wiring 9 as the main bit line via the selection transistor T2, if the resistance value of the selection transistor T2 is high, the resistance value of the bit line is reduced. Despite the lowering, there is a problem that high-speed operation cannot be handled.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to reduce the resistance of a bit line and the resistance of a connection transistor connected to the bit line, thereby enabling high-speed operation.

[0010]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is characterized in that a semiconductor substrate of one conductivity type and a surface portion of the semiconductor substrate are mutually attached. They are arranged in parallel at regular intervals, with 2
A plurality of rows of conductive regions of opposite conductivity type forming a pair across the column, a plurality of auxiliary conductive regions arranged adjacent to the ends of each pair of these conductive regions, and A plurality of gate electrodes arranged in parallel with each other on the semiconductor substrate, a first select gate electrode disposed between the end of one conductive region of each pair and the auxiliary conductive region, A second selection gate electrode disposed between an end of the other conductive region and the auxiliary conductive region; and a second select gate electrode arranged on the gate electrode corresponding to each pair, and each of the auxiliary conductive regions And a conductive line electrically connected to the

[0011]

According to the present invention, by arranging the auxiliary conductive region adjacent to the pair of conductive regions with two rows interposed therebetween, the side of the conductive region facing the auxiliary conductive region can be elongated, The gate width of the select transistor formed between the conductive region and the auxiliary conductive region can be set wide. Therefore, the on-resistance of the selection transistor that selectively connects the conductive region and the conductive line is reduced.

[0012]

FIG. 1 is a plan view of a memory cell portion of a semiconductor memory device according to the present invention, and FIGS.
It is sectional drawing of a line and a YY line. P-type silicon substrate 1
A plurality of N-type conductive regions 12 functioning as a source or a drain of a memory cell transistor are arranged in parallel at a predetermined interval on the surface portion of one. These conductive regions 12 are arranged so as to cross the memory cell region, alternately extend to the peripheral portion of the memory cell region in units of two columns, and have an end 13 on the extended side.
Are formed wider than in the memory cell region. The conductive regions 12 form a pair with two rows interposed therebetween, and one of the pairs extends longer than the other. In a region further outside the end portion 13 of the conductive region 12 formed widely,
N-type auxiliary conductive regions 14 are arranged at a certain distance from end 13. This auxiliary conductive region 14
Corresponding to each of the two rows of conductive regions 12 forming a pair, and has a crank shape so that the distance between the end portions 13 of the pair of conductive regions 12 having different lengths of the extension portions is constant. .

On the silicon substrate 11 on which the conductive region 12 and the auxiliary conductive region 14 are formed, a plurality of gate electrodes 16 made of polycrystalline silicon intersect the conductive region 12 and are parallel to each other via a gate insulating film 15. It is arranged in. Thereby, the memory cell transistor T1 is configured using the adjacent conductive region 12 as a source and a drain. This transistor T1 has the same structure as that of FIG. 5, and a P-type impurity implantation region 17 is selectively formed in a channel region of transistor T1 so as to correspond to data to be stored in a memory cell. Further, on both sides of the gate electrode 16, a select gate electrode 1 also made of polycrystalline silicon is provided.
8 are arranged two each so as to extend between the conductive region 12 and the auxiliary conductive region 14. Thus, a selection transistor T2 having the conductive region 12 and the auxiliary conductive region 14 as a source and a drain is configured. Since two select transistors T2 are provided for every four columns at one end of the conductive region 12, the gate width can be increased to two columns of the conductive region 12. Since a plurality of the select transistors T2 are driven by a common gate electrode, a high-concentration P-type diffusion region 19 is formed in a region under the select gate electrode 18 where the select transistor T2 is not formed. Is provided, and the selection gate electrode 1 is provided.
9 prevents conduction between the conductive region 12 or the auxiliary conductive region 14.

On the gate electrode 16 and the select gate electrode 18, an aluminum wiring 21 serving as a bit line is arranged in parallel with the conductive region 12 via an interlayer insulating film 20. The aluminum wiring 21 is associated with each of the auxiliary conductive regions 14, and has a contact hole 22.
Is electrically connected to the auxiliary conductive region 14 through the gate. Therefore, each conductive region 12 is selectively connected to auxiliary conductive region 14 by controlling the voltage applied to select gate electrode 19, and the voltage applied to aluminum wiring 21 is applied via auxiliary conductive region 14.

FIG. 4 is a circuit diagram of a memory cell, corresponding to FIG. Transistor T1 forming each memory cell
Is such that the gate electrodes 16 continuous for each row form n rows of word lines, and an n-bit selection signal W based on row address data.
It is selectively activated by L1 to WLn. Similarly,
The selection transistor T2 has a common selection gate electrode 18 for each row. The selection gate electrode 18 forms a selection control line, and is selectively operated by 4-bit selection control signals SL1 to SL4 based on column address data. On / off control. Aluminum wiring 21 forms a main bit line, and selects signal BL1 based on column address data.
~ BL4 to be selectively activated. That is, the power supply potential and the ground potential are respectively applied to the two aluminum wires 21 corresponding to the address data, and at the same time, the aluminum wires 2
The two select transistors T2 connected to 1 are selectively turned on to connect the specific conductive region 12 to the aluminum wiring 21, thereby activating two adjacent rows of conductive regions 12. Here, for each aluminum wiring 21, the voltage applied in the selected state is not determined to be either the power supply voltage or the ground voltage, and the power supply voltage and the ground voltage are switched according to the combination of the selected bit lines. Like that.

To explain the memory cell selection operation,
Each of the conductive regions 11 is a, b,.
Assume that Therefore, the bit line selection signals BL1 to BL4
, BL1 and BL2 are selected, and at the same time,
For the selection signals SL1 to SL4 of the selection control line, SL1
And SL4, a and b are connected to the bit line, so that one column of transistors T1 between a and b is selected. Similarly, when BL2 and BL4 are selected and SL2 is selected, d and e are connected to the bit line, and the transistor T1 between d and e is selected. As described above, the selection of the bit line is made by selecting two adjacent lines or one between them.
One of the two control lines is selected, and one or two selection control lines are selected accordingly. Further, by selecting one of the selection signals WL1 to WLn of the gate electrode 16, the selection signals BL1 to BL4 and the selection signal SL are selected.
One of the transistors T1 in one column selected by the combination of 1 to SL4 is designated. Then, a change in the potential of the conductive region 12 according to ON / OFF of the transistor T1 at that time is determined by the sense amplifier connected to the aluminum wiring 21.

In the above-mentioned memory cell, a plurality of blocks may be provided along the aluminum wiring 21, and block selection may be performed by a selection operation of the selection transistor T2. In this case, all the selection transistors T2 of the non-selected blocks are fixed to the off state.

[0018]

According to the present invention, the resistance of the select transistor can be reduced in addition to the reduction of the resistance and the capacitance by shortening the length of the conductive region. Therefore, the effect of reducing the resistance of the bit line can be fully utilized, and the data determination period can be shortened, and high-speed operation can be supported.

[Brief description of the drawings]

FIG. 1 is a plan view showing a memory cell portion of a semiconductor memory device according to the present invention.

FIG. 2 is a sectional view taken along line XX of FIG.

FIG. 3 is a sectional view taken along line YY of FIG. 1;

FIG. 4 is a circuit diagram of FIG. 1;

FIG. 5 is a plan view showing a memory cell portion of a conventional semiconductor memory device.

FIG. 6 is a sectional view taken along line XX of FIG. 5;

FIG. 7 is a plan view showing a memory cell portion of a semiconductor memory device in which resistance of a bit line is reduced.

FIG. 8 is a circuit diagram of FIG. 7;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 11 Silicon substrate 2, 12 Conductive region 3, 16 Gate electrode 4, 15 Gate insulating film 5, 17 Impurity injection region 6, 14 Auxiliary conductive region 7, 18 Select gate electrode 8, 19 Diffusion region 20 Interlayer insulating film 9, 21 Aluminum wiring 10, 22 Contact hole T1, T2 Transistor

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8246 H01L 27/112

Claims (2)

(57) [Claims] 1. A semiconductor substrate of one conductivity type, and a plurality of rows of conductive regions of opposite conductivity type arranged in parallel on a surface portion of the semiconductor substrate at a constant interval from each other and sandwiched between two rows. A plurality of auxiliary conductive regions arranged adjacent to each pair of ends of these conductive regions; and a plurality of gate electrodes arranged in parallel with each other on the semiconductor substrate so as to intersect with the conductive regions. And a first select gate electrode disposed between the end of one conductive region of each pair and the auxiliary conductive region, and between the end of the other conductive region and the auxiliary conductive region. A second selection gate electrode disposed over the semiconductor device, and a conductive line arranged on the gate electrode corresponding to each pair, and electrically connected to the auxiliary conductive region, respectively. The threshold voltage of the transistor formed by the conductive region and the gate electrode Is selectively changed in association with predetermined data. 2. The semiconductor memory device according to claim 1, wherein a width of said conductive region is widened at a portion adjacent to said auxiliary conductive region.