JPH06283689A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To expand the capacity of memory cells while the dropping of the operating speed of the memory cells is prevented by selectively fluctuating the threshold voltages of transistors formed of conductive areas and first gate electrodes in corresponding to prescribed data. CONSTITUTION:Gate electrodes 15 are arranged in conductive areas 11 so that the electrodes 15 can intersect the areas 11. Similarly, selection gate electrodes 16 are arranged so that the electrodes 17 can bridge the spaces between connecting conductive areas 12 and auxiliary conductive areas 13. Then aluminum wiring 18 are arranged in parallel with the conductive areas 11 in corresponding to the auxiliary conductive areas 13 and connected to the areas 13. In addition, the areas 13 are connected to the conductive areas 11 by the actions of the electrodes 16. Therefore, the conductive areas 11 are selectively connected to the aluminum wiring which become bit lines. In addition, the resistances and parasitic capacitances of the bit lines can be reduced. Moreover, currents are made to more easily flow to transistors from conductive line through the conductive areas and the access time to this semiconductor memory device is shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a structure of a memory cell of a read only memory.

[0002]

2. Description of the Related Art A read-only memory such as a mask ROM corresponds to a plurality of memory cells arranged in rows and columns.
A plurality of bit lines and word lines are arranged to cross each other. Generally, in the case of a ROM, one MOS transistor is associated with one memory cell, and data is determined by whether or not a transistor designated based on address data is turned on.
In such a read-only memory, for example, JP-A-3-
As disclosed in Japanese Patent No. 179775, there has been proposed a structure called a flat cell in which there is no isolation region for separating memory cells from each other and a bit line is formed of a diffusion layer.

FIG. 5 is a plan view of a memory cell portion of a conventional NOR type mask ROM, and FIG. 6 is a sectional view taken along line XX thereof. On the surface portion of the silicon substrate 1 having the P-type conductivity type, a plurality of conductive regions 2 serving as bit lines in which N-type impurities are diffused are arranged in parallel at regular intervals. The conductive region 2 is formed by implanting N-type impurity ions, for example, arsenic (As) ions, and is configured to serve as a source and a drain of a transistor forming a memory cell. On the silicon substrate 1 on which the conductive region 2 is formed, a plurality of gate electrodes 3 to be word lines are arranged so as to intersect with the conductive region 2 via the gate insulating film 4.
N-channel MOS transistor T with conductive region 2
Make up. Then, in the channel region of the transistor T (the substrate region below the gate electrode 3), an impurity implantation region 5 for selectively injecting P-type impurities into a high concentration is formed in association with the write data. As a result, the threshold voltage of the specific transistor T can be changed, so that it becomes possible to store data associated with the difference in operating characteristics of each transistor T.

FIG. 7 is a circuit diagram of the memory cell shown in FIG. 6, and FIG. 8 is a characteristic diagram showing the operation of the transistor.
The transistor T forming the memory cell is composed of a conductive region 2 and a gate electrode 3. The gate electrode 3 continuous in each row serves as a word line WL, and the conductive region 2 continuous in each column includes two types. It becomes the bit lines BL _H and BL _L. The bit lines BL _H and BL _L are alternately assigned to each column, and the power supply potential and the ground potential are applied to the respective bit lines BL _H and BL _L in the selected state. Become.

Normally, the threshold voltage V of each transistor T is
_As shown in FIG. 8, _T1 is a voltage V applied to the word line WL (gate electrode 3) when the memory cell is in the selected state.
When it is set lower than ₁ , and in the selected state, the current I ₁ flows between the source and the drain. Therefore, when the impurity is injected into the channel region, the operating characteristic of the transistor T shifts to the right side in the drawing as shown in FIG. 8, and the threshold voltage V _{T2 at} that time becomes higher than the voltage V _1. , The current does not flow between the source and the drain even when the transistor T is in the selected state. That is, in the transistor T in which the impurity-implanted region 5 is not formed, when the voltage V ₁ is applied to the gate electrode 3 with a predetermined potential difference provided between the adjacent conductive regions 2, the current is turned on. On the other hand, the transistor T in which the impurity implantation region 5 is formed
With respect to the above, even if the voltage V ₁ is applied to the gate electrode 3 and the voltage is set to a high level, the gate electrode 3 is not turned on and no current flows. Therefore, the presence / absence of the impurity region 5 selectively formed in the channel region of the transistor T at a desired address in association with the data of “1” and “0” is activated corresponding to the address data. It is determined by the detection of the current flowing between the conductive regions 2 of.

[0006]

In the above memory device, the LO is provided between the transistors forming the memory cell.
Since there is no isolation region such as COS and the size of the memory cell can be reduced, it is suitable for increasing the memory capacity. However, since the bit line is formed by the conductive region 2 formed by diffusing N-type impurities in the silicon substrate 1, the resistance value and the parasitic capacitance of the bit line itself increase, which causes a problem that high-speed operation cannot be achieved. ing. In particular, as the capacity of the memory cell increases, the length of the bit line becomes longer. Therefore, the reduction of the resistance and the capacity of the bit line is an issue for realizing high speed operation.

Therefore, an object of the present invention is to reduce the resistance value and the parasitic capacitance of the bit line, and to increase the capacitance of the memory cell while preventing the decrease of the operating speed.

[0008]

The present invention has been made to solve the above problems, and is characterized in that a semiconductor substrate of one conductivity type and a semiconductor substrate of a constant conductivity type are provided in the vicinity of the surface of the semiconductor substrate. A plurality of rows of conductive regions of opposite conductivity type that are arranged in parallel with a space therebetween, and a connection conductive region that connects one pair of the conductive regions that form a pair with two rows sandwiched therebetween.
An island-shaped auxiliary conductive region disposed adjacent to each of the connection conductive regions; a plurality of first gate electrodes that intersect the conductive region and are arranged in parallel with each other on the semiconductor substrate; A second gate electrode arranged on the semiconductor substrate across the connection conductive region and the auxiliary conductive region, and arranged on the first and second gate electrodes corresponding to the auxiliary conductive region. And a conductive line electrically connected to the auxiliary conductive region, respectively, and selectively changing a threshold voltage of a transistor formed by the conductive region and the first gate electrode in association with predetermined data. Is to let.

[0009]

According to the present invention, a plurality of conductive regions can be associated with a conductive line to be a bit line, and these conductive regions can be selectively connected to the conductive line according to address data. Also, the parasitic capacitance can be reduced. As a result, a current easily flows from the conductive line to the transistor specified according to the address data through the conductive region, and the access time is shortened.

[0010]

1 is a plan view of a memory cell portion of a semiconductor memory device according to the present invention, and FIGS.
It is sectional drawing of a line and a YY line. P-type silicon substrate 1
On the surface portion of 0, a plurality of N-type conductive regions 11 functioning as a source or a drain of the memory cell transistor are arranged in parallel with each other at regular intervals. The conductive regions 11 are arranged so as to cross the memory cell region, and each two columns are connected to each other in U-shape by connecting one end to the N-type connecting conductive region 12. Further, an independent N-type auxiliary conductive region 13 is arranged on the outer periphery of each connection conductive region 12 so as to be separated from the connection conductive region 12 by a predetermined distance. On the silicon substrate 10 on which the conductive regions 11, 12 and 13 are formed, a plurality of gate electrodes 15 made of polycrystalline silicon are arranged in parallel with each other across the conductive regions 11 with a gate insulating film 14 interposed therebetween. To be done. The gate electrode 15 serves as a word line, and a predetermined voltage is selectively applied to the column designated by the row address data. Select gate electrodes 16 made of polycrystalline silicon are similarly arranged on both sides of the gate electrodes 15 so as to extend over the connection conductive region 12 and the auxiliary conductive region 13. As a result, a selection transistor T2 having the selection gate electrode 16 as a gate and the connection conductive region 12 and the auxiliary conductive region 13 as a source and a drain is formed. For the select transistor T2, the conductive region 1
Since it is provided every four columns on one side of 1, the gate width can be set wide and the resistance value can be set sufficiently small depending on the size of the auxiliary conductive region 13. still,
Since adjacent ones of these select transistors T2 are driven by a common gate electrode, each select transistor T2 is configured to prevent conduction between the conductive regions 11 of each other.
A P-type impurity region 19 is formed between them.

Then, on the gate electrode 15 and the select gate electrode 16, an aluminum wiring 18 serving as a bit line is arranged in parallel with the conductive region 11 with an interlayer insulating film 17 interposed therebetween. The aluminum wiring 18 is associated with each auxiliary conductive region 13 and is provided with a contact hole 20.
Is electrically connected to the auxiliary conductive region 13. Therefore, each conductive region 11 is selectively connected to the auxiliary conductive region 12 by the on / off control of the select gate electrode 16.
The voltage applied to aluminum wiring 18 is received through connection conductive region 12 and auxiliary conductive region 13.

The memory cell region in which the gate electrode 15 is arranged on the conductive region 11 has the same structure as in FIG. 5, and the transistor T1 having the gate electrode 15 as the gate and the conductive region 11 as the source and drain is used. Is configured. Then, a P-type impurity implantation region 21 is selectively formed in the channel region of the transistor T so as to correspond to the data stored in the memory cell.

FIG. 4 is a circuit diagram of the memory cell and corresponds to FIG. Transistor T1 forming each memory cell
In the above, the gate electrodes 15 continuous in each row form a word line WL and are selectively activated by a selection signal based on row address data. Similarly, the selection transistor T2
, The selection gate electrodes 16 are common on both sides of the gate electrode 15, and the selection gate electrodes 16 form the selection control line SL. The aluminum wiring 18 forms the main bit line BL and is selectively activated upon receiving a selection signal based on the column address data. That is, the two aluminum wirings 18 are designated corresponding to the address data to apply the power supply potential and the ground potential to each, and the selection transistor T2 connected to the designated aluminum wiring 18 is turned on to turn on the conductive region 11. Is connected to the aluminum wiring 18, the conductive regions 11 in two adjacent columns are selectively activated. Here, with respect to each aluminum wiring 18, the voltage applied in the selected state is not fixed to either the power supply voltage or the ground voltage, and the power supply voltage and the ground voltage are changed depending on the combination of the selected bit lines BL. I am trying to switch.

To explain the selecting operation of this memory cell,
For example, the conductive regions 11 are sequentially arranged from the left side of the drawing in the order of a, b, ...
..F, aluminum wiring 18 is also A, B, C, D
And Therefore, when B and C are selected and a power supply voltage is applied to B and a ground voltage is applied to C, a and d are power supply voltages, and c and f
Becomes the ground voltage, and the transistor T in one row between c and d
1 has been selected. At this time, since the power supply voltage is applied to A and B and b and e become the power supply potential,
Even if a and f are brought into a selected state at the same time as c and d, no current flows from a, c or d, f to b, e, and between the transistor T1 between a and d or between e and f. The transistor T1 of is not selected. Similarly, select B and D and set B to the power supply voltage,
When the ground voltage is applied to D, d becomes the power supply voltage and e becomes the ground voltage, and the transistor T1 between d and e is selected. In this way, the selection of the bit lines BL is performed by either a pair adjacent to each other or a pair with one in between. Therefore, by the combination of the selection of the conductive region 11 and the selection of the gate electrode 15, one of the matrix-arranged transistors T1 is designated according to the address data, and the conductive region by turning on / off the MOS transistor T1 at this time is specified. The potential fluctuation of 11 is determined by the sense amplifier selectively connected to the aluminum wiring 17.

In the above memory cell, a plurality of blocks may be provided along the aluminum wiring 18 and block selection may be performed by the selection operation of the selection transistor T2. In this case, all the selection transistors T2 in the non-selected block are fixed to the off state.

[0016]

According to the present invention, since the resistance value is reduced by shortening the length of the conductive region and the resistance of the select transistor is reduced, the data determination period is shortened, so that high speed operation can be supported. Become. Further, by using the select transistor for selectively connecting the conductive region to the bit line also for block selection of the memory cell, it is possible to minimize the increase in the number of select transistors. Further, since the gate width of the select transistor can be widened, the resistance value can be set low, and the effect of reducing the resistance value of the conductive region is not hindered.

[Brief description of drawings]

FIG. 1 is a plan view showing a part of a memory cell of a semiconductor memory device of the present invention.

2 is a cross-sectional view of the memory cell of FIG.

3 is a cross-sectional view of the memory cell of FIG.

FIG. 4 is a circuit diagram of the memory cell of FIG.

FIG. 5 is a plan view showing a part of a memory cell of a conventional semiconductor memory device.

6 is a cross-sectional view of the memory cell of FIG.

FIG. 7 is a circuit diagram of the memory cell of FIG.

FIG. 8 is a characteristic diagram of a transistor included in a memory cell.

[Explanation of symbols]

 1, 10 Silicon substrate 2, 11 Conductive region 3, 15 Gate electrode 4, 14 Gate insulating film 5, 20 Impurity injection region 12 Connection conductive region 13 Auxiliary conductive region 16 Select gate electrode 17 Interlayer insulating film 18 Aluminum wiring 19 Contact hole T1 , T2 transistor BL bit line WL word line

Claims (2)

[Claims] 1. A semiconductor substrate of one conductivity type and a plurality of conductive regions of opposite conductivity type arranged in parallel in the vicinity of the surface of the semiconductor substrate at regular intervals and paired with two columns interposed therebetween. On the semiconductor substrate, connecting conductive regions that connect the conductive regions to each other at one end, island-shaped auxiliary conductive regions arranged adjacent to each of the connecting conductive regions, and intersecting the conductive regions. A plurality of first gate electrodes arranged in parallel with each other, a second gate electrode arranged on the semiconductor substrate across the connection conductive region and the auxiliary conductive region, and the auxiliary conductive region. Conductive lines arranged on the first and second gate electrodes corresponding to the regions and electrically connected to the auxiliary conductive regions, respectively, and the conductive regions and the first gate electrodes are Predetermine the threshold voltage of the transistor to be formed A semiconductor memory device characterized in that the semiconductor memory device is selectively changed in association with the above data. 2. A voltage is selectively applied to the first gate electrode to activate it in accordance with row address data, and a predetermined voltage is applied to the second gate electrode in response to column address data. A conductive state is established between the connection conductive region and the auxiliary conductive region, and a voltage is selectively applied from the conductive line to the conductive region through the auxiliary conductive region to activate the conductive region. The semiconductor memory device according to claim 1.