JPS6329833B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a fixed memory device using an insulated gate field effect transistor (hereinafter referred to as MISFET), and particularly to a fixed memory device using an insulated gate field effect transistor (hereinafter referred to as MISFET).
This invention relates to a vertical fixed storage device in which two are connected in series. The applicant first developed depletion type MISFET and enhancement type MISFET.
A fixed memory device, ROM ( Read O
nlyMemory (hereinafter sometimes simply referred to as ROM). In such a ROM, the enhancement type MISFET is turned on or off depending on the operating voltage, as shown in, for example, JP-A-52-30388, JP-A-52-58452, and JP-A-52-106665. Depletion type MISFET is
Taking advantage of the fact that MISFETs are always on regardless of the operating voltage, we can arrange MISFETs in a matrix of rows and columns.
The MISFETs in each column are arranged in a so-called vertical configuration so that they are connected in series with each other, and selected locations in the matrix are arranged as enhancement type storage elements, and the rest are arranged as depletion type wiring elements. It is characterized by By using this method,
Extremely high degree of integration on a single semiconductor substrate
Since it is possible to form a ROM device and the manufacturing method is simple, it is possible to improve the manufacturing yield compared to the so-called horizontal ROM in which MISFETs used as memory elements are connected in parallel with each other. I can do it. However, in such a vertical ROM device, when an attempt is made to create a large capacity storage device by increasing the number of MISFETs connected to a series circuit of MISFETs constituting a unit circuit, the resistance of the series circuit increases. As a result, the time constant between the series circuit and other circuits related to it becomes large, making it impossible to achieve high speed. Therefore, the main object of the present invention is to provide a vertical ROM device structure suitable for increasing capacity and speed. Furthermore, another object of the present invention is to provide a layout of a vertical ROM device suitable for increasing capacity, which can be integrated at high density on one semiconductor substrate using semiconductor integrated circuit technology. . According to the ROM device of the present invention, a fixed memory circuit matrix to be formed by a set of unit series circuits of MISFETs is divided into a plurality of parts, and each divided fixed memory circuit matrix part is connected to the fixed memory circuit matrix part. Selection circuit means are provided for selecting each of the. Furthermore, the common output terminal is provided with potential supply circuit means, such as load circuit or precharge circuit means, for applying a potential to the common output terminal. Thereby, the output terminal and the potential supply circuit means are commonly used for each divided fixed storage matrix section. Further, according to the present invention, in order to commonize the column selection circuit means of the series circuits of each column constituting each divided fixed storage matrix section, it is possible to connect the common output terminal and the plurality of divided fixed storage matrix sections. It can also be inserted into. The objects and benefits of the present invention will be better understood from the description taken in conjunction with the following drawings. FIG. 1 shows a circuit diagram of a persistent storage device according to one embodiment of the invention. In Figure 1, ROM ₁₁ , ROM ₁₂ , ROM ₂₁ and
The ROM ₂₂ is a unit fixed storage device in which a predetermined storage capacity determined based on the system design is divided into four fixed storage devices, and each fixed storage device is
a fixed memory matrix section ME and a fixed memory matrix selection circuit section SE for selecting each of the fixed memory matrix sections ME between fixed memory devices;
It consists of Multiple unit storage devices ROM ₁₁ , ROM ₁₂ , ROM ₂₁
and ROM ₂₂ each have P channel MISFETQ ₅ to
Q has ₂₀ . That is, in the column
MISFETs are connected in series, in a row, each column
Conductive lines L ₅ to L ₈ are arranged to commonly connect the gate electrodes of the MISFETs. Selected MISFETs _{Q 5} to _{Q 20} that make up the memory matrix section ME are enhancement type MISFETs E , and the remaining ones are depletion type MISFETs.
Consists of MISFET D. Enhancement type
The matrix position pattern in which MISFET E is selected differs between unit storage devices. This enhancement type MISFET selection pattern is determined according to the system design of the electronic device using the fixed storage device. If the enhancement type MISFET is placed in the position determined in a certain row and a certain column,
If E exists, it can be defined that data “1” is stored at that position, and conversely, if that position is depletion type FET D , data “0” is stored. It can be defined as something that exists. Of course, contrary to this definition, the existence of the enhancement type MISFET E may be defined as data "0". The selection circuit section SE of each unit fixed storage device is connected to the line
It consists of P channel enhancement type MISFETs _Q1 to _Q4 whose gate electrodes are commonly connected by _L9 . Multiple unit fixed storage devices ROM ₁₁ , ROM ₁₂ ,
There is a geometric line between ROM ₂₁ and ROM ₂₂ .
They are also arranged in a matrix of R ₁ , R ₂ and columns C ₁ , C ₂ . In the unit fixed storage devices arranged in the same column, the series circuits of P-channel MISFETs arranged in the corresponding column of each unit fixed storage device are connected in parallel to each other by conductive lines L ₁ to L ₄ . For example, placed in column C ₁
MISFETQ ₅ to _{Q 8} in ROM ₁₁ and ROM ₂₁
are connected in parallel to each other by a line _L1 . ROM _S1 and ROM _S2 are column selection circuit sections connected between common output terminals OUT ₁ and OUT ₂ and each unit fixed storage device. Each column selection circuit block ROM _S1 ,
ROM _S2 has P channels arranged in matrix.
Consisting of MISFETQ ₂₁ ~ Q ₅₂ , MISFET in the same row
The gate electrodes of are commonly connected. The MISFETs _{Q 21} to _{Q 52} constituting this column selection circuit section are selectively enhanced-type MISFETs so as to select a specific column series circuit in the unit fixed storage device according to a selection signal applied to the gate electrode line.
MISFET E , and the remaining ones are depletion type MISFET D. Q ₀₁ and Q ₀₂ are common output terminals OUT ₁ and OUT ₂
P-channel enhancement type provided to precharge the capacitances C ₀₁ and C ₀₂ that exist between the reference potential source (earth potential) and the
MISFET, potential source V _DD and common output terminal OUT ₁ ,
OUT ₂ , and a timing pulse signal φ _P is applied to their gate electrodes. In the memory circuit section ME of the unit fixed memory devices _ROM11 , _ROM12 , _ROM21 , and _ROM22 , address signals _Vn1 to _Vn4 are applied to the gate electrode lines _L5 to _L8 arranged in rows. In the selection circuit section SE, selection signals V _S1 and V _S2 are applied to the gate electrode L ₉ depending on the row. Column selection signals V _C1 to V _C8 are applied to the common gate electrode line of the column selection circuit units ROM _S1 and ROM _S2 . To explain the operation, first the column selection circuit section
Column selection signals V _C1 to _{V C8} are applied to selected ones of the gate electrode lines of ROM _S1 and ROM _S2 , and the selected column with the series circuit of a predetermined unit fixed storage device is connected to the output terminal OUT ₁ or OUT. Connected to ₂ . For example, only column selection signal V _C1 is of enhancement type.
Level that turns on MISFET (-V _DD level)
When the voltage changes to , MISFETQ ₂₁ turns on. At this time, other MISFETs Q ₂₂ ~ _{Q 28} connected in series with Q ₂₁
are all depletion type, so V _C2 ~
Even if the signal level of V _C8 is off level (earth level), the series circuit of Q ₂₂ to _{Q 28} is in a conductive state, so as a result, the output terminal OUT ₁
is connected to one specified output terminal P ₁ of each fixed storage device ROM ₁₁ and ROM ₂₁ . When a timing pulse φ _P is applied for precharging while a specific column is selected by the column selection signal, MISFETQ ₀₁ , Q ₀₂
is in the on state, and each common output terminal OUT ₁ ,
Output capacitance equivalently connected to each of OUT ₂
Precharge C ₀₁ and C ₀₂ . After the output capacitors C ₀₁ and C ₀₂ are precharged to a predetermined potential by applying the timing pulse φ _P for a predetermined time, the selection circuit section SE of the unit fixed storage device
Then, by applying the selection pulse signal V _S1 or V _S2 , the memory circuit section ME in the specified unit fixed memory device is made operational. for example,
When V _S1 is on level and V _S2 is off level,
ROM ₁₁ and ROM ₁₂ are selected and made operational. In this state, as described above, since a certain column has been selected, the corresponding specific column of the selected unit fixed storage device will be selected. Following the example above, V _C1 applied to MISFETQ ₂₁ selects columns Q ₅ -Q ₆ and V _C1 applied to Q ₁ selects a particular fixed storage device.
Only the series circuits _Q5 to _Q6 of ROM ₁₁ are selected.
Therefore, for example, in this state, if only V _n1 of the address signals V _n1 to V _n4 is off level (earth level), the transistor Q ₅
Only the state of is transmitted to the output terminal OUT ₁ . In other words, since _Q5 of ROM ₁₁ is of the depletion type, the series circuit of _Q5 to _Q8 becomes conductive.
The series circuit discharges the precharge voltage of the output capacitor C ₀₁ so that the output level of the output terminal OUT ₁ is set to the off level (earth level). The signal levels of the address signals V _n1 to _{V n4} can be set to an off level (earth level). When you want to judge the state of Q ₅ , as mentioned above, you set V _n1 to off level and the others to on level (-V _DD level), but if you want to judge the state of Q ₆ in the same way, only V _n2 should be set as off-level. If Q ₆ is selected by V _n2 , the series circuit of Q ₅ to _{Q 8} becomes non-conductive, so the precharge voltage of the output capacitor C ₀₁ is maintained, and as a result, the output terminal The output level of OUT ₁ is on level (-V _DD level). In this way, column selection circuit section ROM _S1 and
ROM _S2 works to select specific columns,
Address signals V _n1 -V _n4 cause a particular row to be selected. Further, the selection signals V _S1 to V _S2 applied to the fixed storage device selection circuit section SE select a specific unit fixed storage device. It is also possible to arrange the fixed memory circuit section SE on the ground side of the memory circuit section ME (provide _Q1 on the source side of _Q8 ), but as in the above embodiment, it is possible to arrange it on the power supply side of the series circuit (i.e. , Q ₁ on the drain side of Q ₅
For example, if the series circuit of Q ₅ to _{Q 8} of ROM ₁₁ is selected by V _S1 , the series circuit of Q ₅ to _{Q 8} of ROM ₂₁ is
Due to the off state of MISFETQ ₁ in ROM ₂₁ ,
Since it is released from the ROM ₁₁ , the stray capacitance C _S that the series circuit of Q ₅ to _{Q 8} of the ROM ₂₁ has with respect to the ground potential is not connected to the output capacitance C ₀₁ .
Therefore, an increase in the output capacitance C ₀₁ can be prevented, and as a result, a decrease in switching speed can be prevented. In addition, the common output terminal OUT ₁ of column C ₁ and the common output terminal OUT ₂ of column C ₂ are separated, but have one common output terminal and one precharge terminal.
It can also be a MISFET. According to the circuit arrangement of the fixed storage device of the present invention, there is no need to provide means for applying a potential to the output line, such as a precharge MISFET, for each divided unit fixed storage device. That is, one set of precharge means can be used in common for a plurality of unit fixed storage devices. Furthermore, since a common output terminal is used for each divided unit fixed storage device, a logic circuit such as an AND or OR circuit for synthesizing a plurality of output signals can be omitted. Furthermore, according to the present invention, the column selection circuit unit selects a plurality of unit fixed storage devices arranged in the same column.
One set or an omitted scale circuit may be used. Therefore, according to the present invention, a large capacity fixed storage device can be realized on one semiconductor substrate. In order to facilitate understanding of the present invention, the above-mentioned embodiment assumes that the storage capacity of the unit fixed storage device is 16 bits (4 rows x 4 columns), and that two sets of fixed storage devices are arranged in the same column. The diagram shows the case where
In a more commercially produced fixed storage device, according to the invention, for example, 64 rows by 8 columns (512
A large-capacity fixed storage device can be realized by arranging four sets of bits in the same column as the storage portion of a unit fixed storage device. Another advantage of the present invention is that by increasing the number of divided unit fixed storage devices, the number of series-connected MISFETs in the unit fixed storage devices can be reduced and the switching speed can be increased. . For example, in the embodiment described above,
The two sets of ROM ₁₁ and ROM ₂₁ , which are unit fixed storage devices with 4 rows and 4 columns, can be viewed as two parts of one fixed storage device with 8 rows and 4 columns. As a result, the equivalent resistance of the series circuit is reduced in a series circuit of four MISFETs as in the present invention, compared to a series circuit of eight MISFETs, forming a shorter time constant circuit for precharge capacitance. This allows the readout time to be shortened. Furthermore, at this time, the stray capacitance C _S of the series circuit can also be reduced, so it is expected that the precharge time will be shortened. In this way, the present invention reduces the number of MISFETs to be connected in series in a column of a vertical fixed storage device ROM.
Divide into several series circuits and
Since this can be regarded as a reduction in the number of MISFETs, it is possible to increase the speed. When the fixed memory device according to the present invention is laid out on one semiconductor substrate using semiconductor integrated circuit IC technology, the entire fixed memory device including the column selection circuit section is laid out on one semiconductor substrate.
MISFET matrix circuits can be geometrically arranged precisely in rows and columns. FIG. 2 shows a partial plan view when the fixed storage device shown in FIG. 1 is formed on a single silicon semiconductor substrate to form a semiconductor integrated circuit IC;
The figure shows a sectional view taken along - in FIG. In FIGS. 2 and 3, 1 is an N-type silicon semiconductor substrate. 12 to 20 are polysilicon wiring layers that act as gate electrodes of MISFETs and signal input conductors; 1 to 11 are polysilicon wiring layers 1
P-type diffusion layers 2 to 20 are diffused as part of a mask, each diffusion layer operates as a source or drain of a MISFET, and P-type diffusion layers 1 to 11
MISFETs are formed at the intersections between and the polysilicon wiring layers 12 to 20. That is, as is clear from the cross-sectional view of FIG. 3, the MISFET has diffusion layers 2 to 5 functioning as a source region and a drain region formed in a self-aligned structure by a polysilicon wiring layer, and A thin (for example, 1000 Å) gate insulating film 24 made of silicon oxide is formed at the portion where the polysilicon wiring layer and the diffusion layer are to intersect.
have. The region 23 is a region into which P-type impurity ions are introduced by ion implantation technology, and is selectively formed in the region where the depletion type MISFET is formed. 25 is a relatively thick field insulating film made of silicon oxide, for example, 1 to 2 μm thick, and covers the surface of the P-type diffusion layer and the surface of the polysilicon wiring layer for the gate electrode. . L ₁ , L ₂ and L ₃ are polysilicon wiring layers 14
An aluminum wiring layer is provided on the field insulating film 25 across the field 18, and is in ohmic contact with the P-type diffusion layer at contact portions 21 and 22. This aluminum wiring layer takes the form of a P-type diffusion layer and a two-layer wiring in each column, and can be arranged in parallel thereto. Such structures can be formed, for example, according to the processes disclosed in JP-A-52-30388 and JP-A-52-106689. As is clear from FIGS. 2 and 3, according to the present invention, all the MISFETs can be arranged in an orderly manner in a matrix, making the layout easy and reducing the area occupied. can be reduced. FIG. 4 is a circuit diagram showing another embodiment of the present invention constructed using P-channel MISFETs. In this embodiment, a part of the column selection circuit is incorporated as part of a unit fixed storage device. In Figure 4, ROM _S1 and ROM _S2 are column selection circuit sections. ROM ₁₁ , ROM ₁₂ , ROM ₂₁ and ROM ₂₂
is a unit fixed storage device, and each device is composed of a storage circuit section ME, a storage circuit selection circuit section SE, and a column selection circuit section CE. In each unit fixed storage device (for example, ROM ₁₁ ), a series circuit of P-channel MISFETs (including enhancement type E and depletion type D )
are divided into a plurality of groups, and are connected in parallel to each other in each group. The column selection circuit section CE in the unit fixed storage device is added to select a predetermined series circuit in each group, and the column selection circuit matrix ROM _S1 operates to select a predetermined column group. . That is, only a predetermined column of ME of the unit fixed storage device is selected by the combination of ROM _S1 and CE. The operation of such a fixed storage device will be explained in substantially the same manner as in FIG. 1, so the explanation thereof will be omitted. FIG. 5 shows a plan view of the semiconductor integrated circuit device of the fixed storage device of FIG. 4. The structure of this semiconductor integrated circuit is similar to that shown in FIGS. 2 and 3. In FIG. 5, 50 is an N-type silicon semiconductor substrate, 26 to 35 are polysilicon wiring layers used as a common gate electrode, and 36 to 45 are arranged on both sides of the polysilicon wiring layers 26 to 35. Ta
The P-type diffusion layer 51, which acts as the source or drain of the MISFET, is a depletion type
P-type impurity ion implantation regions 48 and 49 for forming a MISFET connect aluminum wiring layers 46 and 47 to P-type diffusion layers 38 and 45.
This is a contact part for making ohmic contact with. An advantage of such an IC structure is that the contact portion of the diffusion layer to the aluminum wiring layer for connecting unit fixed storage devices can be effectively enlarged. That is, in the case of the embodiment shown in FIG. 2, around the contact parts 21 and 22 of each of the aluminum wiring layers L ₁ , L ₂ , and L ₃ , P is placed so that the contact parts do not protrude.
Although it is necessary to increase the area of the type diffusion layer, the fifth
In the embodiment shown in the figure, it is sufficient to provide common contact portions 48 and 49 for the two columns, so there is no need to particularly increase the area around the contact portion of the P-type diffusion layer. The two rows thus formed can be effectively utilized for installing contact parts. Therefore, the structure shown in FIG. 5 can increase the integration density of MISFETs in the lateral direction compared to the structure shown in FIG. 2. FIG. 6 is a circuit diagram of another embodiment which is a partial modification of the embodiment of FIG. 4. Circuit parts corresponding to those in FIG. 4 are designated with the same reference numerals. This fixed storage device omits the storage circuit selection circuit section SE of the unit fixed storage device in FIG.
AND circuits, AND ₁ and AND ₂ are provided, and the ROM selection signal V _S1 and column selection signals V _C1 ′, V _C2 ′ are
This is applied to the AND circuit, AND ₁ and AND ₂ . According to such an arrangement, a reduction in the number of elements in the fixed storage device can be expected. FIG. 7 is a circuit diagram showing still another embodiment of the present invention.
MISFETs are indicated schematically by the symbol ○ or □. The ○ mark indicates an enhancement type P-channel MISFET, and the □ mark indicates a depletion type P-channel MISFET. In this fixed storage device, a column selection circuit section CE controlled by column selection signals V _C1 to V _Co is provided in each of the divided unit fixed storage devices ROM ₁₁ , ROM ₂₁ , and ROM ₃₁ . There is. Furthermore, unit fixed storage devices ROM ₁₁ , ROM ₂₁ ,
The ROM ₃₁ includes a ROM selection circuit section SE provided for selecting between unit fixed storage devices, and a fixed storage circuit section ME provided for storing data.
Contains. In the ROM selection circuit SE,
When the ROM selection signal V _S1 is applied, the fixed memory circuit section
Address signals V _n1 to _{V no} for selecting a predetermined row are applied to each row of the ME. The MISFET series circuits of each unit fixed storage device are connected in parallel to each other. A common output terminal OUT ₀ is provided for each unit fixed storage device, and a switching circuit is provided for precharging the output capacitor C ₀ connected to this common output terminal for a predetermined period of time.
MISFETQ ₀ is provided. According to such a fixed storage device, a specific fixed storage device is selected by the SE, a certain specified column in the specified fixed storage device is selected by the CE, and the address signal V _n1 is selected by the CE. ~
V _no specifies a certain row within a particular column. The resulting data will be sent to the output terminal
Output from OUT ₀ . In this way, each unit fixed storage device can be configured with one precharge MISFET. This embodiment is applied particularly when the number of columns is small and the occupied area does not increase significantly even if the column selection circuit section is installed in each unit fixed storage device. In some of the embodiments described above, the load capacity
I mentioned a so-called ratioless type circuit that charges C ₀ in advance, but it is not suitable for pre-charging.
The output signal may be extracted by replacing the MISFETs _{Q 0} , Q ₀₁ , and Q ₀₂ with load MISFETs to provide a certain impedance and constructing a ratio type circuit. Further, in the above-mentioned embodiment, an embodiment using a P-channel, silicon gate type MISFET was described, but the present invention uses an aluminum gate type MISFET.
It can be applied to devices using other MIS type elements such as MISFET. FIG. 8 shows a circuit diagram of another embodiment of a fixed storage device configured with a so-called complementary MISFET (or CMOS) using a P-channel type MISFET and an N-channel type MISFET. In FIG. 8, the unit fixed storage device ROM _n is N
Channel enhancement type MISFETQ _R1 ~
A unit fixed storage device selection circuit section SE consisting of Q _Ro ;
Consisting of N-channel MISFETQ _n1 to _{Q no} , the selected one is an enhancement type E fixed memory circuit section ME, and an N-channel enhancement type MISFETQ _D provided to determine the timing for determining the memory state. and a state determination circuit section DI. Column selection circuit section ROM _S is N channel
MISFETQ consists of _S1 ~ Q _So , column selection signal V _C1 ~
In order to select a specific column according to the signal level of V _Co , the selected MISFETs _{Q S1} to Q _So are of enhancement type E. This column selection circuit section ROM _S is provided in common between a large number of unit fixed storage devices arranged in the same column and the common output terminal OUT ₀ . Q ₀ is a P-channel enhancement type MISFET for precharging, and operates to precharge the output capacitance C ₀ for a certain period of time. Such a fixed storage device also performs the same operation as the fixed storage device shown in FIG. In the embodiment shown in FIG. 8, SE can also be used as MISFETQ _D , but if SE is omitted, as mentioned above,
The stray capacitance C _S of the MISFET series circuit of a certain unit fixed storage device is combined as the stray capacitance of the MISFET series circuit of the corresponding column of another unit fixed storage device, which is undesirable from the viewpoint of speeding up.
In this embodiment, the SE acts as a so-called electrical isolation means between unit fixed storage devices. As is clear from the above description, according to the present invention, a vertical fixed storage device having a large storage capacity and high speed can be obtained. The present invention can be modified in various ways without departing from its spirit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a fixed storage device according to the present invention. FIG. 2 is a plan view of a semiconductor integrated circuit in which the fixed storage device shown in FIG. 1 is configured in the form of a semiconductor integrated circuit. FIG. 3 is a partial sectional view taken along a portion of the semiconductor integrated circuit shown in FIG. 2. FIG. 4 is a circuit diagram showing another embodiment of the fixed storage device according to the present invention. FIG. 5 is a plan view of the fixed storage device shown in FIG. 4 configured in the form of a semiconductor integrated circuit. FIG. 6 is a circuit diagram of a fixed storage device according to the present invention, which is a partial modification of the circuit of the fixed storage device shown in FIG. 4. 7 and 8 are circuit diagrams showing still other embodiments according to the present invention. ROM _S1 , ROM _S2 , ROM _S ... Column selection circuit section,
ROM ₁₁ , ROM ₁₂ , ROM ₂₁ , ROM ₂₂ ...unit fixed storage device, ME...fixed memory circuit section, SE...memory selection circuit section, _Q0 , _Q01 , _Q02 ...precharge MISFET.

Claims (1)

[Scope of Claims] 1 Each includes insulated gate field effect transistors selectively arranged in rows and columns and provided as storage elements connected in series in each column, the insulated gate field effect transistors In each row, the gate electrode of the effect transistor includes a plurality of commonly connected fixed memory circuit sections, one common output terminal, and the insulated gate field effect transistor for the memory element in each column of each fixed memory circuit section. a column selection circuit unit for selectively coupling a series circuit of the plurality of fixed memory circuits to the common output terminal; and a fixed memory circuit unit coupled to each of the plurality of fixed memory circuit units, the fixed memory circuit units being selectively operable. a memory selection circuit unit for supplying a predetermined potential to the common output terminal according to the memory content of the memory circuit unit, the potential supply being coupled between the common output terminal and a certain potential source; 1. A fixed storage device comprising circuit means. 2. A patent claim characterized in that the potential supply circuit means comprises an insulated gate field effect transistor used as a switch element for precharging a capacitance existing between the common output terminal and the reference potential source. The fixed storage device according to item 1. 3. The column selection circuit section is characterized by comprising at least one element that is provided between the plurality of memory circuit sections and the common output terminal and is commonly provided to each of the memory circuit sections. A fixed storage device according to claim 1 or 2. 4. Claims characterized in that the column selection circuit section comprises a plurality of circuits provided for each of the memory circuit sections between each of the memory circuit sections and the common output terminal. The fixed storage device according to item 1 or 2. 5. The column selection circuit unit includes a plurality of first circuit units respectively coupled to each of the memory circuit units, each of the memory circuit units, and the first circuit unit provided corresponding thereto. 3. The fixed storage device according to claim 1, further comprising at least one second circuit section provided in common with the fixed storage device.