JPS5818959A - Memory cell arrangement - Google Patents

Abstract

PURPOSE:To obtain an ROM cell alley of large capacitance without lagging access time by a method wherein, in the case of ROM IC, the memory element consisting of MOS transistors is connected in series and in parallel to row selective lines or column selective lines. CONSTITUTION:The diffusion layers 6-9 having a column signal is connected in parallel to the contact 10 which constitutes an MOS cell alley, the MOS transistors of the polycrystalline Si on the row selective line 2 are connected in eight- stage series, and the ROM cell alley of four-parallel and eight-stage series connection is formed. The memory cell is constituted as above, and the column signal lines 6-9 on the diffusion layer which were connected in parallel to the contact 10 are selected by column signal selective lines 3 and 4. At this point, the interval in the column direction is determined by the channel width of the transistors and the metal width which is equal to the former, but the interval at the contact part 10 is provided wider than the above, because a hole is provided there. Also, the row interval is determined in accordance with the arragement of the series connection of the eight-stage transistors as shown by 2 in the diagram and the arrangement of the transistor to be used for two-step switching as shown by 3 and 4 in the diagram.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides Read-on Memo! The present invention relates to a memory circuit of a J(ROM) integrated circuit. The present invention provides that the storage circuit section of a read-only memory integrated circuit (hereinafter referred to as ROM) is constructed by serially and parallelly connecting (hereinafter referred to as series-parallel connection) memory elements (hereinafter referred to as memory cells) consisting of Mo1 transistors. It is characterized by being composed of

Recent developments in large-scale integrated circuits (BS engineering) have been remarkable.
There has been remarkable progress in improving the performance of FF microprocessors and increasing the speed and density of semiconductor memories. Under these circumstances, many microprocessor-applied products have been developed, and as a result, small-sized, large-capacity ROMs are required.

The configuration of a typical ROM is shown in FIG.

Among these, the part that occupies the largest area of the ROM chip is the memory cell matrix array section (hereinafter referred to as the cell array) shown in FIG. 1 (5), which is composed of memory cells. Therefore, when increasing the capacity of mesori, it is required to reduce the stacking capacity of this cell array.

When a conventional ROM cell is constructed with MOS transistors, the address signal is basically divided into two parts inside the ROM chip, decoded into a row selection signal and a column selection signal, and then a memory cell is placed at the intersection of each matrix. MOS for cells
) A method is used in which 1-bit data fixed in a transistor is selected. FIG. 2 shows a basic memory cell 1
This is a cell array consisting of one contact and one contact.

In this cell array, one contact portion is used for one memory cell, so contacts with the same capacity as the memory cell are used, and the area of the cell array is large. FIG. 3 shows a case where two memory cells are connected in parallel to one contact. □This cell array has half the area of the contact area occupied by one memory cell compared to the cell array shown in Figure 2, and although the cell array area is smaller than that shown in Figure 2. , half the number of contacts as memory cell capacity is used, and the chip area is still large.

This is a case in which they are connected in series for one takt. The number of stages of these MOS transistors connected in series is generally one stage (1.2.!).

), the contact area occupied by the memory cell fim is '/2'', and if the number of series stages is increased, the size of the memory cell becomes only the size occupied by the MOS transistor. . This series connection method has a smaller memory cell size than the parallel connection method shown in FIG. 3, and can integrate a large amount of ROM data with high density.
On the other hand, it has the disadvantage that the access time depends on the number of M (Ml) transistors connected in series and becomes slower as the number of transistors in series increases.

The present invention provides such a memory with fast access time.
By appropriately combining a cell parallel connection circuit and a memory cell series connection circuit capable of increasing density, access time is fast and the chip size is small. Efficient memory
It provides a cell array.

FIG. 5 is a series-parallel deaf ROM cell array according to the present invention. (6) e (7
), (s), and (9) column signals are connected in parallel, and the row signal line (2) has an MOI of 9) made of polysilicon.
This is a ROM cell array with 4 parallel and 8 stages connected in series, in which 8 stages of transistors are connected in series. (6)e C7”) # (8) connected in parallel to the contact of (10)
The column signal line using the diffusion layer #(9) is (5) # (4)
is selected by the column signal selection line. For example, if the (MCI) transistor in (12) is a depletion expansion type, and the MOS) transistor in (13) is an enhancement type, then (
When the row selection line (14) and the column selection line (3) are selected, the diffusion layer (A) is selected and connected to the contact (10).

Regarding the mesori cell array, fi[ in the column direction is equal to the channel width and metal width of the M08 transistor constituting the mesori cell. It becomes wider and is determined by the metal spacing in this part. Hence,
At the root of Figure 5, put one contact (10) in the two diffusion layers C6) and (7), and then add (8) # (9 ) diffusion layer (1
0), four diffusion layers are inserted in parallel, resulting in an efficient cell array. Next, regarding the line spacing, considering the access time of a general 0M0S processor, etc., we will use a series connection of 8 stages of MOS transistors like 5e (2) and a series connection like (3) #(4) O. An efficient cell array is constructed with two stages of diffusion layer switching MOS transistors. In this way, as shown in FIG. 5, two side-by-side diffusion layers are arranged facing one contact, and eight memory cells are connected in series to each diffusion layer. Furthermore, a series-parallel connected cell array was invented in which the diffusion layers were selected by two column signal selection lines.

As described above, by using the series-parallel connected memory cell array according to the present invention, a large capacity ROM cell array can be realized without slowing down the access time.

[Brief explanation of the drawing]

FIG. 1 is a block Φ diagram of a general ROM.・Address row decoder 5...Storage element) IJ sock array 6...
... Column selector and sense amplifier section 7 ... Output buffer 8 ... Output signal Figure 2 shows a basic memory cell with one contact per memory cell. Figure 1 showing the array...Metal (column selection line) 2...Polysilicon (row selection 3...
Contact part 4...Diffusion layer 5...Memory cell medium size 6...Field part In Fig. 3, two memory cells are combined into one Funtuff F. Figure 1 shows a memory cell array that goes in parallel...
Metal (column selection It) 2...Polysilicon (row selection ttS>5...
... Contact section 4 ... Diffusion layer 5 ... Memory cell size 6 ... Field section In Fig. 4, memory cells are connected in series to one contact. Figure 1 shows the connection to...Metal (column selection line) 2...Polysilicon (row selection 1ll) 3...
...Contact section 4...Diffusion layer 5...Memory cell size 6...Field section Fig. 5 is a diagram showing a series-parallel memory cell array. 1... Metal (column selection line) 2... Polysilicon (row selection line) 5...
... Polysilicon (column signal diffusion layer selection l1iI) 4...
...Polysilicon (column signal diffusion layer selection, l)5...
... Diffusion layer (source side) 6 ... Diffusion layer (column signal diffusion layer) 7 ...
Diffusion layer (column signal diffusion layer) 8... Diffusion layer (column signal diffusion layer) 9... Diffusion layer (column signal diffusion layer) 10.
...Contact part 11...Contact part 12...Diplegiran type MO8) transistor 13.
...Enhancement 1M03) Langister 14...Field Department and above Applicant Suiwa Seikosha Co., Ltd. Agent Patent Attorney Tsutomu Mogami Figure 114 Figure 5 260- +4 1

Claims (1)

[Claims] t In a read-on-memory (ROM) integrated circuit, M
o8) A memory element of a ride-on memory characterized in that a storage element constituted by a transistor is connected in series and parallel to a row selection line or a column selection line.
Cell array. 2. For one contact, two side-by-side diffusion layers are connected facing each other, and on each of the diffusion layers,
A patent claim characterized in that eight MOf9) transistors are configured in series as a memory element, and each diffusion layer is selected by two transistors further connected in series with the eight Mof9) transistors. The memory cell arrangement of the read-on memory according to item 1.