JPS5975488A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain a semiconductor memory device having low power consumption in a high speed, by processing logically a row decoder output via a pre- word line and a memory cell group selecting output, and performing the row selection in hierarchy to decrease the number of columns where DC current path is formed. CONSTITUTION:The output of row decoders 4- by the pre-word lines 15- formed with a polysilicon layer other than that forming word lines 3a, 3b- or metallic wires, and a selected output of memory cell group selecting lines 14a, 14b- are processed logically by AND ates 16a, 16b, 16c-. Further, the memory cell groups 1a, 1b- are selected and the word lines 3a, 3b- of the memory cell of the selected memory cell groups 1a, 1b- are selected in hierarchy. Thus, the number of columns forming the DC current path without using lots of row decoders is reduced and the semiconductor memory device having low power consumption in a high speed is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device that can improve access time and reduce power consumption.

[Prior art]

FIG. 1 is a block diagram showing a conventional semiconductor memory device. In the figure, (1) is arranged in a matrix,
The detailed circuit of the memory cell is shown in FIG. 2 (2a).
and (2b) are a pair of bit lines in a complementary relationship, (3) is a word line that activates memory cells (1) on the same row when selected, and (4) decodes row address information. A row decoder, (5) is a row address signal line, (6a) and (6b) are bit line loads connected to the bit lines (2a) and (2b), respectively, and (7) is a power supply terminal.

Note that in the memory cell (1) shown in FIG.
) and (8b) are MOS load elements, (9a) and (9b) are inverter transistors, (10a) and (10b) are access transistors, (1, 1a) and (1lb) are This is a store node for memory cell (1).

Next, regarding the operation of the semiconductor memory device having the above configuration, as an example, the store node (Ila) and the store node (1, 1
The case where the bits b) are written at the ``H'' level and the ``V-level'' will be explained. First, in the case of reading, the address information of the cell to be read is input to the address signal line (5). And this word line (3)
When the access transistor (10b) is activated, the access transistor (10b) storing the current level becomes conductive. Therefore, the bit line load (6b) is connected from the power supply terminal (7).

Bit i (2b), access transistor (10b
), current flows through the path of the inverter transistor (9b) and can be read out.

In a semiconductor memory device with this configuration, all memory cells on the same row are activated, so current flows into the memory cells from the two power supplies in all columns. becomes larger. Therefore, in order to reduce current consumption, a semiconductor memory device shown in FIG. 8 has been proposed. In this case, the row decoder (4) is arranged in the center of the memory cell plane, and the word lines are connected to the left word line (8a) and the right word line (8b).
By activating only the word line of the selected memory cell group of the left and right memory cell groups, a current bus is generated in only half of all the columns. Note that (12a) and (12b) are AND gates that select the left word line (8a) or right word line (8b), respectively, (18a) and (18b) are this gate, -) (12a) and (t 2b) is the gate Shingetsu line that opens the gate ◇ Next, FIG. 4 is a layout diagram showing a conventional semiconductor memory device constructed based on the idea of FIG. 8.

In this case, the row decoders (4a) and (4b) are arranged in a plurality of columns, and the word lines (8a) to (8d) are divided by a multiple thereof, thereby reducing the number of DC current paths.

However, conventional semiconductor memory devices require a large number of row decoders. For this reason, there were drawbacks such as an increase in chip area and a loss in speed performance and yield.

[Summary of the invention]

Therefore, an object of the present invention is to provide a high-speed, low power consumption, large capacity semiconductor memory device.

In order to achieve such an object, the present invention includes N memory cell groups in which a memory cell array in which memory cells are arranged in a matrix is divided in the column direction, and one of the N memory cell groups. A memory cell group selection line to be selected;
a row decoder for decoding row address information of a memory cell group to be accessed; a pre-word line connected to the output terminal of the row decoder; a selection signal of the memory cell group selection line and an output signal of the pre-word line. , and a word line connected to the output terminal of the AND gate. The front word line is formed of a polysilicon layer or a metal wiring layer separate from the word line, and will be explained below using an example.

[Embodiments of the invention]

FIG. 5 is a block diagram showing an embodiment of the semiconductor memory device according to the present invention.
) is placed. In the same figure, (14a)
T (14b) and (14c) are this 7l-E-
The memory cell group selection line 06 selects the recell groups (1a) to (1c), and the front word lines (16a) and (16) are arranged in parallel in the same direction as the word lines (8a) to (8c).
b) and (16C) have input terminals connected to the prefix word line 06) and memory cell selection lines (14a) to (14c), respectively, and output terminals to the word lines (8a) to (8C), respectively.
) is an AND gate connected to

AND gate (16a) + (16b) y (
16C) is shown in FIG. 6. In the figure, a drain electrode, a gate electrode, and a source electrode of a MOS transistor (MOS transistor) are connected to a front word line, a memory cell group selection line, and a word line, respectively. The drain electrode of the MOS transistor □□□ is connected to the word line, and the source electrode is grounded. The inverter means is MOS
) is arranged between the gate electrode of the transistor (2t+) and the gate electrode of the MOS transistor z.

Note that in order to reduce the memory cell area, the word line (
8a) to (8c) are MOS transistors (10a)
The word line (
These polysilicon layers 8a) to (8C) are formed of a different polysilicon layer or a metal wiring layer of aluminum, molybdenum, molybdenum silicide, or the like.

Next, the operation of the semiconductor memory device with the above configuration will be explained. First, when selecting a memory cell in the memory cell group (la), for example, the memory cell group (la) to be accessed is
The row address information of 1a) is decoded by the row decoder (4),
When one of the front word lines 05J is activated and a selection signal is applied to the memory cell group selection line (14, a), the MO
(16a)
is opened and the word line (8a) is activated.

Therefore, from a power supply (not shown) to a bit line (not shown),
The column current flowing into the memory cell group (1a) flows only through the columns in the selected memory cell group (1a).

Nao, the above is the memory cell (
Although we have explained the selection of 1), other memory cell groups (1)
Of course, the same can be done for b) and (1c). Further, although the case where the memory cell group is divided into eight cells has been described, it goes without saying that the same effect can be achieved even if the memory cell group is divided into N cells (N22).

In addition, if only the front word line (15+) is made of a low-resistance material, the length of the soot line is short even if the resistance is a little high, so the five memory cells can be accessed at high speed with a small capacitance. Since the gate structure is simple, the increase in chip area can be ignored.

Moreover, as shown in FIG. 7, the inverter (20)
It may be arranged outside the memory cell array, and the negative logic of the memory cell group selection signal may be applied to the gate of the MOS transistor. In this case, the configuration of the index becomes even simpler.

In FIG. 8, the AND gate (16a, L6b,
Another example is shown in the awn of the configuration 16c). In the same figure, the drain electrode of the MOS transistor OD,
The electrode and the source electrode are connected to the memory cell group selection line 1, respectively.
4a (14b, 14c), ml placement word line 05
+ and the word Ig8a (8b, 8c), the drain electrode of the Mo8+- transistor is connected to the word line, and the source electrode is grounded. On the inverter means side, the gate electrode of Mo8) transistor OI) and Mo, 9
) placed between the gate electrodes of the transistors. Even when the AND gate is configured as described above, the column current flowing into the memory cell group flows only in the column in the selected memory cell group, as in the previous embodiment.
Power consumption can be significantly reduced. In addition, when the AND gate is configured as shown in Figure 8, the preword line is insulated from the word line, so the gate capacitance of the memory cell does not parasitic on the preword line, and the preword line is connected to the row decoder. Furthermore, the word line is activated by the memory cell group selection line through the transistor Mo8), so that memory cells can be accessed quickly even if the resistance of the pre-word line is somewhat high. be able to. 1. Since the load capacitance of the memory cell group selection line is larger than that of the front word line, it is better to use a low resistance wiring material such as metal for the front word line or rather for the memory cell group selection line. Memory cells can be accessed at high speed. Furthermore, since the configuration of this AND gate is simple, the increase in chip area can be ignored.

In the above embodiment, the row decoder is placed at the edge of the chip, but it may be placed at the center of the chip. Further, the configuration of the present invention can be applied to a configuration in which row decoder groups are arranged in two or more columns, and similar effects can be achieved.

〔Effect of the invention〕

As described in detail above, according to the semiconductor memory device according to the present invention, row selection is performed hierarchically such that memory cell selection is performed in two stages: front word line and word line. Since the number of columns in which DC current paths can be accommodated can be reduced, it is possible to construct a high-speed, large-capacity semiconductor memory device with low power consumption.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional semiconductor memory device, FIG. 2 is a detailed circuit diagram of the memory cell in FIG. 1, FIG. 8 is a block diagram showing another conventional semiconductor memory device, and FIG. 4 is a block diagram showing a conventional semiconductor memory device. FIG. 6 is a layout diagram showing another conventional semiconductor memory device, and FIG. 6 is a block diagram showing an embodiment of the semiconductor memory device according to the present invention. FIG. 6 is a circuit diagram showing one embodiment of the configuration of an AND gate included in the configuration according to the present invention. FIGS. 7 and 8 are circuit diagrams showing configuration examples of the AND gate. (11... memory cell, (1a) and (1b)...
・Memory cell group, (2a) and (2b)... Number of bits, (3)... Word line, (4"l-°゛ row decoder,
(5) Row address signal lines, (6a) and (6b)
... Bit line load, (7) ... Power supply terminal, (8)
Load element, (9)... Inverter transistor, (L
d...Access transistor, αυ・°°last node, (12a) and (12b)-...And gate, (
18a) and 0sb)... Kate signal line, (14a
) ~ (14c) Mountain memory cell selection line, 05 degree @ position word line, (16a) ~ (16C)...AND gate, (
b) 1123) (30)...Inverter means, (2
])Q force 0υG discharge...MOS) transistor. Agent Makoto Kuzuno - Figure 6 Figure 71.1 Figure 8

Claims (7)

[Claims] (1) N memory cell groups arranged by dividing a memory cell array in the column direction, and a memory cell group selection line for selecting one of the N memory cell groups; a row decoder for decoding row address information of a memory cell group to be accessed; a pre-word line connected to the output terminal of the row decoder; a selection signal of the memory cell group selection line and an output of the pre-word line; It consists of an AND gate that performs logical product with a signal, and a word line connected to the output terminal of this AND gate, and the pre-word line and the first food line are arranged in parallel in the row direction, and the word line is The front word line is formed of a polysilicon layer separate from the word line or a metal wiring layer, and the AND gate is formed of a first transistor, a second transistor, and a first transistor. The first and second transistors are connected in series, and the first and second transistors are connected in series.
The drain (or source) of the transistor is connected to the first word line, the drain (or source) of the second transistor is connected to the word line, the source (or drain) of the first transistor is connected to the ground terminal, and the drain (or source) of the second transistor is connected to the ground terminal. The gate of the second transistor is connected to the memory cell group selection line, and the gate of the second transistor is connected to the output of the first inverter means for generating a negative logic of the memory cell group selection line. semiconductor memory device. (2) The semiconductor memory device according to claim 1, wherein the first inverter means is arranged outside the memory cell array. (3) N memory cell groups in which a memory cell array in which memory cells are arranged in a matrix is divided in the column direction; and a memory cell group selection line for selecting one of the N memory cell groups; a row decoder for decoding row address information of a memory cell group to be accessed; a pre-word line connected to the output terminal of the row decoder; a selection signal of the memory cell group selection line and an output of the pre-word line; It consists of an AND gate that performs logical AND with a signal, and a word line connected to the output terminal of this AND gate, and the pre-word line and the word line are arranged in parallel in the row direction, and the word line is The front word line is formed of a polysilicon layer or a metal wiring layer separate from the word line, and the AND gate is formed of a silicon layer, the front word line is insulated from the word line, and the front word line is insulated from the word line, and A semiconductor memory device characterized in that a word line is configured to be charged by a charge supply line other than the preceding word line. (4) The semiconductor memory device according to claim 8, wherein the resistance value of the material forming the charge supply line is set to be equal to or lower than the resistance value of the material forming the front word line. (5) N memory cell groups in which a memory cell array in which memory cells are arranged in a matrix is divided in the column direction; and a memory cell group selection line for selecting one of the N memory cell groups; a row decoder for decoding row address information of a memory cell group to be accessed; a pre-word line connected to the output terminal of the row decoder; a selection signal of the memory cell group selection line and an output of the pre-word line; An AND gate that performs logical product with a signal, and a word line connected to the output terminal of this AND gate. The front word line is formed of a polysilicon layer or a metal wiring layer separate from the word line, and the AND gate is formed of an eighth transistor, a fourth transistor, and a second inverter. The eighth and fourth transistors are connected in series, the drain (or source) of the eighth transistor is connected to the memory cell group selection line, and the drain (or source) of the fourth transistor is connected to the word line. line, the source (or drain) of which is connected to the ground terminal, the gate of an eighth transistor is connected to the pre-word line, and the gate of the fourth transistor is a gate of a fourth transistor that generates a negative logic of the pre-word line. 1. A semiconductor memory device configured to be connected to the output of a second inverter means. (6) A semiconductor memory according to claim 5, characterized in that the resistance value of the material constituting the memory cell group selection line is set to be equal to or lower than the resistance value of the material constituting the pre-word line. Device. (7) A semiconductor memory device as set forth in item 5 of the scope of Patent No. 8 Seigyu, characterized in that the memory cell group selection line is made of a metal wiring material.