JPH0467717B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device in which a cell array is divided into a plurality of blocks, and particularly to a word line selection circuit thereof.

[Conventional technology]

In large-capacity memories, it has been considered to divide the cell array into a plurality of blocks from the viewpoint of high-speed operation and low power consumption. FIG. 4 shows an example in which the cell array is divided into four in the word line direction. Since each cell array is operated independently, for example, in the case of DRAM (dynamic random access memory), the number of bit lines to be precharged and discharged during access is reduced to 1/N (N is the number of divisions), reducing power consumption. Further, by shortening the word line length, speed delays caused by the resistance of the word line itself can be improved, and furthermore, since the capacitance of the word line is reduced, high-speed operation is possible.

In this diagram, CB is the refresh address RA.
counter and buffer (address a ₀ ,
a ₁ , ... and its inverse ₀ , ₁ , ...), AB
is the normal access address after receiving the external address.
This is an address buffer that generates AA (also generates address bits and their inverted bits).
Refreshing is necessary in DRAM, but if the cell array is divided into multiple blocks and each block can operate independently, one cell array block can be accessed normally, while other blocks can be refreshed, which can be done in parallel with normal access. If the refresh is controlled so that collisions do not occur, normal accesses are less likely to be kept waiting because refresh is in progress, and the busy rate can be reduced.

[Problem that the invention seeks to solve]

However, in order to operate each cell array block independently, N word decoders are required for each cell array block in the above example, and the word decoders have address lines running through them and large output transistors. As the number of word decoders increases, the area occupied by the word decoders becomes considerably large due to the space required.

The present invention aims to reduce the number of word decoders required and to further improve the degree of integration of a large capacity block memory.

The present invention also attempts to improve processing efficiency by allowing a plurality of blocks to be accessed at the same time.

[Means for solving problems]

The present invention provides a semiconductor memory device in which a memory cell array is divided into a plurality of blocks in the word line direction, in which a plurality of selection gates are arranged in the word lines of each block, and a plurality of mutually independent word decoder output lines and block selection lines are arranged. controls the gate to make the word line selectable from a plurality of word decoders, and while the word line of one block is selected from one word decoder, the word line of the same row of the other block is selected. is selected from the other word decoder.

〔Example〕

To explain with the drawings, FIG. 1 shows an example in which the cell array is divided into four, and CA0 to CA3 are each of the blocks. WL0 to WL3 are word lines of each cell array block. In the figure, only one is shown (the other one is shown by a dotted line), but of course there are many in reality. These word lines WL0 to WL3 are one word line before cell array division, and therefore have the property of being selected by the same word address. In order to divide the cell array and select each cell array block independently, as shown in FIG. 4, each cell array block is provided with a word decoder, the same address signal is given to them, and a select signal ( This gives the column address (in this example, the upper 2 bits), but in Figure 1 it gives the cell array block group.
Only word decoders are placed on both sides of CA0 to CA3. WDR is a right word decoder and WDL is a left word decoder. In this figure, WDR and WDL indicate the part of the word decoder that selects one word line, and therefore there are as many WDR and WDL as there are word lines (indicated by dotted lines).
For convenience of explanation, these are assumed to represent the entire word decoder. Output lines WLR and WLL for selecting word lines extend from word decoders WDR and WDL, and each word line WL0 to WL3 has word line selection gates GR0 and GL0, GR1 and GL1,...
... will be established. Lines R0 to R running in a direction perpendicular to the word line, that is, in the direction of the bit line (not shown)
3, L0 to L3 are selection lines for blocks CA0 to CA3, the former for selection from the right side and the latter for selection from the left side. Therefore, the selection gates (AND gates) GR0 to GR3 are inputted with the potentials of output lines WLR and R0 to R3, and the selection gates (AND gates) GL0 to GL3 are connected to the output lines WLL and L0 to L.
One of the three potentials is input. Although not shown, each block CA0 to CA3 is provided with a column decoder for selecting the bit line of the block.

In this device, the word line is selected by the right word decoder WDR, and specifically, the output line WLR is set to H.
(high) level and selects one of the lines R0 to R3. For example, when R1 is set to H level, the output of AND gate GR1 becomes H level, and the word line
WL1 is selected. Other word lines WL0, WL
2. WL3 has R0, R2, and R3 not selected, that is, L
Since it is a (low) level, the AND gate GR0,
The outputs of GR2 and GR3 are at L level and are not selected. Each block CA0 to CA3 has a large number of bit lines running in a direction orthogonal to the word line, and if these bit line groups are divided into four so that they are selected by the upper two bits of the column address, line R0 The selection signal of ~R3 is the upper two bits.

The operation of this memory (DRAM) is well known; when a word line is selected, the corresponding memory cell group is connected to the bit line group and changes the bit line potential according to the stored data, which is then input by the sense amplifier group. The bit line enlarged and selected by the column decoder is connected to the data bus, and the potential of the bit line, that is, the data stored in the selected cell is taken out to the outside.
This is a read operation, but in the case of a write, the data flow is reversed. The word line is selected by the left word decoder WDL, that is, WLL is set to H.
When one of L0 to L3, for example L0, is selected, the output of AND gate GL0 becomes H, and word line WL0 is selected. The selection signals for L0-L3 are also the same as those for R0-R3.

In this way, in this device, a memory cell block can be arbitrarily selected using one word decoder WDR or WDL and block selection lines R0 to R3 or L0 to L3, and the number of word decoders can be significantly reduced compared to the case where each block is provided with a word decoder. .
Also, if it is provided on both sides, when one word decoder is selecting a memory cell in a certain block, the other word decoder can select a memory cell in the other block, and if this is used for refreshing, the busy rate will be reduced. can be reduced.
Right word decoder WDR and left word decoder
In addition to using the same read/write WDL, one may be dedicated for reading and the other for writing, or one may be used for normal access (read/write) and the other for refresh.
In other words, this two-word decoder system is extremely flexible and can be used in various ways.

If cell array blocks are selected independently by two word decoders, a collision may occur, that is, the same block may be selected simultaneously, and this must be avoided, so it is preferable to provide a priority control circuit. As a priority control method, it is conceivable to simply fix it so that the right access system has priority. One side of the word decoder is used for normal access, and the other is used for refreshing. Refreshing must be performed at a predetermined period to prevent the loss of the memory contents of the memory cells. If the period is set to the maximum allowable limit, collision avoidance normally occurs. This will probably be done by making the access standby, but if there is a margin in the period, the refresh can be made to wait. Since the refresh can be performed in a simple manner starting from the end, a simple method can be used in which the access address is generated using a circular shift register that stores only one H data and the rest L data. There is no need to use a complicated word decoder consisting of an address line, an address buffer for creating an inverted bit, a NOR gate, etc.

Two transistors are sufficient for the selection gates GR0, GL0, . . . . FIG. 2 shows the selection gate of cell array block CA1, where field effect transistors Q1 and Q2 constitute gate GR1, and field effect transistors Q3 and Q4 constitute gate GL1. Transistors Q2 and Q4 are for bootstrap. That is, the gates of transistors Q2 and Q4 are connected to potential Vcc. So the output line WLR
When R1 is raised to H (set to Vcc) prior to , the capacitance of the gate node of transistor Q1 is charged to Vcc, and when WLR is raised in this state, the gate of Q1 becomes higher than Vcc, and Q1 is completely turned on. Therefore, the potential Vcc of WLR can be directly applied to the word line WL1. The same applies to transistor Q3.

In the devices shown in Figures 1 and 2, each word line has two
Requires output lines WLR and WLL. DRAM
The word line serves as the gate of the transistor in a one-transistor, one-capacitor type memory cell, so it is generally made of polycrystalline silicon, and the output line WLR,
WLL is made of aluminum and has different layers,
Output lines WLR and WLL are on the same layer, so there is a risk that the wiring spacing will be quite close. FIG. 4 shows an improvement on this point, in which output lines WLR and WLL each make it possible to select any one of the two word lines WL1 and WL1'. In this way, since there are two output lines for two word lines, there is one output line per word line, and the number of output lines can be halved.

To explain the operation of this figure 3, now WLR and R
When 1 is set to H, the output of AND gate GR1 becomes H, and word line WL1 is selected. WLR and R
If 1' is set to H, the output of AND gate GR1' becomes H.
, and word line WL1' is selected. The operation of the left side selection circuit is also similar. selection lines R1 and R1',
The selection signal for L1 and L1' is one bit of the word line address signal, and the word line address signal excluding the least significant bit is added to the word decoder, and the least significant bit selects either R1 and R1' or L1 and L1'. When WL1' is selected, WL1' becomes the next word line WL after WL1.
It becomes 2.

In the embodiment, an example is given in which the cell array is divided into 4 parts, but of course this may be divided into more parts such as 8 parts.
In that case as well, it is sufficient to provide only two word decoders, one on the left and one on the right. Of course, the word decoder may be arranged only on the right or left side, that is, closer to one side, and the gates GR0, GL0, etc. may also be arranged closer to one end of the word line. In addition, in Fig. 3, two word lines WL1 and WL1' are selected by one output line, for example, WLR, but if the selection lines R1 and R1' are made four,
Word lines can be selected, generally n selection lines and n
You can select the word line of the book. Also
Although DRAM is taken as an example, it may also be SRAM (static RAM).

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to reduce the number of word decoders in a cell array divided memory, and moreover, it is possible to use a variety of memory usages, which is extremely effective.

[Brief explanation of drawings]

1 to 3 are explanatory views showing embodiments of the present invention, and FIG. 4 is an explanatory block diagram of a memory having a divided cell array. In the drawing, CA0 to CA3 are cell array blocks,
WL0 to WL3 are word lines, GR0...GL3 are selection gates, WDR, WDL are word decoders, R0...
L3 is a block selection line.

Claims (1)

[Scope of Claims] 1. A block formed by dividing a memory cell array into a plurality of parts in the word line direction, two selection gates provided in each of the blocks, and a gate corresponding to one of the selection gates for each block. a first word decoder connected via one block selection line, and a second word decoder connected via a second block selection line corresponding to the other selection gate for each block;
and a second word decoder that operates independently from the word decoder, and the selection gate is controlled by the output lines of the first and second word decoders and the first and second block selection lines. A semiconductor memory device characterized in that one word line can be selected from a plurality of word decoders. 2. The word decoder is arranged on one side and the other side of the cell array block group, and the output line extends across the cell array block in parallel with the word line. Semiconductor storage device. 3. A patent claim characterized in that a plurality of pairs of block selection lines are provided in each cell array block, and the selection gates are opened and closed by the selection lines so that one output line of a word decoder can select a plurality of word lines. 2. The semiconductor memory device according to item 2.