JPS5965468A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain the titled memory device of high speed and low power consumption by a method wherein a pre-word wire and a word wire are arranged in parallel with row direction and, at the same time, an AND gate is arranged in the center of each memory cell group. CONSTITUTION:When a memory cell is selected from a memory cell group 1a, the row address information of the memory cell group 1a to make access is decoded by a row decoder 4, and one of pre-word wires 15 is activated. Then, when a selective signal is applied to said memory cell group selection wire 14a, an AND gate 16a opens, and word wire 3a is activated. Accordingly, the column current flowing into the memory cell group 1a from the power source via a bit line runs into to the column located in the selected memory cell group 1a. Also when the AND gates 16a-16c, to be used for selection of memory cell groups, are arranged in the center of the memory cell groups 1a-1c, the resistance of the output terminal of the AND gates 16a-16c on a word wire 3a is reduced to half, thereby enabling to create an advantageous condition wherein the titled memory device can be operated at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device capable of improving RFD access time and reducing power consumption.

FIG. 1 is a block diagram showing a conventional semiconductor memory device. In the same figure, °C, (1) are memory cells arranged in a matrix, the detailed circuit of which is shown in Figure 2, (2a)
and (2b) are a pair of bit lines in a one-eye complementary relationship, (3) is a word line that activates memory cells (1) on the same row when selected, and (4) decodes row address information. (5) is a row address signal line, (6a) and (6b) are pin l-k loads connected to the bit lines (2a) and (2b), respectively, and (7) is a power supply terminal.

Note that in the memory cell (1) shown in FIG.
) and (8b) are load elements composed of MOS transistors, resistors, etc., (9a) and (9b) are inverter transistors, (10a) and (10b) are access transistors, (lla) and (llb) are memory cells ( 1) is the store node.

Next, regarding the operation of the semiconductor memory device having the above configuration, as an example, store nodes (lla) and (llb
) are respectively 6 “H′” level and “L′” level (
The case where this is written will be explained.

First, in the case of reading, the address information of the cell to be read is input to the address signal line (5).

When this word line (3) is activated, the access transistor (10b) storing "L level" is activated.
conducts. Therefore, a current flows from the power supply terminal (7) through the path of the bit line load (6b), bit line (2b), access transistor (10b), and inverter transistor (9b), allowing reading.

In a semiconductor memory device with this configuration, all memory cells on the same memory cell are activated, so current flows into all columns from the power supply to the memory cells.When configuring a static RAM with a large number of columns, The current consumption increases.In order to reduce the current consumption, a semiconductor memory device as shown in FIG. 8 has been proposed.In this case,
A row decoder (4) is arranged in the center of the memory cell plane,
The word lines are connected to the left word line (8a) and the right word line (8a).
8b), and by activating only the word line of the selected one of the left and right memory cell groups, a current path is generated in only half of all the columns. Note that (12a) and (12b) are AND gates that select the left word line (8a) or right word line (3b), respectively, and (18a) and (18b) are u5
This is the gate signal line to set the state.

Next, FIG. 4 is a layout diagram showing a conventional semiconductor memory device constructed based on the idea of FIG. 8.

In this case, the row decoders (4a) and (4b) are arranged in a plurality of columns, and the word lines (8a) to (8b) are divided by a multiple thereof, thereby reducing the number of DC current paths.

However, conventional semiconductor memory devices require a large number of row decoders. For this reason, there were drawbacks such as an increase in chip area and a loss in speed performance and yield.

Therefore, an object of the present invention is to provide a high-speed, low power consumption, large capacity semiconductor memory device.

In order to achieve such an object, the present invention includes N memory cell groups in which a memory cell array in which memory cells are arranged in a matrix is divided in the column direction, and one of the N memory cell groups. A memory cell group selection line to be selected;
A row decoder for decoding row address information of a memory cell group to be accessed, a pre-word line connected to the output terminal of this row decoder, a selection signal of the memory cell group selection line and an output signal of the pre-address word line. It consists of an AND gate that takes the AND of the AND gate, and a word line connected to the output terminal of this AND gate. The gate is arranged at the center of each of the memory cell groups,
Examples will be described in detail below.

FIG. 5 is a block diagram showing one embodiment of the semiconductor memory device according to the present invention.
) is placed. In the same figure, (1aa)
, (14b) and (14c) represent this memory cell group (
1a) Memory cell group selection line for selecting (IC), αQ
(16a), (LEB) and (16c) have input terminals connected to the previous word Q5 and the memory cell selection line (16a), (LEB) and (16c), respectively. 14a) to (14c), and output terminals are connected to word lines (8a) to (8C), respectively.

In addition, in order to reduce the memory cell area (the word lines (8a) to (8c) are MOS), a transistor (10a) is used.
) and (iob), while the previous L word line (LQ is formed from this word line (
These polysilicon layers 3a) to (3C) are formed of a different polysilicon layer or a gold wiring layer of aluminum, molybdenum, molybdenum silicide, or the like.

Next, the operation of the semiconductor memory device having the above structure will be explained. First, for example, when selecting a memory cell in the memory cell group (1a), the row address information of the memory cell group (1a) to be accessed is decoded by the row decoder (4), and one of the prefix word lines αG is Activate. Then, when a selection signal is applied to the C1 memory cell group selection line (14a), the AND gate (16a) is opened and the word line (8a) is activated. Therefore, the column current flowing from the power supply (not shown) through the bit line (not shown) to the memory cell group (1a) flows only in the column in the selected memory cell group (la).

Note that the above describes the memory cell (in the memory cell 1n(la))
1) Selection 1 has been explained, but other memory cell groups (
Of course, 1b) and (IC) can also be heated to °C in the same way. Furthermore, if the memory cell group is divided into three, then the number of cells (N, <-'
Of course, the same result can be obtained even if it is divided into 2).

In addition, if only the forward motion word line QQ is made of a low-resistance material, the resistance of the word line will be somewhat large. Cells can be accessed. matco, andk) (
16a) to (16c) have two input terminals and one output terminal, which simplifies the circuit configuration, so the increase in chip area can be ignored. Matoko, row decoder (4)
is placed in the center of the chip for good °C, and placed at the edge of the chip.
Of course, j7,1 and C are also good.

In the following embodiments, the row decoder is placed at the edge of the chip, but it goes without saying that it may be placed in the center of the chip.

As shown in FIG. 6, the memory cell group selection AND gates (t6a) to (16c) are connected to the memory cell group (1a).
) to (IC) (in the figure, the memory cell group (
1a) is exemplified) and the resistance from the output ends of the AND gates (16a) to (16c) of the word line (8a) is halved, which is advantageous for interconnection.

As described above in detail, according to the semiconductor memory device according to the present invention, row selection is performed hierarchically such that memory cell selection is divided into two stages, pre-word line and word line selection, and zero rows are performed. Since the number of columns with direct current paths in the columns can be reduced, it is possible to construct a high-speed, low power consumption, large-capacity semiconductor memory device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional semiconductor memory device, FIG. 2 is a detailed circuit diagram of the memory cell in FIG. 1, FIG. 8 is a block diagram showing another conventional semiconductor memory device, and FIG. 4 is a block diagram showing a conventional semiconductor memory device. Layout diagram showing another conventional semiconductor memory device, Fig. 6, @
FIG. 6 is a block diagram showing different embodiments of the semiconductor memory device according to the present invention. (1)...Memory cell, (la) and (lb)...
-Memory cell group, (2a) and (2b)...bit line, (3)...word line, (4)...row de''-da,
(5)...Row address signal line, (6a) and (6b
)... Bit nominal load, (7)... Power supply terminal, (8)
...Load j? E child, (9)... f inverter transistor, αQ... access transistor, Ql)...
・Store node, (12a) and (12b) ・
...And gate, (18a) and (18b)...
Gate signal lines, (14a-(14c)...memory cell selection lines, (junior...front sword lines, (16a)-(1)
6c)...and gate. Note that the same reference numerals indicate the same or equivalent parts. Agent Makoto Kuzuno - Procedures Amendment Damage (voluntary) 21 Name of the invention Semiconductor memory device 3. If amended, representative piece 111 Jin 8 section 4 Column 6 for detailed description of the invention in the agent's specification Contents (1) For details, please correct as follows. 3F

Claims (1)

[Claims] A memory cell array in which memory cells are arranged in a matrix is divided in the column direction into [L, N memory cells W1].
, a memory cell group selection line for selecting one of the N memory cells 8T, a row decoder for decoding the row address information of the memory cell group to be accessed, and a line before being connected to the output terminal of this row decoder. word line and the memory cell 8
\, consists of an AND gate that takes the logical product of the selection signal of the selection line and the output signal of the prefix word line, and a word line connected to the output terminal of this AND gate, and the prefix word line and the word line are arranged in parallel in the row direction, and the nest is arranged at the center of each of the memory cell groups.