JPS6146059A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To evaluate a signal easily by a simple test by transmitting the signal over each circuit block through a metallic wiring layer. CONSTITUTION:Gates for four MOSFETs Qm for memory arranged in the same line are each connected in common by a conductive polysilicon layer PSi. A second layer aluminum layer Al 2 is disposed in parallel with the conductive polysilicon layer PSi, and connected mutually to the conductive polysilicon layer PSi at one position. In such constitution, a select signal is not transmitted over the four MOSFETs Qm for memory on the left upper side and informations written in the four MOSFETs for memory are not outputted when the position of an X on word line W0 is disconnected. Accordingly, the disconnection of the word line (the aluminum layer Al 2) can be detected only by conducting a DC- like performance test.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a semiconductor integrated circuit device, and relates to a semiconductor memory device such as a random access memory (hereinafter referred to as RAM) or a read-only memory (hereinafter referred to as ROM). The present invention relates to techniques effective for semiconductor integrated circuit devices.

[Background technology]

In semiconductor storage devices such as RAM or ROM,
In order to achieve high integration, the word line is formed of a conductive polysilicon layer integrally formed with the gate electrode of the lattice forming the memory cell. Since the conductive polysilicon layer has a relatively high sheet resistance value of 30 to 40 Ω/gate, the signal propagation delay becomes relatively large.

In order to reduce signal propagation delay, in RAM, a metal wiring layer with a low resistance value (for example, several mΩ/hole) is formed in parallel with this wiring means, and both are connected at predetermined intervals. It is proposed to connect (1983v
IEEE International Soli
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nfrence Digestof Technic
al Paper, P226 and P227).

However, the inventor of the present application has revealed that if this is done, the following problem occurs. In other words, if a disconnection occurs in the metal wiring layer due to a defect in the manufacturing process, the circuit that supplies the signal to the word line will
The resistance value of the wiring layer formed on the far end side from the disconnected portion becomes extremely large. However, electrically, due to the conductive polysilicon layer having a relatively large resistance value,
The circuit and memory cell are coupled. In other words, even if a disconnection occurs in the metal wiring layer, the memory cell is selected.

Therefore, a DC operation test in which an address signal is supplied to a semiconductor memory device and the output signal thereof is simply checked cannot detect a disconnection in the metal wiring layer in the semiconductor memory device.

If a disconnection occurs in the metal wiring layer 1, a selection signal will be transmitted to the memory cell formed on the far end side from the disconnection via a conductive polysilicon layer with a relatively high resistance value. Therefore, the time required to select it is longer than that for other memory cells.

Even if a semiconductor memory device (hereinafter referred to as a memory) includes memory cells whose selection operations require different times, it cannot be detected by the DC operation test described above. As a result, a problem arises in that unreliable memories are shipped.

In order to sort out memory that can be considered defective,
After supplying the address signal to the memory, it is necessary to perform a current-variant operation test such as checking the output signal after a predetermined period of time, making the selection extremely troublesome. In other words, it is necessary to pay close attention to the timing of applying a signal to the memory to be tested and the timing of checking the output signal from the memory, which makes testing cumbersome.

In particular, in the case of a memory built into a large-scale integrated circuit device, such as a one-chip microcomputer, it is generally not possible to directly supply an address signal from the outside and take out the output signal directly to the outside. Therefore, when performing a regular operation test, it is necessary to check the delay time of the logic circuit interposed between the terminals of the one-chip microcomputer and the address input terminal of the built-in memory, and the data input/output terminal of the built-in memory. In consideration of the delay time of the logic circuit interposed between the terminals of the 1-chip microcomputer and the terminals of the 1-chip microcomputer, the above-mentioned operational tests must be performed. That is, considering at least the delay time of the above-mentioned 2Ft class, after giving the address signal to the microcomputer, the time during which the output signal of the memory will be output from this microcomputer is determined. Operation trial sale is
This is done by applying an address signal to the microcomputer and checking the output signal of the microcomputer after the time determined above from when the address signal was applied. In this way, the above-mentioned time must be determined in advance, making the operation test even more troublesome. Also, accurate tests cannot be expected.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor integrated circuit device that can be easily evaluated by a simple test.

Another object of the present invention is to provide a semiconductor integrated circuit device in which the propagation delay time in a signal line can be shortened and the propagation delay time can be evaluated by a simple operation test.

Other objects of the invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A memory array is divided into multiple circuit blocks. The circuit block includes wiring formed of a conductive polysilicon layer and circuit elements operated by signals transmitted via the wiring. Each circuit block is supplied with signals via an aluminum layer. Signals supplied to the circuit block are transmitted to circuit elements via internal wiring. If a disconnection occurs in the aluminum layer, the circuit block formed on the far end side from the disconnection point will not operate normally. Thereby, disconnection of the aluminum layer can be easily detected. Furthermore, since signals are supplied to each circuit block through the aluminum layer, the operating speed of the memory array can be improved.

[Embodiment 1] FIG. 1 shows a circuit diagram of an embodiment of a horizontal ROM to which the present invention is applied. Although not particularly limited, each circuit element in the figure is formed on a semiconductor substrate such as single crystal silicon by a known CMOS (complementary MO8) integrated circuit manufacturing technique.

An address decoder X-DCR receiving a plurality of first complementary address signals axi consisting of a plurality of internal address signals and a plurality of internal address signals whose phase is substantially inverted with respect to these internal address signals forms a selection signal, Memory array M-
Among the plurality of word lines formed in ARY, the word line W according to the complementary address signal is selected, and the formed selection signal is sent to it. The address decoder Y-DCR receives a plurality of second complementary address signals ayi,
A selection signal is formed and outputted to the column switch circuit so as to select the data line according to the complementary address signal from among the plurality of data lines formed in the memory array M-ARY.

The memory array M-ARY has a plurality of word lines WO~
Wm and data lines DO to Dn, and insulated gate field-effect transistors for storage (hereinafter referred to as
Qm (referred to as MOSFET) and each of the above data lines DO~
It is constituted by column switches MO8FETQI to Q3 respectively provided between Dn and common data line CD.

Note that, in order to simplify the drawing, the word lines wQ, representative word lines wQ,
Wl, Wm and data lines DO9D 1 s D n are shown.

Also, as a memory MO5FET, only one whose threshold voltage is turned on at the word line selection level is
The storage MO8FET which is shown in the figure and is in an off state or whose gate or drain is not connected is omitted. In the memory array M-ARY, the gates of the storage MOSFETs Qm arranged in the same column are connected to the corresponding word lines WO to Wm, respectively, and the gates of the storage MOSFETQm arranged in the same row are connected to the respective word lines WO to Wm. are connected to corresponding data lines DO to Dn, respectively. Although not particularly limited, these storage MO3FE
Each of TQm and column switches MO8FETQI to Q3 is composed of an n-channel MO3FET, and is formed in the same well region.

The common data line CD is connected to the input terminal of the sense amplifier SA. Sense amplifier SA connects common data line CD
The information transmitted to the memory MO8FET (memory cell) is amplified. As a result, the sense amplifier SA outputs a high level or low level read signal according to the information of the memory cell.

In this embodiment, in order to speed up the read operation, although not particularly limited, in addition to the precharge MO8FETQ4 provided in the common data fiCD, each of the data lines DO-Dn is also provided with a precharge MO.
Eight FETs Q5 to Q7 are provided. These precharge MO8FETs Q4 to Q7 are configured with p-channel MO8FETs, although they are not particularly limited. A precharge signal φp is commonly applied to the gates of these precharge MO3FETs.

Note that the precharge signal φp is generated by a timing signal generation circuit (not shown) formed on the same semiconductor substrate as the horizontal ROM.

FIG. 2 shows a circuit diagram of a specific embodiment of the memory array M-ARY. In this example,
In order to shorten the propagation delay time between the word line and the ground line of the circuit, and to easily detect a disconnection defect, the memory array M-ARY has the following configuration.

That is, the word line WO shown as a representative in the same figure and located at ℃
2. Like Wl, the gates of four memory MO8FETQm arranged in the same row, although not particularly limited, are formed in a conductive polysilicon layer PS integrally formed with the gate electrode.
They are commonly connected by i. Further, for each row, although not particularly limited, a second aluminum layer AJ2 formed on the semiconductor substrate via an insulating film is arranged substantially parallel to the conductive polysilicon layer PSi. . and.

The conductive polysilicon layer PSi and the second layer aluminum/WAA2 are connected to each other at one place (one point).

Further, the source electrodes of the four memory MO3FETQm are formed by a common diffusion layer N+, and are therefore commonly connected to each other. This common diffusion layer is formed on the semiconductor substrate through an insulating layer, and is a first layer of aluminum running in the same direction as the data line, in other words, substantially parallel to the data line. Even if it is connected at one point (single point) to the grounding line GND of the circuit constituted by the first layer aluminum scrap container 11 formed in the first layer.

In addition, each of the drain regions of the memory MO3FETQm arranged in the same column is connected to a data line formed by the first aluminum layer AAI formed on the semiconductor substrate via an interlayer, although not particularly limited. They are connected to Do to D7, respectively.

The conductive polysilicon layer PSi is formed on a semiconductor substrate with an insulating layer interposed therebetween. Further, the conductive polysilicon layer PSi and the first aluminum layer All
between the first aluminum layer All and the second aluminum layer k12, and between the conductive polysilicon layer PSi and the second aluminum layer A.
An insulating film is formed between each of them and 12. Therefore, as mentioned above, the second aluminum layer A1
When bonding different wiring layers, such as when bonding 2 and a conductive polysilicon layer PSi,
Contact holes are formed in the insulating film formed between the wirings, and different wirings are connected to each other through these holes. As mentioned above, when connecting different wirings at one place (for example, using a conductive polysilicon layer PSi
and the second aluminum layer AJ2 and the semiconductor region formed on the semiconductor substrate and the first aluminum layer AAI), the insulating film formed therebetween is For example, one contact hole is drilled, and different wirings are connected to each other through this contact hole.

The general operation of this embodiment circuit is as follows.

Prior to reading out the information stored in the memory cell, the precharge pulse φp is set to a low level.

As a result, the precharge MO8FETs Q4 to Q7 are turned on, and the common data i! icD and each data line D
O to Dn are precharged to the power supply voltage VDD level. Next, the precharge pulse φp is set to high level, and after the precharge MO8FETs Q4 to Q7 are turned off, the address decoders X-DCR, Y-DC
Memory cell selection is performed by R. The selected memory cell is a storage MQSF with a threshold voltage higher than the selected level of the word line according to the write data.
ETI (not shown) or MO8FETQm having a low threshold voltage with respect to the selected level. A selection level is supplied to the selected memory cell from the address decoder fX-DCR via the word line. As a result, the memory MO8F that constitutes the memory cell
ET is turned off or on according to the data written to it. As a result, the potential of the data line is brought to a low level or low level in accordance with the written data of the selected memory cell. In this way, the memory cell information transmitted to the data line is transferred to the common data line C via the column switch MO8FET turned on by the address decoder Y-DCR.
D, is amplified by the sense amplifier SA, and is output as a read signal.

If a disconnection occurs at the X mark of the word line WO in Figure 2, then the X address decoder X-DC
With respect to H, the selection signal from the X address decoder X-DCR is not supplied to the memory cells formed on the far end side from this disconnection point (X mark). That is, in FIG. 2, the selection signal is no longer supplied to the four storage MO8FETQm on the upper left side. Therefore, even if complementary address signals axi and ayi for selecting these four storage MOS F E'r are supplied to the X decoder X-DCR and the Y decoder Y-DCR, the sense amplifier SA
It simply outputs a constant signal.

That is, the information written to the four storage MO3FETs is not output.

As a result, it is possible to detect fresh green on the word line (aluminum NB Al 2 ) simply by performing the DC operation test as described above, and to detect RO that can be considered defective.
M can be prevented from being shipped.

Furthermore, since the word onion is formed of the aluminum layer A-2, the delay time until the selection signal is transmitted to the memory cell is short (this makes it possible to achieve high-speed operation of the ROM).

[Embodiment 2] FIG. 3 shows a block diagram of a large-scale integrated circuit device to which the present invention is applied. In the figure, each block surrounded by a broken line is formed on one semiconductor substrate using CMO3 integrated circuit technology.

In FIG. 3, LGC is a logic circuit that uses ROM RO (and) RAMRA in the process of performing a predetermined operation. As will be explained in detail later with reference to FIGS. 4 to 8, the ROMRO receives complementary address signals axi and ayi output from the logic circuit LGC and performs instructions using these complementary address signals axi and ayi. The information of the memory cells is sent to the logic circuit, LG
Output to C. The above RAMRA will be explained later in Fig. 9 and 1.
As will be explained in detail with reference to FIG. 0, in response to the complementary address signal aXj+aYJ output from the logic circuit LGC and the write enable signal WE, the complementary address signal axj.

The information stored in the memory cell designated by ayj is output to the logic circuit LGC, or the information from the logic circuit LGC is stored in the memory cell designated by the complementary address signals 3xj and aYj. It is RAM.

In FIG. 3, II is an external terminal for supplying a signal from the outside to the logic circuit LGC, and 0 is an external terminal for supplying a signal output from the logic circuit LGC to the outside. be. Further, φp is a precharge signal similar to that described in FIG. 1 above.

ROMRO and RA built into this large-scale integrated circuit device
In the test for evaluating MRA, ROMR
The signal corresponding to the complementary address signal to be supplied to O or RAMRA is supplied from the external terminal II, although not particularly limited, and the signal corresponding to the output signal of ROMRO or RAMRA is supplied to the external terminal II, although not particularly limited. Output from IO. In addition, the built-in RAM
When writing information into a memory cell in a test for RA, a signal corresponding to the information to be written is supplied from the external terminal II, although not particularly limited thereto.

FIG. 4 shows a circuit diagram of the ROMRO shown in FIG.

In order to simplify the drawing, FIG.
A portion of is shown. Further, the main circuits shown in FIG. 4 are drawn in accordance with the layout actually formed on the semiconductor substrate.

The detailed circuit arrangement will be explained later using FIG. 5.

In FIG. 4, X-DCR is an X address decoder, and Y-DCR is an X address decoder. The X-address decoder X-DCR receives the plurality of complementary address signals axi supplied from the logic circuit LGC, and selects the word line designated by the complementary address signal axi from among the plurality of word lines forming the memory array. A selection signal is supplied only to the selected word line.

The address decoder Y-DCR is the logic circuit LGC above.
A selection signal is formed by receiving a plurality of complementary address signals ayi supplied from the column switch, and is supplied to the MOSFET forming the column switch. As a result, the MOS FET Q that constitutes the column switch
s couples the data line designated by the complementary address signal ayi among the plurality of data lines forming the memory array to the common data line CD.

The memory array has a plurality of word lines AA2 (WO) to AA.
2 (Wn) and multiple data iAJ 1 (DO)
~AA! 1 (Dn), a memory MOSFET Qm selectively provided at the intersection of the word line and the data line according to write information, and a memory MO3FETQ.
m and a ground line GND for supplying the ground potential of the circuit. In order to simplify the drawing, FIG. 4 shows word line input l2(wo)-Al2(W5),
Data lines AJ1 (D9) to AJI (D24) and Al
1 (Dn-n) to AJ 1 (Dn) are shown.

Each of the above-mentioned data lines is coupled to the -7 input terminal of MO3FETQs whose switch is controlled by the selection signal output from the Y address decoder Y-DCR. Although not particularly limited, in this example, 2
One data line is made into one set, and one data line is selectively coupled to the common data line CD by the output signal of the Y address decoder Y-DCH. For example, if we look at a set of data lines made up of data lines D9 and DIO, one of the data lines is selected by the output signal of the Y address decoder Y-DCH, and the selected data line corresponds to It is combined with the common data 1llcD4. As a result, the information transmitted from the storage MO8FET to the selected data line is transmitted to the common data line CD4, and is supplied to the logic circuit LGC as output data DO4.

Although not shown in FIG. 4, each data line is provided with a precharge MO3FET that precharges the parasitic capacitance of the data line. Although not particularly limited, this precharge MO3FET is
MO3FET for precharging (Q4~Q7
), p-channel enhancement MO3F
It is composed of ETIC, and its gate electrode has
A precharge signal φp formed by the logic circuit LGCk is supplied.

In addition, FIG. 4 shows a storage MO3FET that is turned on by a selection signal from the X address decoder X-DCR.
Only Qm is shown. This memory MosFETQm
is composed of an n-channel r7 channel type MO5FET. That is, from the X address decoder X-DCR,
Only the storage MO3FET, which is turned on only when a selection signal having a selection potential (for example, 5V) is supplied, is connected to the fourth
The storage MO5FET shown in the figure and which does not substantially function as a MOSFET has been omitted.

In the above memory array, the gates of the storage MO8FETQm arranged in the same column are electrically coupled to the same word line, and the storage MO8FETQm arranged in the same row are electrically coupled to the same word line.
The drain of each FETQm is coupled to the same data line.

In this embodiment, the memory array is configured as follows in order to shorten the signal propagation delay time in the word line and to easily detect word line disconnection. .

That is, the storage MO8FETQm arranged in the same column
Although not particularly limited, the circuit blocks are substantially divided into eight units to form a circuit block. In other words, each column is provided with a plurality of circuit blocks including substantially eight MO3FETs for storage. However, the eight storage MO8FETs that make up the circuit block do not actually operate as MOSFETs according to the written data.
- It is necessary to note that it also includes MO8FET for storage. The memory MO8FET constituting the circuit block has a gate electrode formed integrally with a conductive polysilicon layer. In other words, when a circuit block includes a plurality of storage MOSFETs that operate as MOSFETs, their respective gate electrodes are coupled by a conductive polysilicon layer. What must be noted here is that the conductive polysilicon layer PS
The gate electrodes connected by i are memory MQ SFETf included in the same circuit block.
The gate electrodes of the memory MO8FETs included in different circuit blocks are not connected by the same conductive polysilicon layer PSi.Each circuit block arranged in the same column are bonded to each other by the aluminum layer forming the word line.That is, the conductive polysilicon 1Psi in different circuit blocks are bonded to each other by the aluminum layer forming the word line. There is.

Although not particularly limited, in this embodiment, as will be explained later with reference to FIGS. 5 to 8, the aluminum layer forming the word line is the second aluminum layer A1.
It is composed of 2.

Further, although not particularly limited, the bonding between the second aluminum layer A12 and the conductive polysilicon layer PSi is performed as follows. The second aluminum layer A12 is bonded to the first aluminum layer A1, and the first aluminum layer A1 is bonded to the conductive polysilicon layer PSi. combined. By doing so, the area required for bonding the aluminum layer AJ2 and the conductive polysilicon layer PSi can be reduced in terms of specific yield.

Among the eight storage MO8FETs forming the circuit block, the source regions of each of the four storage MO8FETs are configured by a common N+ type semiconductor region. This common N-type semiconductor region is coupled to a ground line GND formed substantially parallel to the data line. Although not particularly limited, in this embodiment, the ground line GND is constituted by an N+ type semiconductor region, and this N medium semiconductor region GND and the common N type semiconductor region are integrally formed.

Also, the memory MO8FET wired in the same row
each of the drain regions forming a data line.
It is bonded to the second aluminum layer AII.

The operation of the ROM in this embodiment is almost the same as that in the embodiments shown in FIGS. 1 and 2 described above, and therefore the explanation thereof will be omitted.

If a disconnection occurs at the X mark of the word line A12 (WO) in FIG. 4, the X address decoder
With respect to H, the selection signal is no longer supplied to the circuit block formed on the far end side from the disconnection location. That is, in FIG. 4, the selection signal is no longer supplied to the circuit block on the lower left side. As a result, complementary address signals axi and ayi for selecting memory cells included in this circuit block are sent to the X address decoder X-DCR-■■
---When supplied to the Y-address decoder Y-DCH,
The signals supplied from ROMRO to logic circuit I and GC are as follows:
This is not information written in advance into the selected memory cell, but a constant signal.

This makes it possible to easily test the memory built into a large-scale integrated circuit device.

Further, since selection signals are supplied to each circuit block by the aluminum layer, the operating speed of the ROMRO can be increased.

FIG. 5 shows a plan view of essential parts of the ROM shown in FIG. 4 above.

That is, in FIG. 4, data lines A11 (D9) to
A11 (D24) and word + W5! Al2(WO)~
AJ 2 (W5') and data #AJ1 (D9) ~
AJI (D24) and word line A12 (WO
) to A12 (W5), and a plurality of ground lines GND, a plan view of a memory array section is shown in FIG.

In FIG. 5, the area surrounded by the broken line is the semiconductor substrate (
For example, N-type silicon substrate)
It shows an N+ type semiconductor region formed on the main surface of the " type well region Well, and the region surrounded by a dotted line is a P-
The P-type well region Wel is
1 shows the conductive polysilicon layer formed on the main surface of 1, the area surrounded by the two-dot dashed line shows the first aluminum layer AJI, and the area surrounded by the solid line, A second aluminum layer A12 is shown. Further, in the figure, D is an N+ type semiconductor region for forming the drain region of the MO8FET for storage. An isoelectric polysilicon layer PS integrally formed with each gate electrode of a plurality of memory MO5FETs constituting a circuit block.
i is electrically coupled to the second aluminum layer H2(W) via the first aluminum layer Al11(C). This allows the X address decoder
The output signal from the CR is transmitted to the gate electrode of the memory MO3FET forming the circuit block.

Although not shown in FIG. 5, a 7I8 green film is formed between the first aluminum layer Ill and the second aluminum sea urchin layer AA2, and the first aluminum layer A An insulating film is also formed between No. 1 and the conductive polysilicon layer PSi.

In each of FIG. 4, FIG. 5, FIG. 6, FIG. 7, and FIG. 8, the same symbols are attached to the same parts.

FIG. 6 shows a cross-sectional view taken along the line AA in FIG. 5.

In FIG. 6, reference numeral 1 denotes a thin insulating film (for example, a TF-/licon silicide film), which also constitutes the gate oxide film of the memory MO8FET. An enhancement type memory MO8FET is formed in the region where the gate oxide film 1 is formed. That is, the conductive polysilicon layer formed on this gate oxide film 1 acts as a gate electrode of an enhancement type memory MO8FET. On the other hand, 2 is an insulating film (for example, a silicon oxide film) that is thicker than the gate oxide film 1, and constitutes a field oxide film. 6 is a P′″ type semiconductor region;
Configure channel stopper.

GND is an N+ type semiconductor region for forming the above-mentioned ground line. Reference numeral 3 denotes a glabellar insulating film for separating the conductive polysilicon layer PSi and the first aluminum layer AII, and is made of, for example, a PSG film. C2 is a contact hole provided in the interlayer insulating film 3. The first aluminum layer AAI (C) and the conductive polysilicon layer PSi are connected through this contact hole C2. 4 and 5 are formed on the eyebrow insulating film (for example, PSG film) interposed between the first aluminum layer A71 and the second aluminum layer A12 and the second aluminum layer AA2. This is an insulating film made of a final insulating film B (for example, Si, NL film). Further, in FIG. 6, Sub is an N-type semiconductor substrate, and Wel 1 is a P-type well region formed in the N-type semiconductor substrate.

FIG. 7 shows a sectional view taken along the line B-Bm in FIG. 5.

In FIG. 7, A No. 1 (D23) is the data line AA!
1 (D23) 1st N! This is the J-th aluminum sea urchin layer. This first W1 aluminum layer A11 (D2
3) is coupled to the N'' type semiconductor substrate via the contact hole C1 provided in the eyebrow insulation [31C].
This is a semiconductor region that is formed on the entire surface of the memory MO8FET and is to become the drain region of the memory MO8FET. 4 is an interlayer insulating film formed on the main surface of the first aluminum layer A11 (D23). This prevents the first aluminum layer Ano1 and the second aluminum layer AJ2 from being electrically coupled undesirably. A12 (
Wl) to Al12 (W4') are word lines A12
(Wl) to A12 (W4) is the second aluminum layer. In FIG. 7, 5 is a final compression film.

7 is N+ which should be the source area of MO8FET for storage
type semiconductor region. This N″″ type semiconductor region 7 is %
Although not limited to the above-mentioned N+ type semiconductor region GNI)
It is formed integrally with ℃.

In FIG. 7, it should be noted that the thickness of the insulating film formed under the conductive polysilicon PSi varies depending on the conductive polysilicon core PSi. This is a storage MO8F that stores memory cells in 11ffi according to the information to be stored in the memory cells.
Will ET be made into an enforcement type MO3FET?
Or, this is because the MOSFET is prevented from actually functioning as a MOSFET.

4) of the insulating film under the conductive polysilicon layer PSi formed on the leftmost side in FIG. Since the area is thin, an enforcement type memory MO8FET is formed in this area. On the other hand, since the thickness of the insulating film under each of the remaining conductive polysilicon layers PSi is increased, the memory MO8FETs formed in these regions are substantially MOSFETs.
ET, C doesn't work.

FIG. 8 shows a sectional view taken along the line CC in FIG. 5.

In FIG. 8, c2 is a contact hole made in the interlayer insulating film 3. In FIG. The first aluminum layer AII (C) and the above-mentioned conductive polysilicon layer PSi are coupled through this contact hole C2. c3ba,
This is a contact hole made in the interlayer insulating film 4. The second aluminum layers AJ 2 (W2) and AJ 2 (Vl/3
) and the first aluminum layer A11 (C) are combined.

As a result, the second aluminum layer A l 2 (Wn) forming the word line AJ 2 (W3') and the conductive polysilicon layer PSi formed integrally with the gate electrode of the memory MO8FET are separated. electrically coupled.

In this way, once the first aluminum layer, l1l
(C) By combining the second aluminum layer AA2 and the conductive polysilicon PSi, the second aluminum layer A12 and the conductive polysilicon layer can be combined in a relatively small area. It can be combined with PSi. This is the second aluminum layer AJ2
If an attempt is made to directly bond the aluminum layer A12 and the conductive polysilicon layer PSi, the interlayer insulating film provided between them will become relatively thick. The contact hole becomes large. As a result, the area occupied for bonding becomes larger than in the case of bonding as in this embodiment.

As in this embodiment, the second aluminum layer AJ2
By combining the conductive polysilicon layer PSi with the conductive polysilicon layer PSi, the area occupied for the combination is reduced,
High integration can be achieved.

However, the invention is not limited to such a coupling method. As described above, the aluminum layer A12 and the conductive polysilicon layer may be directly bonded.

Next, a method for manufacturing this semiconductor integrated circuit device will be explained (
(See Figures 5 to 8).

In the N″″ type single crystal silicon substrate sub, a P− type well region is formed in a region where an N channel type MO8FET is to be formed. Next, the P-type well region we
In the N-type silicon substrate sub, silicon is sequentially applied to a region where an N-channel type MO3FET is to be formed and a region where a P-channel type MO3FET (for example, the precharge MO3FET described above) is to be formed. An oxide film and a 5isN4 film are formed. This 313 N
A channel stopper is formed by selectively diffusing boron and phosphorus into the region where no film is formed. 6th
8 to 8, only the P+ type channel stopper 6 formed in the P- type well region is shown.

Next, the field oxide film 2 is formed by selectively oxidizing the substrate surface using the S i , , N films as a mask.

In this example, the SiQ film and the Si, N film are not formed in the region where the gate electrode E of the memory MO8FET is to be formed.As a result, As shown in FIGS. 6 and 7, a P+ type channel stopper 6 and a field oxide film 2 are also formed in the region where the gate electrode of the storage MO8FET, which does not substantially function as an M'08FET, is to be formed. On the other hand, a memory MO8FE that acts as an enhancement MO8FET is formed.
In the region where T is to be formed, the above-mentioned S IQ z film and Si, N, and films are formed. As a result, this area has
Only the channel stopper and field oxide film 2 are formed. In other words, the above Sin, film and Si3
N. Whether or not to form a film is determined according to the information to be written in the MO8FET PC for storage.

Here, the storage MO8FET that works as the enhancement ff1M08FET is the X address decoder
This is a MOSFET that is turned on or off by a signal supplied from CR. On the other hand, actually M
A memory MO3FET that does not work as an OSFET is
This is a MOSFET that is always in an off state without being affected by the signal supplied from the address decoder X-DCR.

Let us return to the explanation of the manufacturing method.

031. After removing the S jot m and the S is N4 film, remove the MO-8FET (e.g. enhancement type M
A thin gate oxide film (S
i Ot R')1 is formed.

(C) A polysilicon layer is formed on the entire surface of the field oxide film 2 and the gate oxide film 1 by CVD (vapor phase chemical reaction method). Next, in order to lower the resistance of the polysilicon layer, in other words, to form a conductive polysilicon layer, an N-type impurity such as phosphorus is diffused.

In this case, a high concentration of N-type impurity is diffused. Thereafter, the polysilicon layer (conductive polysilicon layer) whose resistance has been reduced is selectively etched using a photoetching technique. That is, the unnecessary polysilicon layer is removed, leaving a portion corresponding to the gate electrode of the MOSFET and a portion corresponding to the above-mentioned conductive polysilicon layer PSi. Next, the exposed gate oxide film 1 is removed by etching.

(2) A photoresist mask is formed in the power region where a P-channel type MO3FET (for example, the above-mentioned precharge M, OSFET) is formed, and ions of an N-type impurity such as phosphorus are implanted. As a result, phosphorus ions are implanted into the main surface of the P-type well region we11 in self-alignment with the gate electrode (including the portion of the conductive polysilicon layer PSi that functions as the gate electrode).

As a result, an N+ type semiconductor region that will become the source region 7 of the N-channel MO8FET and an N+ type semiconductor region that will become the drain region thereof are formed. Furthermore, at this time, no photoresist mask is formed on the region where the semiconductor region corresponding to ground 1GND is to be formed. As a result, as shown in FIG. 6, an N+ type half body region GND is formed in the P~ type bottom region well.

Note that the conductive polysilicon layer PSi is a memory MO
3FET gate electrode, word line and the above memory M, 0
It constitutes a wiring layer that connects to the gate electrode of the 8FET.

CE), the photoresist mask formed in step) above is removed. Next, a photoresist mask is formed in the region where the N-channel type MO8FET is to be formed and the region where the conductive polysilicon layer PSi is to be formed, and ion implantation of P-type impurities such as boron is performed. As a result, P-channel type MO8
Boron ions are implanted into the substrate sub by self-forming with the gate electrode of the FET. As a result, a P+ type semiconductor region to become a source region of the P channel type MO3FET and a P+ type semiconductor region to become its drain region are formed.

The deposit of boron implanted in this step is kept relatively low. As a result, the gate electrode of the P-channel type MO8FET is formed of an N-type polysilicon layer similarly to the gate electrode of the N-channel type MO8FET.

Then, the photoresist mask formed in the above step (F2) is removed, and then a PSG film 3 is formed on the entire surface by CVD method.

q, PS on the PSG film 3 and conductive polysilicon layer Psi on each drain region of the memory MO8FET
Contact holes C1°C2 are formed in the G film 3.

Next, aluminum NIAJ1 is formed on the entire surface by vapor deposition or the like, and etched into a desired shape to form the first aluminum layers A11(C), A11(Do) to AJ1.
(Dn) is formed. Data line M1 (DO) ~ AJI
(Dn) is coupled to the drain region of the storage MO5FET via a contact hole C1 (FIG. 7). Further, each of the interconnects AAI(C) is coupled to the conductive polysilicon layer PS1 via the contact hole C2 (FIG. 8).

Next, a PSG film 4 is again formed on the entire surface by the CVD method.

First layer aluminum layer AA! A contact hole C3 is formed in the PSG film 4 formed on 1(C).

Thereafter, aluminum ff1AA2 is again formed on the entire surface by vapor deposition, etched into a desired shape, and the second layer of aluminum MAA2 (WO,) to Ano2 (W
form n). Each of the formed second H-th aluminum layers AJ 2 (WO) to AA 2 (Wn) is coupled to the first aluminum layer AJ1 (C) through a contact hole C3.

(I) A final passivation film 5 is formed on the entire surface, and the semiconductor integrated circuit device is completed as shown in FIGS. 6 to 8.

FIG. 9 shows a circuit diagram of the RAMRA shown in FIG.

In order to simplify the drawing, FIG.
A portion of is shown. Although it will be explained in detail later using FIG. 10, the main circuits shown in FIG. 9 are drawn according to the layout actually formed on the semiconductor substrate.

In FIG. 9, X-DCR is an X address decoder, and Y-DCR is an X address decoder. The X address decoder X-DCR is the logic circuit LGC described above.
receives a plurality of complementary address signals axj supplied from
Of the plurality of word lines forming the memory array, the word line designated by this complementary address signal axj is selected, and a selection signal is supplied only to the selected word line. The Y address decoder Y-DCR receives the plurality of complementary address signals ayj supplied from the logic circuit LGC described above, forms a selection signal, and supplies this to the MOSFET forming the column switch. This results in
The MO5FETQs constituting the column switch couples the complementary data line pair designated by the complementary address signal ayj, among the plurality of complementary data line pairs forming the memory array, to the common data line pair CDO, CDO.

The memory array has multiple words MA12 (WO) to A
l) 2 (Wn) and a plurality of complementary data line pairs Ai (
DO), A11(DO) to A11(Dn)2M1(Dn
) and a memory cell provided at the intersection of a word line and a pair of data lines. In FIG. 9, word lines A12 (W5) to
), -12 (W7), and data line pair AJ1 (D5
), All (D5) to A11 (D6).

AJI (D6) and AJ 1 (Dn), A11 (Dn
) and word lines hi 2 (W5) to AJ 2 (W
7') and data line pair AII (D5),
A11 (D5) ~ A11 (D6 L A11 (D6
) and A l l (I) n ) * A l 1 (
A memory cell provided in the t-b sole co'ZA of Dn) is shown.

Each of the data line pairs described above is coupled to the -1 input/output terminal of MO8FETQs whose switch is controlled by the selection signal output from the Y address decoder Y-DCR. The other input/output terminals of these MO8FETQs are coupled to a common complementary data line pair CDO, CDO. Plural complementary data line pairs AA 1 (Do)
, All (Do) ~A A! 1(Dn) r A
Of l l (Dn), complementary address signal ayj
Each of a set of complementary data line pairs designated by
, coupled to CDO.

As a result, the information transmitted from the memory cell to the complementary data line pair is transmitted to the common complementary data line pair via MO3FETQ, s, and is supplied to the logic circuit LGC via the amplification circuit & output buffer. be done.

Although not shown in FIG. 9 to simplify the drawing, RAMRA receives information supplied from the logic circuit LGC and transfers it to the common complementary data line pair CDO, CD.
An input buffer is provided to communicate to O. In the write operation, the information supplied from the logic circuit LGC is
The common complementary data lines CDO and C are connected via the input buffer.
This will be communicated to the DO. Then, information is transmitted to the complementary data pair coupled to the common complementary data line pair CDO, CDO via the MO3FETQS, and written into the memory cell.

The amplification circuit & output buffer and the manual buffer are connected to a control signal φRW formed by the logic circuit LGC.
The operation is controlled by For example, when the control signal φRW is at a low level, the amplification circuit & output buffer operates and the information of the memory cell is output. At this time, the human cover sofa is placed in a non-operating state. On the contrary,
When the control signal φRW is at a high level, the above-mentioned buffer operates and information is written into the memory cell.

At this time, the amplifier circuit and output buffer 7 are rendered inactive.

Although not shown in FIG. 9, each data line is provided with a precharge MOSFET. These precharge MO8FETs are
It has the same configuration as the precharge MO3FET described in the figure, and a precharge signal φp is supplied to its gate electrode.

Each of the memory cells includes a flip-flop circuit (F, F,) having a pair of input/output terminals, a first output electrode coupled to the -1 input/output terminal of the flip-flop circuit, and a data line A11. (D) N-channel enhancement MO8FE with second output electrode coupled to
TQa, a first output electrode coupled to the other input/output terminal of the flip-flop circuit, and data 1liiAll.
(D) N-channel enhancement MO3FETQa with a second output electrode coupled to the second output electrode. The above-mentioned flip-flop circuit is constituted by P-channel MO8FETQ1.Q2 and N-channel MO8FETQ3.Q4, although it is not particularly limited. That is, it is a CM037 flip-flop circuit.

In the memory array described above, the gates of the MO25FETs Qa, Qa constituting each of the memory cells arranged in the same row are electrically coupled to the same word line. In addition, MO5FETQa, Q constituting each of the memory cells arranged in the same column
a17) The second person's output IEffl is coupled to the same agitator line.

The gate electrode of the MO8FETQa and the MO8FE
The gate electrode of TQa is conductive polysilicon Psi
are connected to each other by. However, it must be noted that this conductive polysilicon/1Psi is not coupled to the gate electrode of the MOSFET that constitutes the other memory cells. The above conductive polysilicon layer is
Coupled to the corresponding word line. Thereby, a signal from the X address decoder X-DCR is transmitted to the memory cell via the word line. When the signal transmitted to the memory cell is a selection signal (for example, the signal 5), MO3FE'l'Qa and Qa forming the memory cell are turned on. This makes it possible to read or write information from this memory cell.

The RAM (LA) of this embodiment is configured so that input/output is performed in units of multiple bits, as shown in FIG.
However, in FIG. 9 mentioned above, in order to simplify the explanation, only the circuit portion where input/output is performed in units of 1 bit has been explained. Actually, a plurality of sets of the circuits shown in FIG. 9 are provided. However, in this case, the X address decoder X-DCR, the f-coater Y7, and the f-coater Y-DCR are used in common. However, the application of the present invention is not limited to RAM (ROM) in which input/output is performed in units of multiple bits.

Although not particularly limited, in this embodiment, the word line is
It is formed by the second aluminum layer A12. Further, the bond between the second aluminum layer AJ2 forming the word line and the conductive polysilicon layer PSi is as follows.
As explained using FIGS. 5 to 8, this is done through the first aluminum layer AJI(C). Further, the data line is connected to the first aluminum layer All
It is formed by

Since the operation of the RAM shown in FIG. 9 is the same as that of a well-known static type RAM, a description of the operation will be omitted.

If a break occurs in the word line, as in the case of the ROM shown in Figure 4, the word line is Since the selection signal is no longer transmitted to the memory cell that is currently in use, the information stored in this memory cell is not read out. This allows the built-in R
It becomes possible to easily perform AM tests. Furthermore, since the word line is formed of the aluminum layer, the RAM can operate at high speed.

FIG. 10 shows a plan view of essential parts of the RAM shown in FIG. 9 above.

That is, in FIG. 9, complementary data line pair All (
D5), AJI (D5') to A11 (D6).

AJI (D6) and word lines A12 (W5) to AA
2 (W7) and data line pair All (D5)tA
AI (D5) ~ AA 1 (D6), AJ 1 (
D6) and word lines AA2 (W5) to A72 (
FIG. 10 shows a plan view of a memory array section consisting of memory cells provided at the intersections with each of W7).

In FIG. 10, parts similar to those in FIGS. 5 to 9 described above are given the same symbols.

That is, the area surrounded by the four-dot broken line is the N-type silicon substrate sub, and the area surrounded by the three-dot broken line is the N-type silicon substrate sub.
This is a P-ya well region well formed on the whole surface of the - type silicon substrate sub. The area surrounded by the dashed line is N-
P+ type semiconductor region formed on the main surface of type silicon substrate sub or N type formed in P'' type well region well
This is a + type semiconductor region.

The region surrounded by the dotted line is the conductive polysilicon layer Psi, PSii formed on the surface of the insulating film formed on the main surface of the substrate sub or the well region well. The area surrounded by the two-dot broken line is the conductive polysilicon layer Ps.
i, the first aluminum layer Al formed on the surface of the insulating film formed on PSii! I (C), AJI
(D5)t A/1 (D5 LA/1 (D6)
, AJI (D6). The area surrounded by the solid line is the second aluminum layer AA2 (W5) to AA2 (W7) formed on the surface of the insulating film formed on the first aluminum layer. It is.

In FIG. 10, C1 is C1 shown in FIG.
Similarly, in order to bond the P"" type or N" type semiconductor region and the first aluminum layer AII, a contact hole is provided in the insulating film 3 interposed between them. Similar to C2 shown in FIG. 8, C2 is an insulating layer interposed between the conductive polysilicon layers PSi, PSii and the first layer of aluminum 4A11 in order to bond them together. A contact hole y formed in the film 3, C3 is for bonding the first aluminum layer Ail and the second aluminum layer AA2, similar to C3 shown in FIG. First, there is a contact hole formed in the insulating film 4 interposed between these.

In this embodiment as well, similarly to the embodiment described in FIG.
The first aluminum layer A/1 (C) is used to bond the second aluminum layer A12 (Wn) forming the word line and the conductive polysilicon layer PSi. Ru.

The conductive polysilicon layer PSi allows the above-mentioned M
A wiring layer is formed to connect the gate electrodes of the OS FETQa and Qa, and the gate' electrodes of these and the word aI (second layer aluminum layer) Al 2 (Wn). Furthermore, the conductive polysilicon WliPSii allows the MO8FETQI to Q
4 gate electrodes and a wiring layer for forming a 7-trip flow knob circuit are formed.

In Fig. 10 ℃, P channel type MOS FETQ
Each source region of I and C2 is constituted by a P+ type semiconductor region VDD. These P+ type semiconductor regions are interconnected by, for example, a second layer of aluminum layer A12 (not shown), and each P channel type MO8FET is connected via this second layer of aluminum layer A12 (not shown).
Voltage VDD is supplied to the source region of. In addition, N-channel type MO8FETQ3. Each source region of C4 is constituted by an N+ type semiconductor region GND. These N+ type semiconductor regions GND are also interconnected by, for example, a second aluminum layer A12, and are connected to the source region of each N channel/l/type MO8FET via this second aluminum layer A12. The ground potential of the circuit is supplied.

A final passivation film 5 (not shown) is formed on the second aluminum layer AJ2, similar to the embodiments described in FIGS. 5 to 8.

The method for manufacturing the RAM of this embodiment is shown in FIGS. 5 to 8 above.
Since the manufacturing method is the same as that described in the figures, the explanation thereof will be omitted.

In order to facilitate understanding of FIG. 10, the plan view of the memory cell shown on the upper left side in FIG. 10 is labeled with the symbol of the corresponding MOSFET in FIG. Furthermore, in the plan view of the memory cell shown in the lower part of FIG. 10, the second layer 7 aluminum layer Al
12 (W7),! -1 First layer aluminum layer All
(D6) and AC (D6) are partially removed.

[Embodiment 3] FIG. 11 shows another embodiment of the RAM to which the present invention is applied.

In FIG. 11, parts having the same configuration as in FIG. 9 are given the same symbols. The configuration and operation of the RAM shown in FIG. 11 are almost the same as the configuration and operation of the RAM shown in FIG. Therefore, here, the RAM shown in FIG. 11 and the R shown in FIG.
Only the differences with AM will be explained, and the explanation of the similarities will be omitted.

That is, in the RAM shown in FIG.
A plurality of cells (two in the example) formed in the same memory cell row
One circuit block is composed of memory cells. The conductive polysilicon layer PSi is a MOS F for address selection provided in the same circuit block.
E T Qa, MO8FE is connected only to the gate electrode of Qa and is used for address selection in other circuit blocks.
It is not coupled to the gate electrodes of TQa and Qa. This conductive polysilicon layer PSi is coupled to a corresponding word line in the same manner as the conductive polysilicon layer PSi shown in FIG. That is, in FIG. 9, one circuit block was made up of one memory cell, but in this embodiment, one circuit block is made up of a plurality of memory cells. By doing this, the second aluminum layer A
It is possible to reduce the number of contact holes for bonding A2(Wn) and conductive polysilicon 75PSi. This makes it possible to reduce the limitations caused by the number of contact holes or the size of the area occupied by the contact holes when downsizing the memory cell.

〔effect〕

(1) Since signals are transmitted to each circuit block through the metal wiring layer, signals can be transmitted to each circuit block with a relatively small delay time.

As a result, internal R
It is possible to achieve high-speed operation of the memory.

(2) When the signal from the first wiring layer is supplied to the second wiring layer included in the first circuit block, substantially simultaneously, the signal is supplied from the first wiring layer to the second circuit block. A signal is supplied to the third wiring layer. Second distribution a above
The j layer and the third wiring layer are not directly coupled to each other. Therefore, if a disconnection occurs in the first wiring layer, for example, a signal is supplied to the second wiring #, but no signal is supplied to the third wiring layer. As a result, the first circuit block operates normally, but the second circuit block does not operate normally (or does not operate). Therefore, a break in the first wiring can be easily detected by the DC operation test described above.

In other words, it is possible to detect whether or not a break has occurred in the first wiring through a hour wheel test.

(3) Each circuit block includes circuit elements and wiring means with a relatively large resistance value that connects the circuit elements. This wiring means with a relatively high resistance value is connected at one point to a metal wiring layer for reducing propagation delay time.Thereby, each circuit block is always connected to a predetermined signal via the metal wiring layer. is supplied. When a disconnection occurs in the metal wiring layer, no signal is transmitted to the circuit block on the far end side from the disconnection point. From this, it is possible to detect defects in the metal wiring layer to reduce propagation delay only by using DC operation test scissors. The effect is that the selection can be performed at high speed and with high reliability.

(4) The circuit block on the far end side of the disconnection point does not operate normally (or does not operate). Therefore, it is possible to obtain the effect that evaluation of internal circuits of a large-scale integrated circuit can be performed relatively easily.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the aluminum layer constituting the word line may be a metal wiring layer such as molybdenum.

[Application field]

Although the present invention has been described above with reference to examples in which it is applied to horizontal ROMs and static RAMs, the present invention is not limited thereto. ), and can be widely used in semiconductor integrated circuit devices including circuits in which a large number of circuit elements are connected to relatively long wiring.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of a ROM to which the present invention is applied, Fig. 2 is a circuit diagram drawn in accordance with the layout of the ROM, and Fig. 3 is a circuit diagram showing an embodiment of a ROM to which the present invention is applied. FIG. 4 is a block diagram showing an embodiment of a large-scale semiconductor integrated circuit device, and FIG. 5 is a circuit diagram showing an embodiment of the ROMRO shown in FIG. A plan view showing the layout of the ROM corresponding to the circuit diagram of the ROM, FIG.
Figure 7 is a sectional view taken along line A-A of the layout diagram shown in Figure 5.
The cross-sectional view, FIG. 8, is c-c of the layout diagram shown in FIG.
FIG. 9 is a circuit diagram showing an example of the RAMRA shown in FIG. 3. FIG. 10 is a RAM layout corresponding to the RAM circuit diagram shown in FIG. 9. The plan view, FIG. 11, shows
FIG. 3 is a circuit diagram showing another embodiment of a RAM to which the present invention is applied. Figure 1 Figure 2

Claims (1)

[Claims] 1. A first wiring layer, a first insulated gate field effect transistor, and a second wiring layer coupled to the gate electrode of the first insulated gate field effect transistor and to which a signal from the first wiring layer is supplied. a first circuit having a second insulated gate field effect transistor; and a first circuit having a second insulated gate field effect transistor;
A second circuit having a third wiring layer to which a signal is supplied from the first wiring layer substantially simultaneously with the signal being supplied from the first wiring layer to the wiring layer. Semiconductor integrated circuit device.