JP2784271B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device such as a two-port RAM capable of simultaneously reading or writing a plurality of data.

[0002]

2. Description of the Related Art FIG. 4 is a collection of lectures (469) "2 Port R of DSSP1"
FIG. 1 is a circuit diagram showing a memory cell configuration of a conventional two-port RAM described in "AM". As shown in FIG. 1, in the memory cell section 1, a flip-flop type memory cell 4 is formed by crossing the input and output of CMOS inverters 2 and 3 provided between a power supply and a ground.

The first and second nodes N1 (output of the inverter 2) and N2 (output of the inverter 3) of the memory cell 4 are connected to the first bit line via N-channel access transistors 5 and 6. It is connected to BL1 and bar BL1, respectively. Further, the third and fourth nodes N3 (output of the inverter 2) and N4 (output of the inverter 3) of the memory cell 4 are connected to the second bit line BL2 and the bar through the P-channel access transistors 7 and 8, respectively. B
L2. Then, the first word line WL1 is connected to the gates of the first access transistors 5 and 6, and the second word line WL2 is connected to the gates of the second access transistors 7 and 8.

FIG. 5 is an explanatory diagram showing the overall configuration of a conventional two-port RAM. As shown in FIG. 4, the memory cell unit 1 shown in FIG. 4 is arranged in a matrix, and the first word line WL1 is connected to the first decoder 1 via the word line driver 13.
1 and the second word line WL2 is connected to the second decoder 12 via the word line driver 13. And
The first pair of bit lines BL1 and / BL1 are connected to a first sense amplifier 21 (also serving as a write driver), and the second pair of bit lines BL2 and / BL2 are connected to a second sense amplifier 22.
(Also serves as a write driver).

The first decoder 11 decodes the address signal AD1 and outputs the first word line WL1 via the driver 13.
Is selectively set to H level, the second decoder 12 decodes the address signal AD2, and selectively sets the second word line WL2 to L level via the driver 13.

At the time of reading, the first sense amplifier 21 amplifies the potential difference between BL1 and / BL1 between the first pair of bit lines and outputs it to a first input / output line (not shown). At the time of writing, the write data obtained from the first input / output line is transmitted to the first pair of bit lines BL1 and / BL1.
Similarly, at the time of reading, the second sense amplifier 22
The potential difference between the second bit line pair BL2 and bar BL2 is amplified and output to a second input / output line (not shown), and at the time of writing, write data obtained from the second input / output line is written to the second bit line pair BL2. , Bar BL2.

As described above, the two-port RAM includes the first decoder 11, the first word line WL1, and the first decoder 11 in the memory cell unit 1.
The access transistors 5, 6, the first bit line BL1, and the first sense amplifier 21 constitute a first port, and the second decoder 12, the second word line WL2, the second access transistors 7, 8, in the memory cell 1, A second port is constituted by the 2-bit line BL2 and the second sense amplifier 22.

In the above configuration, a read operation will be described.

First, the address signals AD1 and AD2 are decoded by the first and second decoders 11 and 12, respectively, so that one of the first and second word lines is one of the first and second word lines, respectively. Of word lines WL1 and WL2 are selected.

As a result, the selected first word line WL1
Are turned on, and the second access transistors 7 and 8 connected to the selected second word line WL2 are turned on, so that the data stored in the memory cells 4 in two rows are simultaneously turned on. Appears as a potential difference between the first pair of bit lines BL1 and / BL1 and the second pair of bit lines BL2 and / BL2 independently of the first port and the second port.

Then, the first bit line pair BL1, bar BL
1 is amplified by the first sense amplifier 21 and
And the second bit line pair B
The potential difference between L2 and / BL2 is amplified by the second sense amplifier 22 and read out to the second input / output line.
Simultaneous reading of two data becomes possible.

On the other hand, the writing is performed in the opposite direction to the reading in the first direction obtained through the first and second input / output lines.
And the second write data are amplified by first and second sense amplifiers 21 and 22, respectively, and the first and second bit line pairs BL1, / BL1 and BL2, / B
L2 and the first and second word lines WL1 and WL2 selected by the first and second decoders 11 and 12
The first and second write data are respectively written in the memory cells 1 in the memory cell unit 1 connected to the memory cell unit 1.

In a conventional two-port RAM, generally,
In order to improve the integration degree of the word line, polysilicon or the like, which is a gate material of a transistor, is often used. However, since the wiring material such as polysilicon has a higher resistivity than the metal wiring such as aluminum wiring, when the word line is formed of polysilicon, when accessing the memory cell at the time of reading and writing, it is determined by the RC time constant. The rise and fall times of word lines (hereinafter, collectively referred to as “word line delay times”) become longer, which causes a delay in the access time of the entire memory. In particular, in a large-capacity memory, the word line length tends to be long, and the word line delay time when the word line is formed of polysilicon becomes a nonnegligibly large value.

[0014]

A conventional two-port RAM
Is configured as described above. If the number of memory cells to be connected to the word line increases with the increase in capacity, the word line length becomes too long and the word line resistance becomes too large. There is a problem that the word line delay time determined by the constant becomes a large value that cannot be ignored.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and provides a two-port semiconductor memory device capable of minimizing the word line delay time even if the capacity is increased without impairing the integration. The purpose is to:

[0016]

According to a semiconductor memory device of the present invention, each set is arranged in a matrix with a plurality of word line sets including first and second word lines, and the plurality of word line sets are arranged in a matrix. Each of the first and second word lines is provided with a memory cell commonly connected in a row unit, and each of the plurality of first and second word lines is selectively activated to be selected. Accessing the memory cell connected to the first word line
It is possible to access the memory cells connected to the selected second word line, divide the memory cells in the same row into a plurality of blocks, and divide each block into first and second groups. A first low-resistance wiring having a lower resistance value than the first word line is connected in parallel to only the first word line in the word line set in the blocks of the first group; The second
And a second low-resistance wiring having a lower resistance value than the second word line is connected in parallel to only the second word line in the word line set in the blocks of the group.

[0017]

According to the present invention, a memory cell on the same row is divided into a plurality of blocks, and each block is divided into first and second blocks.
And a first low-resistance wiring having a lower resistance value than the first word line is connected in parallel to only the first word line among the word line sets in the blocks of the first group. Since the second low-resistance wiring having a lower resistance value than the second word line is connected in parallel to only the second word line of the word line set in the blocks of the second group, the first and second lines are connected. The resistance value of each of the first and second word lines is reduced by the provision of the low resistance wiring in parallel.

Further, the first and second low-resistance wirings include
And one of the first and second low-resistance wirings is formed for each memory cell because only one of the first and second low-resistance wirings is formed for each memory cell. I'm done.

[0019]

FIG. 1 shows a two-port R according to an embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of an AM . As shown in FIG. 1, the memory cell array 30 is divided into memory cell array blocks 30A to 30D, and the memory cell portions 31 of the memory cell array blocks 30A to 30D are arranged in a matrix (only one row is shown in FIG. 1), and are the same. For the memory cell unit 31 in the row, the memory cell array blocks 30A to 30A
0D, the first and second word lines WL1 and WL2
Are respectively connected.

Then, the memory cell array block 30
A, 30C, a first bypass wiring 40A, 40 made of aluminum is provided at both ends of the first word line WL1.
C is provided on each of the first word lines in parallel with WL1, and second bypass lines 40B and 40D made of aluminum are provided at both ends of the second word line WL2 in each of the memory cell array blocks 30B and 30D. Are provided in parallel with WL2.

Although not shown, the memory cell unit 31 in each of the memory cell array blocks 30A to 30D is provided.
And bit line pair BL1, bar BL1 and BL2, bar BL
2 is the same as the connection relationship between the memory cell section 1 and the pair of bit lines BL1, / BL1, / BL2, / BL2 in the memory cell array 10 shown in the conventional example of FIGS. In addition to the first and second decoders 11 and 12 and the word line driver 13, the configuration of a sense amplifier (not shown) is the same as that of the conventional example shown in FIG.

FIG. 2 is a circuit diagram showing the inside of the memory cell section 31 shown in FIG. As shown in the figure, the memory cell section 31 constitutes a flip-flop type memory cell 34 by crossing the input and output of CMOS inverters 32 and 33 provided between the power supply and the ground. The CMOS inverter 32 includes a PMOS transistor 32A and an NMOS transistor 32B.
Reference numeral 3 includes a PMOS transistor 33A and an NMOS transistor 33B.

The nodes N5 (output of the inverter 32) and N6 (output of the inverter 33) of the memory cell 34 are connected to the N-channel first access transistor 35.
And 36 are connected to the first bit line BL1 and bar BL1, respectively. The node N of the memory cell 34
5 and N6 are connected to the second bit line BL2 and / BL via N-channel second access transistors 37 and 38, respectively.
2 respectively. Then, the first word line WL1 is connected to the gates of the first access transistors 35 and 36, and the second word line WL2 is connected to the gates of the second access transistors 37 and 38.

A single bypass wiring 40 (40A to 40A) is connected in parallel with the first and second word lines WL1 and WL2.
0D) is provided.

FIG. 3 is an explanatory view schematically showing a planar layout of the memory cell section 31. In the figure, GND indicates a ground line, and V _CC indicates a power supply line. In addition, the hatched portion indicates a transistor active region, and in the wiring shown by a straight line, a solid line is a first layer aluminum wiring, a short broken line is a second layer aluminum wiring,
Long dashed lines indicate polysilicon wiring (word lines and transistor gates), x and ■ indicate contact parts,
□ indicates a via hole.

As shown in FIG. 3, N channel access transistors 35 to 38 and CMO
NMOS transistors 32 of S inverters 32 and 33
B and 33B are formed, and C is formed in the N well region 39B.
The PMOS transistors 32A and 33A of the MOS inverters 32 and 33 are formed.

The access transistors 35 to 38
And the memory cell 34 ( CMOS inverters 32 and 33) via the first layer aluminum wiring and the polysilicon wiring , or by sharing the transistor active region,
The connections are made as shown in the circuit diagram of FIG. The access transistors 35 to 38 and the bit line pair BL1 and bar BL
1 and BL2 and the bar BL2 are connected via via holes.

The first word line WL1 is formed of a polysilicon wiring, and serves as a gate of the first access transistors 35 and 36 to increase the degree of integration. The second word line WL2 is formed of a polysilicon wiring, and the second word line WL2 is formed of a polysilicon wiring. The degree of integration is increased by also serving as the gates of the access transistors 37 and 38. In FIG. 3, a first-layer aluminum interconnection is formed slightly above the first word line WL1.
Is formed of a first layer aluminum wiring.
Formed independently of other wiring (grounding line, power line)
You.

The read and write operations to the memory cell array 31 of the two-port RAM having such a configuration are performed in exactly the same manner as in the prior art. At this time, the first word line WL1 is provided with the first bypass wirings 40A and 40C, and the second word line WL2 is provided with the second bypass wirings 40B and 40D. Each of WL1 and WL2 is equivalent to being connected in parallel with a bypass line having a length of の of the entire length.

Therefore, if the resistance of the bypass wiring is negligible compared to the resistance of the word line, the bypass wiring (first
And 2) a first resistor formed by a combined resistance with the word line.
And the resistance value of the second word line is reduced to half of the conventional value.

That is, since the low-resistance bypass wiring is provided in parallel with each of the first and second word lines, the first and second word line resistances are reduced by the length of the bypass wiring. I can do it.

On the other hand, the load capacitance associated with the first and second word lines is increased by the addition of the bypass line, but the load capacitance associated with the bypass line is smaller than the load capacitance associated with the gate of the access transistor. Therefore, the increase in load capacitance associated with the first and second word lines due to the addition of the bypass wiring can be ignored.

As a result, even if the word line length is increased due to the increase in capacity, the word line resistance value can be sufficiently reduced without adversely affecting other factors. Can be minimized.

Further, as shown in FIG. 1, a bypass line is provided only in one of the first and second word lines WL1 and WL2 in units of a memory cell array block. As shown in FIG.
By simply providing extra aluminum wiring, bypass wiring can be provided to each of the first and second word lines WL1 and WL2, so that the layout area of the memory cell portion 31 increases little by providing the bypass wiring. Only needs to be done. Therefore, the provision of the bypass wiring does not impair the degree of integration.

The memory cell array blocks 30A-
30D, the bypass lines 40A to 40D are provided in parallel with the first and second word lines WL1 and WL2 alternately in units of memory cell array blocks adjacent to WL1, WL2, WL1, and WL2. The bias in the low resistance region due to the connection of the bypass wiring between the word line WL1 and the second word line WL2 can be minimized.

In this embodiment, the read and write operations of the two-port RAM have been described. However, the present invention can be applied to a two-port ROM having a similar configuration. Further, in this embodiment, an example in which the word line is made of polysilicon is shown. However, the present invention is not limited to this. The present invention is applicable to all two-port semiconductor memory devices in which the word line is made of a material that can be highly integrated but has a large resistance. The invention is applicable.

In this embodiment, a two-port RAM is shown. However, the present invention can be applied to a semiconductor memory device having three or more ports capable of simultaneously, reading, or writing three or more data.

[0038]

As described above, according to the present invention, the memory cells in the same row are divided into a plurality of blocks, and each block is divided into first and second groups, respectively. Set of word lines in a block
With respect to only the first word line connecting the first low-resistance wiring resistance lower than the first word line in parallel among the word line sets in a block of the second group
Since the second low-resistance wiring having a lower resistance value than the second word line is connected in parallel to only the second word line, the first
In addition, the resistance of the first and second word lines is reduced by the provision of the second and low resistance wirings in parallel, and the word line delay time can be minimized even when the capacity is increased.

Further, the first and second low-resistance wirings are formed by the first and second low-resistance wirings.
And only one of the first and second low-resistance wirings is formed for each memory cell in each block of the second group. In this case, the integration is not hindered.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a two-port DRAM according to one embodiment of the present invention.

FIG. 2 is a circuit diagram showing details of a memory cell unit shown in FIG. 1;

FIG. 3 is an explanatory diagram illustrating a planar layout of a memory cell unit illustrated in FIG. 1;

FIG. 4 is a circuit diagram showing a memory cell section of a conventional two-port DRAM.

FIG. 5 is a block diagram showing a configuration of a conventional two-port DRAM.

[Description of Signs] 30A to 30D Memory cell array block 34 Memory cell 35 to 38 Access transistor 40 (40A to 40D) (First and second) bypass wiring BL1, bar BL1 first bit line pair BL2, bar BL2 second bit Line pair WL1 First word line WL2 Second word line

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ identification code FI H01L 27/11 (58) Investigated field (Int.Cl. ⁶ , DB name) G11C 11/41 H01L 21/8244 H01L 27/11

Claims (1)

(57) [Claims] 1. A plurality of word line sets each including a first and a second word line, and a plurality of word line sets are arranged in a matrix, and rows are arranged in the first and second word lines in each of the plurality of word line sets. When a memory cell connected to the selected first word line is accessed by selectively activating each of the first and second word lines, the memory cell includes a memory cell commonly connected in units. At the same time, in a semiconductor memory device capable of accessing a memory cell connected to the selected second word line, a memory cell in the same row is divided into a plurality of blocks, and each block is divided into first and second blocks. The first group of the word lines in the blocks of the first group, wherein only the first word line has a lower resistance than the first word line. Resistance distribution Lines in parallel and said words in said second group of blocks
A semiconductor memory device, wherein a second low-resistance wiring having a lower resistance than the second word line is connected in parallel to only the second word line in the line set .