JP2515029B2 - Semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and in particular, in a semiconductor memory device using a two-layer aluminum wiring process, a word line for selecting an arbitrary memory cell is operated at high speed. It is about the improvement for.

[Conventional technology]

FIG. 3 is a conventional schematic diagram showing a method of connecting a word line made of polysilicon and an aluminum layer at a desired interval (hereinafter referred to as a method of staking aluminum of a word line). 1 is a word line made of polysilicon, 2 is a word line made of aluminum, 3 is a contact hole for connecting the word lines 1 and 2, 5 is a memory cell region, and 6 is an X decoder. Note that in an actual device, the word line 2 is located directly above the word line 1, but these positions are shown shifted in FIG. 3 for convenience of explanation.

FIG. 4 is a schematic diagram showing a conventional divided word line system in which a word line selection system is divided into arbitrary memory cell groups and adopted. In the figure, 5a is a divided memory cell group, 1 is the memory cell group. 5 is a divided word line arranged in 5a, 7 is a sub-X decoder for decoding the divided word line 1 in the divided memory cell group 5a, and 4 is a selection line for selecting the memory cell group 5a and is composed of an aluminum layer. ing. Also in this figure, the divided word lines 1 and the memory cell group selection lines 4 are shown at different positions, as in FIG.

 Next, the operation will be described.

The purpose of the aluminum staking method for word lines in FIG. 3 is that the memory cells connected to one word line have a very large gate input capacitance and the polysilicon 1 forming the word line has a large resistance. , The capacitance and the resistance of the polysilicon 1 itself are reduced. In this method, the polysilicon word line 1 and the aluminum layer 2 are connected through a contact hole 3 at a desired interval. The objective, reduction of capacitance and resistance, has been achieved.

Further, in the divided word line system in FIG. 4, in order to reduce the number of memory cells connected to one word line, the memory cell array is divided into a certain memory cell group, and first, the memory cell group is selected. A line 4 is provided, and a sub X decoder 7 which decodes a divided word line in the memory cell group is provided. As a result, the gate capacitance per word line is reduced, and the wiring length of the word line can be shortened by setting the wiring area only within the arbitrary memory cell group. Has been done.

[Problems to be Solved by the Invention]

As a conventional measure for high-speed operation of word lines, the above-described two methods are generally implemented, but since the word line wiring becomes longer as the memory capacity increases,
There is a problem that the resistance of the polysilicon itself forming the word line cannot be reduced only by the aluminum pile driving method.

Also in the divided word line system, there is a problem that an increase in the wiring length of the memory cell group selection line due to an increase in the number of memory cells hinders the high speed operation of the word line.

The present invention has been made to solve the above-mentioned problems, and it is possible to realize a low resistance and a low capacity of a word line, and thereby a semiconductor capable of selecting an arbitrary memory cell at high speed. The purpose is to obtain a storage device.

[Means for solving the problem]

A semiconductor memory device according to the present invention is a memory cell array composed of a plurality of memory cells divided into a predetermined memory cell group, a memory cell group selection line for selecting the memory cell group, and a memory cell group in the memory cell group. The divided word line made of a conductor layer for selecting a memory cell with the divided word line is arranged in parallel with the divided word line at a constant interval, and the divided word line is formed by a plurality of connecting portions made of a metal material. And a metal wiring layer connected to the wire.

[Operation] In the present invention, a memory cell array composed of a plurality of memory cells divided into predetermined memory cell groups, a memory cell group selection line for selecting the memory cell group, and The divided word line for selecting a memory cell is formed in parallel with the divided word line made of a conductive layer and a plurality of connecting portions made of a metal material and arranged in parallel with the divided word line at a constant interval. And the metal wiring layer connected to the word line is used, the divided word line selection method is used to set only the wiring region of the divided word line to the memory cell group, and the entire word line when an arbitrary memory cell group is selected. The wiring length can be shortened, and the wiring resistance of the divided word lines can be reduced by the metal wiring layer. As a result, the high speed operation of the word line can be maintained in the memory device that requires the high speed operation even if the number of memory cells increases.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view for explaining a semiconductor memory device according to an embodiment of the present invention. In FIG. 1, 1 is a divided word line formed of a polysilicon layer, and 2 is a divided word line 1.
Auxiliary word line made of aluminum layer for low resistance of 3
Is a contact hole for connecting the divided word line 1 and the auxiliary word line 2, and is formed at a predetermined interval in the word line direction. Reference numeral 4 is a memory cell group selection line made of an aluminum layer, 5a is a memory cell group, 6 is an X decoder, and 7 is a sub X decoder for decoding the divided word line 1 in the divided memory cell group 5a. Although the divided word line 1, the auxiliary word line 2, and the memory cell group selection line 4 are shown at different positions in this figure, in an actual device, the auxiliary word line 2 is formed on the divided word line 1. The auxiliary word line 2 is composed of the same aluminum layer as the memory cell group selection line 4.

FIG. 2 shows the circuit simulation waveform showing the rise time of the word line, when the aluminum staking method of word lines and the divided word line selection method of the present invention are used together, and only the conventional divided word line selection method. It is shown in comparison with the case of using.

 Next, the function and effect will be described.

In the semiconductor memory device using the two-layer aluminum wiring process, the first layer aluminum can be used for the bit line and the second layer aluminum can be used for the memory cell group selection line of the divided word line selection system. Further, in the memory cell area, the second layer aluminum wiring is used only for the select line 4 of the memory cell group 5a, so that other areas can be used freely.

Therefore, the auxiliary word line 2 of the aluminum layer is realized by performing the aluminum staking of the divided word line 1 by using the metal layer forming the memory cell group selection line 4 in FIG. 1, that is, the second layer of aluminum. The divided word line selection method and the word line aluminum pile driving method can be used together.

As a result, even if the memory capacity increases and the wiring resistance and gate capacity of the word line increase, the word line can operate at high speed by combining the above two methods. Also the second
From the figure, it can be seen that by carrying out the present invention, the speed at the rise of the word line is increased by about 10%.

As described above, in this embodiment, since the aluminum layer of the memory cell group selection line 4 is used as the metal layer for staking the word lines 1, in other words, the aluminum staking method and the divided word line selection method are used in combination. Therefore, even if the capacity of the memory cell is increased, the word line for selecting an arbitrary memory cell can operate at high speed.

〔The invention's effect〕

As described above, according to the present invention, a memory cell array composed of a plurality of memory cells divided into a predetermined memory cell group, a memory cell group selection line for selecting the memory cell group, and the memory cell The divided word line made of a conductor layer for selecting a memory cell in the group and a plurality of connection portions made of a metal material, which are arranged in parallel with the divided word line at a constant interval. Since the divided word line and the metal wiring layer connected to the divided word line are provided, the divided word line selection method is used to set the wiring region of the divided word line to only the memory cell group and the word when an arbitrary memory cell group is selected. The wiring length of the entire line can be shortened, and the wiring resistance of the divided word line can be reduced by the metal wiring layer. As a result, there is an effect that the high speed operation of the word line can be maintained in the memory device that requires the high speed operation even if the number of memory cells increases.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a configuration in which a divided word line selection method according to an embodiment of the present invention and a word line aluminum pile driving method are used in combination, and FIG. 2 shows the word line rise time using the method of the present invention. Waveforms compared with the case of using only the divided word line selection method, FIG. 3 is a schematic diagram showing a conventional aluminum staking method of word lines, and FIG. 4 is a conventional divided word line. It is a schematic diagram showing a selection method. 1 ... Divided word line made of polysilicon, 2 ...
Word lines made of aluminum, 3 ... Word lines 1 and 2
4 for the memory cell group, 5 for the memory cell region, 5a for the memory cell group,
6 ... X decoder, 7 is sub-X decoder. The same reference numerals in the drawings indicate the same or corresponding parts.

 ─────────────────────────────────────────────────── --Continued from the front page (56) Reference JP-A-2-25068 (JP, A) JP-A-62-145862 (JP, A) JP-A-58-199557 (JP, A) JP-A-60- 245271 (JP, A) Actual development Sho 62-63948 (JP, U)

Claims (1)

(57) [Claims] 1. A memory cell array composed of a plurality of memory cells divided into a predetermined memory cell group, a memory cell group select line for selecting the memory cell group, and a memory cell within the memory cell group. A divided word line made of a conductor layer for selection is arranged in parallel to the divided word line at a constant interval, and is connected to the divided word line by a plurality of connecting portions made of a metal material. And a metal wiring layer.