JPS62180594A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To shorten significantly the wiring connecting circuits and a divided memory cell array and to decrease the occupancy ratio of a wiring area by providing a peripheral circuit and a switching circuit approximately at the center of a memory chip. CONSTITUTION:A peripheral circuit 4 for a usual access and a peripheral circuit 5 for refreshment are separately installed at the section of a switching circuit 6 approximately in the center of a memory chip 1, and in the right and left directions of the circuits, memory cell array blocks 2 and 3 are allocated and provided. Thus, while the low power consumption property and low busy ratio are maintained since the memory cell array is divided into a block, wirings 8A-8D can be made into the shortest distance.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a semiconductor memory device in which a normal access peripheral circuit, a refresh peripheral circuit, and a switching circuit are formed approximately in the center of a memory chip, and the left and right peripheral circuits are connected to each other. By forming a configuration in which memory cell arrays are distributed and formed, while maintaining low power consumption and low busy rate,
This makes it possible to significantly shorten the wiring connecting the various ports and the divided memory cell arrays, thereby reducing the occupation rate of the wiring area in the memory chip.

[Industrial application field]

The present invention relates to an improvement in a dynamic semiconductor memory device in which a memory cell array is divided into a plurality of blocks.

[Conventional technology]

The present inventor has previously developed a dynamic memory cell array that reduces power consumption and improves the busy rate by dividing the memory cell array into multiple blocks and dividing the peripheral circuits into normal access and refresh blocks. type semiconductor memory device.

FIG. 3 shows a block diagram of the main parts of the improved dynamic semiconductor memory device.

In the figure, 1 is the memory chip and 2 is the first memory chip.
3 is a second memory cell array block; 4 is a peripheral circuit for normal access; 5 is a peripheral circuit for refresh; 6 is a switching circuit; 7A to 7;
D indicates each wiring made up of a group of signal lines.

In this way, the memory cell array is divided into multiple blocks 2
and 3, and at the time of access, only the block to which the memory cell to be accessed belongs is selected, so that current consumption is reduced in accordance with the number of divisions of the memory cell array.

In addition, the peripheral circuit is divided into the peripheral circuit 4 for normal access and the peripheral circuit 5 for refresh, so that both can operate independently, so that while one of blocks 2 and 3 is normally accessed, the other is refreshed. can,
If the blocks to be accessed normally and those to be refreshed collide, depending on the predetermined priority determination method,
By setting one to execution and the other to standby, we aim to reduce the busy rate.

[Problems to be Solved by the Invention] The Guinamisoku type semiconductor memory device described with reference to FIG. 3 has excellent effects in terms of low power consumption and low busy rate. It consists of dozens of signal lines, including row side address signal lines, word yA drive signal lines, sense amplifier drive signal lines, and signal lines for resetting various parts and providing appropriate timing. .

In this way, in wiring consisting of many signal lines, what are the symbols? Although the wiring indicated by A, 7B, and 7C is fine, the wiring 7D, which is required due to the division of the memory cell array into blocks 2 and 3, becomes long as shown in the figure.

Therefore, it occupies a fairly large area as a wiring area, and as a result, there is a lot of wasted memory chip area.

The present invention aims at making effective use of the memory chip area by reducing the wiring length by devising the layout of each block of the memory cell array and the peripheral circuits.

[Means for solving problems]

In the semiconductor memory device according to the present invention, a peripheral circuit for normal access (for example, peripheral circuit for normal access 4) and a peripheral circuit for refresh (for example, normal access peripheral circuit 4) are separated approximately in the center of a memory chip (for example, memory chip 1). For example, a peripheral circuit for refreshing), a plurality of memory cell arrays (for example, a first memory cell array・Block 2 and second memory・
a cell array block 3), and a switching circuit (for example, a switching circuit 6) that is provided approximately in the center of the memory chip and switches and connects the normal access peripheral circuit and the refresh peripheral circuit to the plurality of memory cell arrays.
It has a configuration that includes the following.

[Effect]

By adopting the above-mentioned measures, while maintaining low power consumption and low busy rate of the semiconductor memory device, the memory can be separated from various ports such as normal access peripheral circuits, refresh peripheral circuits, and switching circuits. This makes it possible to significantly shorten the wiring connecting the cell array and reduce the occupation rate of the wiring area in the memory chip.

〔Example〕

FIG. 1 shows a block diagram of the main parts of one embodiment of the present invention, and the third
Symbols used in the drawings indicate the same parts or have the same meaning.

In the figure, 8A, 8B, 8C, and 8D indicate wiring.

As can be seen from the figure, a normal access peripheral circuit 4 and a refresh peripheral circuit 5 are separated approximately in the center of the memory chip 1 with a switching circuit 6 in between, and memory cell arrays are located on the left and right of these ports.・The configuration is such that blocks 2 and 3 are distributed and arranged.

It will be understood that according to this embodiment, each of the wirings 8A to 8D has the shortest distance.

FIG. 2 is an explanatory diagram of the main part circuit specifically representing the switching circuit indicated by symbol 6 in FIG. 1, and the same symbols as those used in FIG. 1 indicate the same parts or shall have the same meaning.

In the figure, Ql to Q8 are transistors, and INl to IN4 are input terminals, respectively.

This switching circuit 6 operates as follows.

Now, the peripheral circuit 4 for normal access is connected to the memory cell array block 2 or the memory cell array block 3.
If you want to connect to
When the level is reached, transistor Q2 or Q4 becomes conductive and the connection is completed.

Further, in order to connect the refresh peripheral circuit 5 in the same manner, the input terminal IN3 or IN4 may be set to the H'' level.

Such a switching operation can be performed separately and independently for the normal refresh peripheral circuit 4 and the refresh peripheral circuit 5, so one memory cell array block is placed in the normal access state and the other memory cell array block is placed in the normal access state. Placing an array block in a refreshed state is optional.

In the embodiment described with reference to FIGS. 1 and 2,
Although the memory cell array is divided into two, the present invention is not limited to this. For example, one side can be divided into two, so a total of 4
You can also split it up.

In general, the interval between refresh operations is long, but normal access operations can be considered to be almost constant. Therefore, if the memory cell array is divided into two, the power consumption will be approximately 2, and
When divided into four, it becomes approximately A. Note that when the memory cell array is divided into four, the number of switching circuits can be increased. However, it is not preferable to increase the number of divisions of the memory cell array too much, as this will complicate the circuit configuration.

〔Effect of the invention〕

In the semiconductor storage device according to the present invention, a peripheral circuit for normal access, a peripheral circuit for refreshing, and a switching circuit are formed approximately in the middle of a memory chip, and memory cell arrays are distributed to the left and right of these circuits. The structure was created by

According to such a configuration, while maintaining low power consumption and low busy rate due to the memory cell array being divided into blocks, it is possible to connect the various ports such as the peripheral circuits for normal access and the divided blocks. It is possible to significantly shorten the wiring connecting the memory cell array.
It is possible to reduce the occupation rate of the wiring area on the chip, and it is also a reasonable configuration in terms of pattern.
Special techniques such as layered aluminum wiring are no longer required.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the main parts of an embodiment of the present invention, Fig. 2 is an explanatory diagram of the main parts of the switching circuit shown in Fig. 1, and Fig. 3 is a block diagram of the main parts of the conventional example. . In the figure, l is the memory chip and 2 is the first memory chip.
3 is a second memory cell array block; 4 is a peripheral circuit for normal access; 5 is a peripheral circuit for refresh; 6 is a switching circuit; 7A to 7;
D indicates a wiring consisting of a signal line group, and 8A to 8D indicate wiring consisting of a signal line group.

Claims (1)

[Claims] A peripheral circuit for normal access and a peripheral circuit for refresh are separated approximately in the center of the memory chip, and the peripheral circuit for normal access and the peripheral circuit for refresh are distributed to the left and right with the normal access peripheral circuit and refresh peripheral circuit sandwiched therebetween. a plurality of memory cell arrays provided therein; and a switching circuit provided substantially in the center of the memory chip for switching and connecting the normal access peripheral circuit and the refresh peripheral circuit to the plurality of memory cell arrays. A semiconductor memory device characterized by: