JP2887951B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
Particularly, the present invention relates to a highly integrated semiconductor memory device such as a DRAM.

[0002]

2. Description of the Related Art Among semiconductor memory devices in which MOS transistors are integrated, a DRAM is most suitable for high integration because of a small memory cell occupation area. Recently, the minimum processing dimension 0.
16Mbit DRAMs of 6 μm or less have been announced in Japan and overseas, and their mass production is near. In such a highly integrated DRAM, the pursuit of high speed only by improving the switching speed of the MOS transistor by miniaturization has reached its limit, and further improvement in high speed is required. DR
One of the major obstacles to high-speed AM is the sense time of the sense amplifier. The sense time is greatly influenced by the data pattern written in the memory array, and the access time is defined by the data pattern having the longest sense time. This situation is described in JP-A-3-16082. In the configuration described in this publication, the wiring resistance of the discharge path is equivalently reduced by providing the discharge current path from the bit line in multiple directions, and the clamp potential of the bit line discharge path can be reduced.
The bit line discharge time constant is reduced, and the sensing time can be shortened.

[0003] Referring to the drawings,
And will be described in detail. FIG. 4 is a circuit diagram of the DRAM of the present invention.
2 shows a configuration of a core circuit section centered on a amplifier.
Bit line pair BL, / BL (BL₀, / BL₀, BL₁, /
BL₁,...) And word lines WL (WL₀, WL₁,…)
The memory cells M (M₁₁, M
₁₂,...) 1 are arranged. Each bit line pair BL, / B
L is a MOS transistor (Q₁, Q_Two), (Q_Three, Q_Four),
The dynamic sense amplifier circuit SA (SA
₁, SA_Two, ...) 3 and connected to the MOS transistor
(Q₁₁, Q₁₂), (Q₁₃, Q₁₄), ... column
Connected to input / output lines I / O and / I / O via switch 11
Have been. The column switch 11 includes a column decoder 12
Column selection line CSL (CSL₀, CS
L₁, ...). Sense amplifier circuit
The common source line / SAN of the three MOS transistors is
A MOS transistor for driving the sense amplifier circuit SA
Jista Q₉Main sense amplifier drive circuit with a main component
8 and MOS transistor (Q_{twenty one}, Q_{twenty two}, ...)
Connected to the sub-sense amplifier drive circuit 9 as a component
I have. These sense amplifier drive circuits are
In the main sense amplifier driving circuit 8 arranged at the end,
Row block selection signal RBS and sense amplifier active
Controlled by a logic circuit which receives the activation signal SEN.
You. M for drive circuit activation in main sense amplifier drive circuit 8
OS transistor Q₉Are grounded. Ma
In addition, the auxiliary sense amplifier driving circuit 9 has two sense amplifier circuits.
The driver is located in the space between
MOS transistor Q for activating the driving circuit_{twenty one}, Q_{twenty two}Source of
The line passes through the word line snap area 10 in parallel with the bit line.
Grounded.

Here, as the resistance value of / SAN, the driving transistors Q ₉ of the main sense amplifier driving circuit 8 and the driving transistors Q ₂₁ and Q _{22 of the} sub sense amplifier driving circuit 9 are used.
, And / SAN wiring resistances R ₁ , R ₂ ,
R ₂₁ and R ₂₂ are considered. The ON resistance of the former transistor is mainly determined by the gate width of each transistor. Compared to the gate width of the driver transistor Q ₉ of the main sense amplifier driving circuit 8, the gate width of the driver transistor Q _21, Q ₂₂ of the sub-sense amplifier driving circuit 9 can not be increased on the layout area, Q _21, Q ₂₂ each on-resistance is larger than the on-resistance of Q _9. However, the word line lengthens and the snap area 10 per word line increases with the integration degree of the DRAM, so that a large number of sub-sense amplifier driving circuits 9 can be provided. A driving transistor Q ₂₁ arranged in parallel with the driving circuit 9,
The total on-resistance of Q ₂₂ ,... Can be reduced. Also, regarding the wiring resistance of the sub-sense amplifier drive circuit 9, the wiring width of the sub-sense amplifier drive circuit 9 is smaller than that of the main sense amplifier drive circuit 8, and the wiring length is longer. Similarly, the individual values of R ₂₁ , R ₂₂ ,... Are larger than R ₁ and R ₂ , but the total wiring resistance can be reduced by connecting a large number of wires in parallel, and the bit line discharge path can be reduced. Discharge time constant can be reduced.

[0005]

However, in order to further shorten the sensing time due to the demand for higher speed, the bit line discharge path is provided only in the snap region 10 of the word line as in the prior art. If so, there is a possibility that the resistance value cannot be reduced sufficiently from the area.

[0006] The present invention has been made in view of such problems,
It is an object of the present invention to provide a semiconductor memory device in which the discharge time constant of the bit line discharge path is made sufficiently small to further reduce the sense time.

[0007]

SUMMARY OF THE INVENTION The present invention provides a bit line pair coupled to a memory cell, a sense amplifier circuit connected to the bit line pair, and a connection between the sense amplifier circuit and a data input / output line. And a first control line for controlling the first switch is wired at an interval smaller than an arrangement interval of the first switch, and a common source line of the sense amplifier circuit is A first power line connected via a second switch or a first ground line via a third switch, and the first power line or the ground line connected to the first switch for controlling the first switch; A semiconductor memory device which is wired in the same wiring layer as that of the control line to cover a boundary region between two memory cell array regions adjacent in the column address direction.

According to a second aspect of the present invention, there is provided a sense amplifier circuit row including a plurality of CMOS type sense amplifier circuits, the memory cell array arranged corresponding thereto, a common source line of an N type sense amplifier circuit, and a fourth circuit. And a second power supply line connected to a common source line of a P-type sense amplifier circuit and a fifth switch, and the fourth and fifth switches Is the CMOS
, And the CMOS sense amplifier circuit row and the memory cell array arranged corresponding to the CMOS sense amplifier circuit row are divided in the column address direction. When viewed from the boundary region of the CMOS type sense amplifier circuit row region, a wiring for supplying the same potential as the farthest one of the second ground line and the power supply line is connected to the two divided lines adjacent to each other in the column address direction. A semiconductor memory device characterized in that wiring is performed so as to cover a boundary region of a memory cell array region.

[0009]

According to the present invention, the spacing between the first control lines arranged in the memory cell region is made narrower than the spacing between the column switches, so that the space in which the bit line discharge path can be provided also in the memory cell region. Since the discharge path of the bit line charge is extended not only from the word line snap region but also from the word line snap region to the memory cell region, the wiring resistance can be further reduced and the discharge time constant can be reduced. Therefore, it is possible to reduce the sensing time of the sense amplifier circuit.

[0010]

(Embodiment 1) FIG. 1 is a plan view of a DRAM according to a first embodiment of the present invention. FIG. 1A shows a memory cell array region 2 comprising a plurality of memory cells and a sense amplifier circuit. 2 shows a memory area in which sense amplifier circuit array areas 4 are arranged in a matrix. DRAM
The input / output of the data is controlled by the row switch 7, the word line 6 is selected, the column decoder 12 selects the column switch control line CSL, and the column switch control line CSL selected from the column switches by the MOS transistors. Is turned on and the bit line is connected to the input / output line. The column switch control lines CSL are usually wired at intervals of the column switches. However, it is only necessary to input a selection signal to the gate of the MOS transistor which is a column switch. The CSL is wired so as to be narrower than the arrangement interval of the column switches.

In recent DRAMs, metal wires are arranged in parallel with word lines and contacts with the word lines are taken at appropriate intervals in order to prevent a delay caused by a narrow line width of the word lines. The area for making this contact is called a word line snap area 10. The memory area is divided into the memory cell array area 2 by the word line snap area 10.
The sense amplifier circuit array is also divided and arranged as the sense amplifier circuit array region 4 in accordance with the division. Conventionally, the column switch control lines CSL are arranged at intervals of the column switches on the memory cell array region 2.
Only in the word line snap region 10, wiring using the same wiring layer as the column switch control line CSL (for example, second layer aluminum) was possible. However, according to the configuration of the present invention, the column switch control lines CS are provided not only on the word line snap region 10 but also on a part of the memory cell array region 2.
Wiring in the same wiring layer as L is possible.

FIG. 1B is an enlarged view of a hatched portion in FIG. The column switch control line C at an interval l ₁ smaller than the column switch arrangement interval l _{2 in the} sense amplifier circuit array region 4
This indicates that the SL is wired, and that not only the word line snap area 10 but also the memory cell array area 2 is provided with the same wiring layer (for example, second layer aluminum) as the column switch control line CSL. Although FIG. 1A shows that five column switch control lines CSL are wired to the memory cell array region 2, actually, several tens of column switch control lines CSL are wired to the memory cell region 2. ing.

FIG. 2 is a circuit configuration diagram centering on the sense amplifier according to the configuration of the first embodiment of the present invention.

An NMOS type sense amplifier circuit 3 is connected to a drive circuit for driving a sense amplifier. This sense amplifier drive circuit includes a main sense amplifier drive circuit 8 provided at an end of a memory area, and a sense amplifier drive circuit 8. It is constituted by a sub-sense amplifier drive circuit 9 provided at an end of the amplifier circuit array region 4. The main sense amplifier drive circuit 8 includes a row block selection signal RBS and a sense amplifier activation signal SE.
Is constituted by MOS transistor switch Q _9, which results on the logic circuit and the logical operation for taking a logical product of the N. The sub-sense amplifier drive circuit 9 includes MOS transistor switches Q ₂₁ , Q ₂₂ ,... Which are turned on in synchronization with the switch Q ₉ .

In the reading operation, first, the word line 6 is selected, the electric charge of the memory cell 1 connected to the selected word line is read out to the bit line, and then the main and sub sense amplifier driving circuits 8 and 9 are operated. MOS transistor switch Q
_When Q ₉ , Q ₂₁ , Q ₂₂ ... Are turned on, the sense amplifier circuit 3 is activated, and the potential difference between the bit lines BL and / BL is amplified. Bit lines BL and / BL are column switches 1
1, only the column switches connected to the input / output lines I / O and / I / O and connected to the column switch control line CSL selected by the column decoder 12 are turned on, and the potential of the bit line is turned on. Is output to the input / output line and input to the I / O buffer 13.

In order to shorten the sensing time, the wiring resistance of the bit line discharge path / SAN may be reduced. The source line of the sub sense amplifier driving circuit 9 is a column switch control line CSL.
_Vss wired in the same wiring layer (for example, second layer aluminum)
The column switch control line C
When the SL is wired toward the center of the memory cell array region 2 with a distance smaller than the column switch arrangement interval, the column switch control line CS is connected to the end of the memory cell array region 2.
There is an area where the same wiring layer as L can be wired, and the _VSS ground line 1
4 are wired so as to cover the end portions of the word line snap region 10 and the memory cell array region 2 above and below it.

If the V _SS ground line 14 is wired as described above,
Bit line discharge path / SA without increasing chip area
It is possible to keep the wiring resistance of N lower than before. Since the MOS transistors Q ₂₁ , Q ₂₂ ,..., Which are components of the sub sense amplifier drive circuit 9, are provided between the divided sense amplifier circuit row regions 4, the chip area does not increase.

(Embodiment 2) FIG. 3 is a circuit diagram mainly showing a CMOS type sense amplifier according to a second embodiment of the present invention.

The CMOS type sense amplifier circuit comprises an N type sense amplifier circuit 3n and a P type sense amplifier circuit 3p, and respective common source lines / SAN are connected to main sense amplifier drive circuits 8n and 8p, respectively. In this configuration, as the bit line is farther from the main sense amplifier drive circuit, the wiring resistance of the discharge path becomes larger, and voltage clamping becomes a problem.

To solve this problem, the common source line / SAN of each of the N-type and P-type sense amplifier circuits 3n and 3p is
The sub-sense amplifier driving circuit 9n, connect the 9p, word lines snap region 10 to V _SS ground line 14 and the V _CC supply line 15
Although it is sufficient wiring respectively, two sense amplifier circuit array region 4 and the memory cell array sub-sense amplifier driving circuit between the region 2 9n, 9p and V _SS ground line 14, V _CC supply line 1
When wiring 5, the possibility of increasing the chip area must be considered. FIG. 3 shows a configuration for efficiently reducing the wiring resistance of the discharge path of the bit line far from the main sense amplifier driving circuit. Main sense amplifier drive circuits 8n, 8p
Are provided at both ends of the memory area, and a sub-sense amplifier drive circuit 9n is provided between the two sense amplifier circuit row areas 4 far from the main sense amplifier drive circuit 8n and far from the main sense amplifier drive circuit 8p. A sub-sense amplifier drive circuit 9p is provided between the two sense amplifier circuit row regions 4. The sub-sense amplifier driving circuit 9n is connected to V _SS ground line 14, the sub-sense amplifier drive circuit 9p are connected V _CC supply line 15. Other configurations are the same as those in FIG.

Although the first embodiment has been described using an NMOS type sense amplifier circuit, it is also possible to use a PMOS type sense amplifier. Basically, the same circuit configuration may be used, but the _Vcc power supply line is connected to the sub sense amplifier drive circuit instead of the _Vss ground line.

Further, when the column control line CSL is wired so as to be narrower than the interval between the column switches, it is not necessary to narrow the column control line CSL toward the center of the memory cell array region 2, but may narrow it toward an arbitrary position in the memory cell array.

[0023]

According to the present invention, the chip area is increased by wiring the ground line and the power supply line of the bit line discharge path so as to cover not only the word line snap region but also the end of the memory cell region. Therefore, the wiring resistance of the bit line discharge path can be reduced, the sensing time can be shortened, and a high-speed DRAM can be obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor memory device according to a first embodiment of the present invention;

FIG. 2 is a circuit configuration diagram centered on a sense amplifier of the semiconductor memory device of the embodiment;

FIG. 3 shows C of the semiconductor memory device according to the second embodiment of the present invention;
Circuit configuration centering on MOS type sense amplifier

FIG. 4 is a circuit configuration diagram centering on a sense amplifier circuit of a conventional semiconductor memory device;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory cell 2 Memory cell array area 3 Sense amplifier 4 Sense amplifier circuit row area 6 Word line 7 Row decoder 8 Main sense amplifier drive circuit 9 Secondary sense amplifier drive circuit 10 Word line snap area 11 Column switch 12 Column decoder 14 Ground line 15 Power supply line

Claims (2)

(57) [Claims] A bit line pair coupled to a memory cell, a sense amplifier circuit connected to the bit line pair, and a first switch for connecting the sense amplifier circuit to a data input / output line. And a first control line for controlling the first switch is wired at a smaller interval than an arrangement interval of the first switch, and a common source line of the sense amplifier circuit is connected via a second switch. A first power supply line or a first ground line via a third switch;
The power supply line or the ground line is wired in the same wiring layer as the first control line for controlling the first switch so as to cover the boundary region between two memory cell array regions adjacent in the column address direction. Semiconductor storage device. 2. A sense amplifier circuit array comprising a plurality of CMOS type sense amplifier circuits, a memory cell array arranged corresponding thereto, and a common source line of an N type sense amplifier circuit connected by a fourth switch. A second ground line, a second power supply line connected to a common source line of a P-type sense amplifier circuit by a fifth switch, and the fourth and fifth switches are connected to the CMOS type. The CMOS type sense amplifier circuit row and the memory cell array arranged corresponding to the CMOS type sense amplifier circuit row are arranged in the column address direction. When viewed from the boundary region of the CMOS type sense amplifier circuit array region, a wiring for supplying the same potential as that of the second ground line and the farthest power supply line is provided.
A semiconductor memory device, wherein wiring is performed so as to cover a boundary region between two divided memory cell array regions adjacent in a column address direction.