JPS61217994A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To increase a bit line signal voltage and to make possible fast reading by disposing a sense circuit at both sides of a cellarray at two times pitch as large as a pitch in the direction of the word line of a memory cell, multi- dividing the bit line and transmitting them to the sense circuit at both the sides by using a main bit line which is not directly connected to the memory cell. CONSTITUTION:When a certain word line of a left side in a sub-block 1-2 is selected, a memory cell information activated, by the word line is read on bit lines 2-1, 2-3. On bit lines 2-2, 2-4, a dummy cell information activated by a dummy word line 7 is read at the same time of the memory cell information. The memory cell information and the dummy cell information (reference signal) on the bit lines 2-1, 2-2 in the sub-block 1-2 are inputted to a sense circuit 9-1. The memory cell information and the dummy cell information (reference memory cell information and the dummy cell information (reference signal) on the bit lines 2-3, 2-4 in the sub-block 1-2 are inputted to a sense circuit 9-2. By both the sense circuits, the signals are amplified and two memory cell informations are externally read.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary of the Invention] The present invention provides a symmetrical bit line type memory cell array with a symmetrical bit line type memory cell array arranged in the C second direction in the bit line direction. Divide to form multiple chip locks, and connect the main bit line, which is formed in a separate layer from the bit line, in parallel with the bit line (
The bit line and main bit line are divided at the center in the bit line direction in each chip lock, and the two sets of bit line signals and reference signals adjacent to each other in the word line direction are sent to the left and right sides of the divided part, respectively. A switch section is provided to connect to the two main bit lines of C2 on both sides of the memory cell array.
This is a semiconductor memory device in which a sense circuit connected to two main bit lines is arranged, and the sense circuit can be arranged on both sides of the cell array with a pitch twice as large as the pitch in the word line direction of the memory cell, so it is 5 to 10μ. It is possible to provide a memory cell array configuration for extremely small memory cells, and furthermore, (the two bit lines are divided into multiple parts, and each is connected to the sense circuit 1 on both sides using a main bit line that is not directly connected to the memory cell. Therefore, the bit line signal voltage applied to the sense circuit can be increased, enabling high-speed read operation.

[Industrial application field]

The present invention relates to a memory cell array configuration of a high-density, large-capacity, dynamic random access memory (DRAM).
In particular, the present invention relates to a semiconductor memory device C2 having a symmetrical bit i format, that is, a one-cross point type memory cell array configuration C2, in which the sense circuit pitch can be increased.

[Conventional technology]

In dynamic random access memory (hereinafter referred to as DRAM), which has an increasingly large capacity, the memory cell area is steadily decreasing, and the currently researched and developed 1Mb
The memory cell area of DRAM is as small as about 20μ. Fourth
This is an example of a layout of memory cells, and two memory cells are depicted.

2-5.2-6 is a bit line pair (BL and EL), 6 is a word line, 16 is a diffusion layer region, and 14 is a capacitor electrode (
(cell plate), 15 is a groove introduced for high density, and the MO formed with a thin insulating film on the side wall of this groove 15
S capacitor 1: Controls the storage of information depending on whether it stores @load or not. This memory cell layout is for a folded bit layer format (two-intersection type) that is commonly used at present. In this format, a total of two word lines, one word line forming a switch transistor and a passing word line, are required in one memory cell area. These two wiring regions become a factor that hinders reduction in memory cell size when a memory cell with a higher density is assumed.

In other words, in an extremely small memory cell, a memory cell array configuration that can be configured with only one pin for exchanging signals with the memory cell and one word line for selecting the memory cell, that is, a symmetrical (one-intersection type) Also called) Beep) M
Format is desired. This symmetrical bit line format is a configuration that has been widely used in the past.

Figure @5 shows a conventional example of this configuration, in which both sides of the sense circuit (2, 2-1.
, Bl, ) and select the word line indicated by 6, the minute signal which is successively outputted from the memory cell indicated by 4 on bit a of 2-1 is opposite to the bit line indicated by 1.2-1. From the dummy word line C2 indicated by 7 on the side, from the dummy cell indicated by 5 to the pit line C2 simultaneously indicated by 2-2 (; based on the successive reference signals, the sense circuit 9 amplifies them.

[Problem that the invention seeks to solve]

In conventional symmetrical bit line formats, the pitch of the sense circuitry must be equal to the bit line pitch, ie, the vertical pitch of the memory cells. Since the sense circuit requires at least one flip-flop circuit, additional C
When using extremely small memory cells, such as 5 to 10 microns, with high density, it is impossible to keep the sense circuit within its pitch (2), which is close to C2.

Therefore, when attempting to configure a 4Mb or 16Mb class high-density, large-capacity DRAIyf memory cell array, even if the area of the memory cell itself can be reduced, it is limited by C2 such as wiring pips or sense circuit pitch.
There was always a problem if sufficient density could not be achieved.

[Failure to solve the problem]

In order to solve the conventional problems, the present invention divides a symmetrical bit line type memory cell array into multiple parts in the bit line direction to form a plurality of chip locks, and the main bit line is formed in a separate layer from the bit line. The bit line and main bit line are arranged parallel to the bit line in correspondence with the bit line, and the bit line and main bit line are divided at the center in the bit line direction within the chip lock. The memory cell array is characterized by a switch section that connects the reference signal and the reference signal to the two main bit lines on the left and right sides of the dividing section, respectively, and a sense circuit that connects the two main bit lines at both ends of the memory cell array. .

[For production]

The present invention has the following features: 1. Since the sense circuits can be arranged on both sides of the cell array at a pitch that is twice the pitch of the memory cells in the word line direction, it is possible to provide a memory cell array configuration that targets extremely small memory cells of 5 to 10μ77L2. Furthermore, one bit line is divided into multiple parts, and each of them is transmitted to the sense circuits on both sides using a main bit line that is not directly connected to the memory cell, so the bit line signal voltage applied to the two sense circuits is increased. This enables high-speed successive output operations. This will be explained below with reference to the drawings.

〔Example〕

FIG. 1 shows an embodiment of the present invention, in which a memory cell array is
It is a diagram when divided. 1-1.1-2゜1-5.1
-4 is chip lock, 2-1.2-2.2-5゜2-4
are bit lines, 3-1, 5-2, 5-5, 5-4 are main bit lines, 4 is a memory cell, 5 is a dummy cell, 6
is a word line, 7 is a dummy word line, 8 is a switch section, 9
-1.9-2 is a sense circuit. Each subblock 1-
The memory cell array of 1 to 1-4 circles has a configuration in a symmetrical bit line format (one intersection type), and two memory cells are arranged at the intersections of each word line and each bit line. Also, the second
The figure shows an example of the switch section 8 in FIG. 1, and is an example in which a MOS (MOS) transistor is used. Q1 to Q6 are MOS
) is a run star, and the above Q, -Q,
controls the 0N10FF of the transistor.

Next (2) We will explain the circuit operation in this configuration. Now, Figure 1 +
7) 1-2. When the word line on the left side of the chip lock is selected, the memory cell information activated by that word line is read onto the bit lines 2-1 to 2-5. On the other hand, on the bit line C2 indicated by 2-2°2-4, the dummy cell information activated by the dummy word line indicated by 7 is output simultaneously (two times in succession) with the memory cell information. The state of the switch section indicated by is set to C2 as follows.In other words, in the switch section in the sub-block 1-2 in which the selected word line exists, the control line 10 in FIG. 2 is at a high level. situation,
The control line 11 is in a low level state, so that the transistors Q1 and Q2 are in the OFF state, Q, , Q, ,
Transistors Q5 and Q are in the ON state, and 2
The bit line -1 is connected to the main bit line 6-1 and the main bit line 2-
The bit line 2 is the 3-3 main bit line, I-';
)-3 bit line is connected to main bit line 5-2 and 2
The bit line is -4! They are connected to main bit lines 1-4, respectively. On the other hand, in the switch section in the non-selected sub-blocks 1-1.1 to 5.1-4, 10 in FIG.
The control line 11 is at a low level, and the control line 11 is at a high level, so that transistors Q1 and Q are turned on.
Condition, Q3. Q4. Q! , Q6 transistor is OFF
The main bit line 5-1 is connected to the main bit line 3-2, and the main bit line 3-3 is connected to the main bit line 5-4. therefore,
Memory cell information and dummy cell information (reference signal) on the bit lines 2-1 and 2-2 in the sub-block 1-2 and the sense circuit C 9-1 are input to the memory cells 2-5 and 2-2 in the same nap block. The memory cell information and dummy cell information (reference signal) on the bit line 2-4 are input to the sense circuit 9-2, the signals are amplified by both sense circuits (Y), and the two memory cell information are sent to the outside [two consecutive outputs]. be done.

In such a memory cell array configuration, -9-1.
The pitch of the sense circuits indicated by 9-2 can be twice the pitch of the memory cells in the word line direction in the one-cross point type memory cell array C; In addition, although this embodiment uses a configuration in which dummy cells are provided, a configuration in which the dummy cells are omitted is also possible in consideration of the bit line precharge level, and is one aspect of the present invention.

By the way, in the example of the switch shown in FIG. 2C2, the connection relationship between the memory cell information and the sense circuit 9-1 or 9-2 is uniquely determined.
Multi-preflexors selected by column decoder C2 must be placed on both sides of the sense circuit to select output information.

FIG. 6C-2 shows an example of the switch unit 8 of the present invention that can control the connection relationship between memory cell information and the sense circuit 9-1 or 9-2. Main transistor Q1 in Figure 2
~Q6 and other C2, Q-r, Q, , Q*, Q
,. 4 MOS transistors and another control Im shown at 12 are added. In the main part of the selected nap block, the control lines 10 and 11 are in a low level state, and the control line 12 is in a high level state (if set to 2, the control lines 11 and 12 are in a low level state) When the control line 10 is set to the high level state C2, the connection relationship between the sense circuits 9-1 and 9-2 and the memory cell information is reversed, so by controlling the control lines 10 and 12, For example, desired memory cell information can be connected to two sense circuits 9-2. Therefore, in this case, only two multiplexes f need to be placed on the sense circuit a side of 9-2.

The gist of the present invention is illustrated as follows using the embodiment shown in FIG. 2 described above.

A plurality of chip locks (1-1
~1-4), and bit lines (2-1, 2-2) and (2-3°2-4) further divided into C22 in each nap block,
Inside each chip block, bit lines (main bit lines (3-1, 5-2) are arranged in two pairs in parallel with the pit line direction C and are divided at the bit line dividing part in each chip block).
, (5-5, 5-4), and the bit line dividing section in each nub block (two divided bit lines (2-1) and (2-2) t' in the same row, respectively) Connect one of the divided main bit lines C to the other 2-1) (3-1)
, and one main pit line C and two adjacent main bit lines (two connected 2-2) (5-5) in the word line direction,
Each of the two divided bit lines (2-3) and (2-4) t' in the same row as the adjacent main bit line, and the other divided main bit line C are connected to each other (2-5) and C5-2. )
, or connect the main bit lines (2-4) and (5-4) adjacent to the other main bit line in the word line direction, or connect the main bit lines divided into two (5-1) and (
5-2L (5-5)・<5-4) A switch unit (8) that controls whether or not Yfli is connected by an address signal, and a main bit line and a word line direction (two devices) at both ends of the memory cell array. Main bit line C; sense circuit (9-1), (9-2) connecting C to the adjacent main bit line
A semiconductor memory device comprising:

〔Effect of the invention〕

As described above, the present invention uses a high-density memory cell array (two suitable symmetrical bit line type (one intersection type) cell array configuration, and sense circuits are connected to both sides of the cell array.
2. Since the memory cells can be arranged at a pitch twice as large as the pitch in the word line direction, it provides an effective memory cell array configuration for extremely small memory cells of 5 to 10 cells. Further 1
: The bit line is divided into multiple parts, and each is transmitted to the sense circuits on both sides using a main bit line that is not directly connected to the memory cell, so the bit line signal voltage applied to the two sense circuits can be increased. This enables high-speed continuous output operation.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the memory cell array configuration of the present invention. 2
The figure shows an example of a switch section which is a main part of the present invention, FIG. 3 shows an example of a switch part which is a main part of the present invention, and FIG. FIG. 5 is a diagram showing the configuration of a conventional symmetrical bit line format array. 1-1.1-2.1-3.1-4...Memory cell array sub-block, 2-L2-2.2-3.2-4.2-
5.2-6°,. Bit line, 3-1, 3-2.3-3
, 5-4... Main bit line, 4... Memory cell, 5... Dummy cell, 6... Word line, 7... Dummy word line, 8.8-... Switch section, 9. 9-1.
9-2...Sense circuit, 10,11°12...Control a
Line, 13... Diffusion layer region, 14... Capacitor electrode (cell plate), 15... Groove Patent applicant Nippon Telegraph and Telephone Public Corporation agent Patent attorney Gobe Tamamushi (two others) Conventional folding Figure 4: Memory cell layout diagram for conventional symmetric bit line format Figure 5: Array configuration diagram for conventional symmetrical bit line format
figure

Claims (1)

[Claims] A memory cell array configuration in a symmetrical bit line format (one intersection type) consisting of one bit line that exchanges signals with a memory cell and one word line that selects the memory cell. In the semiconductor memory device, the memory cell array is divided into a plurality of sub-blocks in the bit line direction, the bit lines are further divided into two in each of the sub-blocks, and the bit lines in each of the sub-blocks are divided into two. a main bit line arranged corresponding to the bit in parallel with the bit line direction and divided by the bit line dividing portion in each of the sub-blocks; and a main bit line provided at the bit line dividing portion in each of the sub-blocks; and each of the divided bit lines is connected to one of the divided main bit lines in the same row and to each of the main bit lines adjacent to the one main bit line in the word line direction, and Each of the two divided bit lines in the same row as the main bit line is connected to the other divided main bit line and each of the main bit lines adjacent to the other main bit line in the word line direction. , or a switch unit that controls whether or not the two divided main bit lines are connected to each other by an address signal, and a switch unit that is arranged at both ends of the memory cell array and that connects the main bit line and the main bit line in the word line direction. A semiconductor memory device comprising a sense circuit connected to an adjacent main bit line.