JPS63127566A - Mis type semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent the generation of short-circuit accidents among word lines by a residue layer of a second layer polycrystalline silicon layer by dividing a first layer polycrystalline silicon layer into blocks and forming it so as to be isolated at every memory cell in the direction of bit lines and so as not to simultaneously cross two or more of adjacent word lines in the direction of word lines. CONSTITUTION:A first layer polycrystalline silicon layer forming a capacitance electrode is isolated into blocks and shaped so as to be isolated at every memory cell in the direction of bit lines 7a, 7b as shown in 4a and 4b and so as not to simultaneously cross adjacent word lines in the direction of word lines 6a-6d. Since the first layer polycrystalline silicon layer is parted between adjacent two word lines, a residue layer generated when a second layer polycrystalline silicon layer is shaped after a pattern to 6a-6d is also brought to a mutually divided state as shown in 10a and 10b. Accordingly, short circuits among word lines by the residual layer in the second layer polycrystalline silicon can be prevented.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an MIS type semiconductor memory device, and in particular to a capacitor electrode pattern of a one-transistor type semiconductor memory device in which the memory plane is formed of a two-layer structure of polycrystalline silicon. Concerning shape.

[Conventional technology]

The semiconductor memory device most commonly used today is a one-transistor type semiconductor memory device in which one memory cell is constructed using one MIS type transistor and one capacitor.

In this memory cell, the MTS transistor functions as a switching transistor in a circuit connecting the digit line and the capacitor, and stores the digit line potential in the capacitor during writing in response to changes in the word line potential applied to the gate electrode. At the time of reading, it acts to output this accumulated charge to the digit line. That is, in this memory device, the storage content of each memory cell is defined by the presence or absence of accumulated charge in the capacitor.

According to common manufacturing techniques, this capacitive component is made with a so-called MOS structure. In other words, an activated polycrystalline silicon layer is placed on a semiconductor substrate in an island-shaped switching transistor/registration region surrounded by a thick field insulating film, and a thin insulating film is placed between the substrate and the semiconductor substrate. It is formed by sandwiching it. In this structure, the activated polycrystalline silicon layer acts as a capacitive electrode and acts to form an inversion layer at the interface between the thin insulator and the substrate in response to the digit line potential applied through the switching transistor. do. Normally, when the capacitor electrode is formed of polycrystalline silicon in this way, the gate electrode of each memory cell and the gate electrode of the transistor included in the decoder and other peripheral circuits are also formed of activated polycrystalline silicon. That is,
An activated polycrystalline silicon layer is further stacked on the polycrystalline silicon layer forming the capacitor electrode and patterned as a word line passing over the gate of the switching transistor. In this case, insulation between the two polycrystalline silicon layers is usually achieved by a silicon oxide film obtained by thermally oxidizing the surface of the underlying polycrystalline silicon layer.

FIGS. 2(a), (b), and (c) are partial views of the storage plane in a conventional one-transistor type semiconductor memory device with a two-layer structure of polycrystalline silicon layers, and their A-A- and B-
B'' cross-sectional views are shown, which clarify the pattern shapes of the polycrystalline silicon layers forming the memory plane. In other words, the first polycrystalline silicon layer 4 forming the capacitor electrode has a thickness of Switching at the opening of the membrane field insulating film 2 (the edge is indicated by a dashed line)
The entire surface of the memory plane is continuous except for the opening (the edge is shown by a dotted line) of -, which includes a transistor (not shown) forming part and a contact forming part 8 with its bit lines 7a and 7b. On the other hand, the second polycrystalline silicon layer is patterned to be perpendicular to bit lines 7a and 7b to form word lines 6a to 6d. Here, 5 is a thermally oxidized silicon film formed on the surface of the first polycrystalline silicon layer 4,
In FIG. 2(a), hatching is particularly applied to facilitate identification, although this is not appropriate in terms of drawing. Further, a region 9 surrounded by a double dotted line is one memory cell region, and 3 is a thin insulating film formed on the semiconductor substrate 1 within that region.

[Problem that the invention seeks to solve]

However, in general, when patterning a polycrystalline silicon layer, the edge of the opening after the etching process has an angle close to perpendicular to the semiconductor substrate. It grows constricted at the lower end. Therefore, when a second polycrystalline silicon layer is laminated on top of this, the polycrystalline silicon layer grows within this constriction and is not removed during patterning. As shown in the word line 6a
6d is patterned, the residual layer 10 of the second polycrystalline silicon layer remains in the constricted part of the thermally oxidized silicon film 5 without being removed, and the cross section B-B in FIG. 2(c) remains. Below the word lines 6b and 6c that cross the opening of the first polycrystalline silicon layer 4, the residual layer 10 is a thin thermally oxidized silicon film that has grown to protrude into the opening in the shape of an eave. It remains as a horizontal rectangle that is only slightly covered.

Therefore, if the top of the residual layer 10 exceeds the "eaves" of the thermally oxidized silicon film 5, the two word lines 6
A short circuit accident occurs between terminals b and 6c.

Conventionally, as a countermeasure for this, a new etching process using a photomask is inserted to remove a portion of the residual layer 10 at the edge of the opening of the first polycrystalline silicon layer 4 and separate the layers from each other. be exposed. However, when this process is performed,
Misalignment of the mask during photolithography can erode the second layer of polycrystalline silicon and cause the word line to break, or damage to the surface of the semiconductor substrate around the contact formation area can cause leakage current in the diffusion layer. In addition to significantly deteriorating the memory retention function as the number of memory cells increases, it also imposes restrictions on the improvement of the degree of integration.

In view of the above circumstances, an object of the present invention is to provide an MIS type semiconductor memory device that can prevent the occurrence of short circuit accidents between word lines due to the residual layer of the second polycrystalline silicon layer. be.

[Means for solving problems]

According to the present invention, a one-transistor MIS whose memory plane includes a first polycrystalline silicon layer forming a capacitor electrode and a second polycrystalline silicon layer forming a word line
In the type semiconductor memory device, the first polycrystalline silicon layer is separated for each storage cell in the bit line direction, and is separated in the word line direction so as not to cross two or more adjacent word lines at the same time. This includes being formed by dividing into blocks.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIGS. 1(a), (b), and (C) are partial views of a storage plane showing an embodiment of the present invention, and its C-C- and D-D-
FIG. According to this embodiment, the MIS type semiconductor memory device of the present invention includes first-layer polycrystalline silicon layers 4a and 4b forming capacitor electrodes, and a thermally oxidized silicon film 5 on the surface thereof.
Word lines 6a to 6d made of a second layer polycrystalline silicon layer patterned via a and 5b, and a bit line 7a.

7b, where 1, 2, 3, 8 and 9 respectively indicate a semiconductor substrate, a thick field insulating film, a thin insulating film 9 contact forming part, and one memory cell area.

Also, a thermally oxidized silicon film 5a.

5b was hatched in the same manner as in FIG. 2(a).

According to this embodiment, the first polycrystalline silicon layer forming the capacitor electrode is separated for each memory cell in the direction of the bit lines 7a and 7b, as shown in 4a and 4b, and adjacent words in the direction of the word lines 6a to 6d. The lines (for example, 6a and 6b) are formed in separate blocks so that they do not cross at the same time. That is, the first polycrystalline silicon layer is divided into blocks and formed so that the capacitor electrode does not cross two or more adjacent word lines at the same time in the direction parallel to the pitch I line.

In this way, the first polycrystalline silicon layer is 4 a.

When a block is formed as shown in 4b, C-C in Fig. 1(b) is formed.
-As is clear from the cross section, the first polycrystalline silicon layer is not continuous between two adjacent word lines (for example, 6b, 6c), but is divided, so the second polycrystalline silicon layer The residual layers generated when patterning the silicon layer 6a to 6d are also separated from each other as shown in 10a and 10b. Therefore, the short-circuit accident that conventionally tends to occur between the word lines 6b and 6c can be completely solved without adding a step of cutting the residual layer as in the conventional method. In other words, there is no need for a mask margin that occurs during the cutting process of the residual layer, so the degree of integration can be increased, and word line disconnection due to erosion of the second polycrystalline silicon layer in the subsequent process can be avoided. Since the occurrence of undesirable problems such as damage to the surface of the semiconductor substrate around the contact forming portion can be completely suppressed, reliability and extremely high memory retention ability can be achieved at the same time.

[Effects of the Invention] As explained above, according to the present invention, short circuits between word lines can be prevented by the residual layer of the second layer of polycrystalline silicon in a one-transistor type semiconductor memory device consisting of a two-layer polycrystalline silicon layer. This has significant effects that can be achieved at the same time as improving cell integration and reliability.

[Brief explanation of the drawing]

FIGS. 1(a), (b) and (c) are partial views of a storage plane showing one embodiment of the present invention, and its C-C- and D-D-
Cross-sectional views, FIGS. 2(a), (b), and (C) are partial views of the memory plane in a conventional one-transistor type semiconductor memory device having a two-layer structure of polycrystalline silicon layers, and its A-A- and B -B- is a sectional view. 1...Semiconductor substrate, 2...Thickness field insulating film, 3...Thin insulating film, 4.4a, 4
b...First layer polycrystalline silicon layer forming a capacitor electrode, 5°5a, 5b...Thermal oxidation silicon film,
6a to 6d...Word line (second polycrystalline silicon layer), 7a. 7b...Bit line, 8...Contact formation part, 9...One memory cell area, 10.1
0a, 10b... Residual layer of second layer polycrystalline silicon. (b no Confucian l ward (D-D' cross section ji (Cn Fig. 7 4 (a, 4b:, the f-th layer hand that forms as soon as the mass chanting 2 η, 3''b: temporary 9ran ii l > 97 n 1 scarcity (oa,
fo b: $ 2nd layer 4 Wakaakikun I Noko 4 Hakuhaku family layer Fig. 2 (Ej-B' cross section (C) Fig. 2

Claims (1)

[Claims] In a one-transistor MIS type semiconductor memory device in which the storage plane includes a first layer polycrystalline silicon layer forming a capacitor electrode and a second layer polycrystalline silicon layer forming a word line, the first layer polycrystalline silicon layer A MIS type semiconductor characterized in that a crystalline silicon layer is separated for each memory cell in the bit line direction, and divided into blocks in the word line direction so as not to cross two or more adjacent word lines at the same time. Storage device.