JPH01154552A - Semiconductor storage integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To minimize the size of a semiconductor storage integrated circuit device, by providing a first dielectric film formed on a first storing electrode of a stacked capacitor, a first plate electrode formed thereon, a second dielectric film formed thereon, a third dielectric film formed on a second storing electrode of the stacked capacitor and a second plate electrode formed thereon. CONSTITUTION:On a first storing electrode 29, there are deposited sequentially a first capacitor dielectric film 30, a first plate electrode 31 of a conductor, and a second capacitor dielectric film 32 of a nitride or the like having resistance to oxidation. Then, an opening 33 for connecting the first plate electrode 31 is formed so that a side wall of the first plate electrode 31, a side wall of the first storing electrode 29 and a part of the high-concentration diffused layer 28 are exposed. The whole surfaces are then oxidized under a predetermined condition. Thereafter, a partially oxidized layer 36 on the high- concentration diffused layer 28 is selectively etched off. Subsequently, a second storing electrode 37 and a third capacitor dielectric film 38 are formed through similar processes, providing a second plate electrode 40.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing an MO3 type semiconductor Guinami-no-Crunchy random access memory using stacked capacitor cells.

(Prior art) Conventionally, technologies in this field include, for example, separate volumes.
N011 Nikkei Microdevice “4 Starting towards practical application 4 The complete picture of MDRAM JP, 117-130
, P, 165-174 (May 1987).

FIG. 3 shows an example of a method of manufacturing a dynamic random access memory (semiconductor memory integrated circuit device) using such a conventional stack/capacitor cell. here,
The cell part and the peripheral part are shown separately. The cell portion will be mainly described below.

Through a known oxidation and diffusion process, a selective oxide film 2 for isolation, a gate insulating film 3, a gate electrode 4, a sidewall insulating film 5, and a relatively low concentration (10'
A transistor consisting of an impurity diffusion layer 6 of 7 to 1019/cI+ and a relatively high concentration impurity diffusion layer 7 of the same conductivity type as the impurity diffusion 156 (hereinafter referred to as a high concentration diffusion layer), A deposited insulating film 8 is formed (see FIG. 3(a)), where the gate electrode 8i4 also serves as a word line and the heavily doped diffusion Ji17 also serves as a part of a storage capacitor.

Next, a connection hole 9 between the lower electrode of the stacked capacitor and the high concentration diffusion layer 7 is opened by a known photolithography method (including exposure/development/etching) [see FIG. 3(b)].

Subsequently, the lower electrode 10, which will become the charge storage part of the stacked capacitor, is formed by a normal photolithography method [Third
(See Figure (c)) Here, the lower electrode 10 is usually made of polycrystalline silicon of the same conductivity type as the highly doped diffusion N7.

Next, a dielectric film 11 is deposited on the entire surface, and the upper electrode 12 of the stacked capacitor is further formed in a predetermined pattern on the entire surface by a normal photolithography method [FIG. 3(d)]
], here, the upper electrode 12 is usually made of the same type of polycrystalline silicon as the lower electrode 10.

Further, although the dielectric film 11 remains on the entire surface here, it does not matter if it is removed except for the lower part of the upper electrode i12.

Next, a glabellar insulating film 13, a metal wiring 14, and a panshythmation insulating film 15 are formed to obtain the final structure [see FIG. 3(e)].

In addition, in the peripheral area, Fig. 3(a') is
), FIG. 3(d') shows the structure of the peripheral part in FIG. 3(d), and furthermore, a contact hole 16 with a metal wiring 14' which provides a predetermined voltage to the capacitor upper 'l pole 12' is shown. FIG. 3(e') shows the final structure formed at the same time as the photolithography process for forming contact holes that contact metal wiring at predetermined positions on the entire surface.

(Problems to be Solved by the Invention) However, according to the conventional method described above, the stacked capacitor portion is only formed on the opposing surface areas of the lower electrode 10 and the lower electrode 12. Electrode 10
The upper electrode 12 does not face each other! ! The surface in contact with the edge film 8 hardly contributes to the capacitor.

For this reason, when increasing the density of the stacked capacitor cell of this structure, that is, reducing the size of the lower electrode 10, it is necessary to keep the capacitor dielectric P1ill at a constant thickness in order to satisfy the capacitance required for circuit performance. This puts a limit on size reduction. That is, there is a problem that is a major limiting factor in increasing the density of the semiconductor memory integrated circuit device of this structure.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory integrated circuit device that eliminates the above-mentioned problems and can be further miniaturized, and a method for manufacturing the same.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a semiconductor memory integrated circuit device having a stacked capacitor type cell. a storage electrode, a first dielectric film formed on the first storage electrode, a first plate electrode formed on the first dielectric film, and a first plate electrode formed on the first plate electrode. a second dielectric film formed on the impurity diffusion layer, a second storage electrode of the stacked capacitor connected to the impurity diffusion layer, and a third dielectric film formed on the second storage electrode; A second plate electric plumage is formed on the third dielectric crotch.

Further, a semiconductor memory integrated circuit device having the stacked capacitor type cell is manufactured as follows.

A step of forming an isolation region on a substrate, a transistor whose sidewalls directly above the gate electrode are surrounded by an insulating film, and a diffusion layer to which at least the storage electrode is connected, and exposing the surface of the diffusion layer; (A step of forming a first storage electrode in a predetermined shape, which is partially connected to the first storage electrode, and a step of forming a first plate electrode made of a first dielectric film, a conductive polycrystalline silicon film, and an oxidation-resistant film on the entire surface. a step of continuously depositing a second dielectric film on the iS! layer or the first storage electrode; A hole is formed through the first plate electrode, the second dielectric film, and the first dielectric film at the position, and the diffusion layer or the first dielectric film is opened.
exposing the surface of the aperture of the storage electrode; and exposing the exposed aperture side surface of the first plate electrode and the exposed aperture of the diffusion layer or the first storage electrode to a predetermined thickness in an oxidizing cloud atmosphere. By performing anisotropic etching on the entire surface under predetermined conditions for selectively etching only the oxide film, only the oxide film formed on the exposed surface portion of the diffusion layer or the first storage electrode is removed. a step of selectively removing a conductor, a step of depositing a conductor that will become a second storage electrode connected at least in part to the diffusion layer over the entire surface and forming it into a predetermined shape; After forming the body film and depositing the third dielectric film, holes are formed in the first and third dielectric films at predetermined positions in the cell periphery, and
A step of exposing the surface of the second plate electrode, and a step of depositing a conductor to become the second plate electrode over the entire surface and forming it into a predetermined shape to cover at least the storage electrode.

(Function) According to the present invention, with the above configuration, it is possible to obtain approximately three times the capacity of a conventional stacked capacitor with the same size. As a result, the size of the capacitor can be reduced to about ⅓ compared to the conventional capacitor with the same capacitor dielectric material.

(Embodiment) FIG. 1 is a sectional view of a semiconductor memory integrated circuit device showing an embodiment of the present invention, FIG. 1(a) is a sectional view of a cell portion, and FIG. 1(b) is a sectional view of a peripheral portion. It is a diagram.

In this figure, 21 is a substrate, for example, a p-type silicon substrate, 22 is a selective oxide film for element isolation, 23 is a gate insulating film, 24 is a gate electrode, 25 is an insulating film, 26 is a sidewall insulating film, 27 28 is a relatively low concentration impurity diffusion layer of the opposite conductivity type as the substrate 21, for example, n-type, and 28 is a relatively high concentration impurity diffusion layer of the same conductivity type as the impurity diffusion layer 27 (hereinafter referred to as a high concentration diffusion layer). 29 is a first storage electrode connected to the impurity diffusion layer 28, 30 is a first capacitor dielectric film, 31 is a first plate electrode made of a conductor, and 32 is an oxidation-resistant film such as a nitride film. The second capacitor dielectric film 34, 35 having the first storage electrode 29 and the first
A partial oxidation layer formed on the side surface of the plate electrode 31, 3
7 is the second storage electrode, 38 is the third capacitor dielectric film, 39 is the contact hole, 40 is the second plate electrode, and 41 is the third capacitor dielectric film when the second plate electrode 40 is patterned. 38. This is an end portion formed by etching and removing the second capacitor dielectric film 32 and the first plate electrode 31 in a self-aligned manner.
3 is a metal wiring, and 44 is a passivation insulating film. In addition, in the peripheral area, as shown in FIG. 1(b),
In order to apply a plate voltage to the first plate electrode 31 and the second plate electrode 40, the first plate electrode 31
And the second plate electrode 40 is connected to a metal wiring 43'.

FIG. 2 is a manufacturing process diagram of a semiconductor memory integrated circuit device showing an embodiment of the present invention.

The semiconductor memory integrated circuit device is manufactured as follows.

The cell portion will be mainly described below. Identical numbers refer to the same elements as shown in FIG.

First, as shown in Figure 3, through the known oxidation and diffusion steps,
A selective oxide film 22 for element isolation, a gate insulating film 23, and a gate electrode 24 are formed on a substrate 21, for example, a p-type silicon substrate. Thereafter, unlike in the case shown in FIG. 3, gate electrode patterning is performed using a photolithography method to leave an insulating film 25 on the gate electrode 24, and a sidewall insulating film 2G is further formed.

Then, there is an impurity diffusion layer 27 of a relatively low concentration (10" to 10"/J) of the conductivity type opposite to that of the substrate, for example, n-type, and a relatively high concentration impurity diffusion layer of the same conductivity type as the impurity diffusion layer 27. (hereinafter referred to as a high concentration diffusion layer) 28 is formed, and the surface portion of the high concentration diffusion layer 28 is exposed in a self-aligned manner to form a first storage electrode 29 [see FIG. 2(a)]. . This first storage electrode 29 is made of, for example, polycrystalline silicon having the same conductivity type as that of the heavily doped diffusion layer 28 . On the other hand, the structure of the peripheral part of this process is shown in FIG. 2(a').

Next, a first capacitor dielectric film 30, a first plate electrode 31 made of a conductor, and a second capacitor dielectric film v32 having oxidation resistance such as a nitride film are successively deposited [second
See figure (b)]. Here, the first plate electrode 31 may be made of the same material as the first storage electrode 29, and the second capacitor dielectric film 32 may be made of the same material as the first capacitor dielectric film 30. On the other hand, the structure of the peripheral part of this process is shown in FIG. 2(b').

Next, an opening 33 connecting the first plate electrode 31 is formed by a normal photolithography method, and a hole 33 is formed on the side surface of the first plate electrode 31, on the side surface of the first storage electrode 29, and on one side of the high concentration diffusion layer 28. [See Figure 2(c)].

Here, since the first storage electrode 29 and the high concentration diffusion jiJ28 are already connected, the opening 33 is connected to the first storage electrode 2.
You can stop it where the surface of 9 is exposed. That is, it is not necessary to open the opening 33 until the high concentration diffusion layer 28 is exposed. On the other hand, the structure of the peripheral part of this process is
This is the same as in Figure (b').

Next, when the entire surface is oxidized under predetermined conditions, the parts of the first plate electrode 31, first storage electrode 29, and high concentration diffusion layer 28 exposed through the opening 33 are partially oxidized, resulting in a partially oxidized layer 34. .35 and 36 [see Figure 2 (d>)]
. For example, if oxidation is performed at 800 to 950°C, the second capacitor dielectric film 32 will hardly be oxidized even after 100-degree wave changes, and part of the polycrystalline silicon portion and part of the single silicon will be partially oxidized. 100 as layers 34° 35, 36
It is possible to create waves of up to 1,000 people. on the other hand,
The structure of the peripheral part in this step is the same as that shown in FIG. 2(b').

Thereafter, only the partially oxidized portions 1 to 36 on the heavily doped diffusion layer 28 are selectively etched by anisotropic etching (RIE). For example, as an etching gas, CnP2+
++! /CIIH2g system (n, m are integers) allows the etching rate ratio of Sin and StN to be sufficiently large. - For example, when CZF&/C2+14 was used, SiN was hardly etched and a high etching rate of 5t (h only ~ 800 people/min) could be obtained.

In this way, only the oxide layer 36 on the heavily doped diffusion layer 28 is removed, leaving the partially oxidized layers 34 and 35 where polycrystalline silicon is oxidized [see FIG. 2(e)]. On the other hand, the structure of the peripheral part in this step is the same as that shown in FIG. 2(b').

Subsequently, the second storage electrode 37 and the third capacitor dielectric film 3 are formed through the same steps as in FIGS. 3(c) and 3(d).
8 [see FIG. 2(f)]. On the other hand, in the peripheral area of this process, as shown in FIG.
A connection hole 39 is formed in the capacitor dielectric film 32 and the third capacitor dielectric film 38 by a normal photolithography method.

Next, a second plate electrode 40 is formed [Fig.
)reference〕. On the other hand, in the peripheral area of this step, as shown in FIG. 2(g'), a second plate electrode 40 is formed on the entire surface including the connection hole 39, and a second plate electrode
1 and the second plate electrode 40 are connected.

Next, when patterning the second plate electrode 40, the third plate electrode 40 is patterned.
capacitor dielectric film 38. The second capacitor dielectric film 32 and the first plate electrode 31 are removed by etching in a self-aligned manner to form an end portion 41. [See Figure 2 (h)]
. Here, the second storage electrode 37, the second plate electrode 4
0 and the first plate electrode 31 may be made of the same material as the first storage electrode 29, or may be made of a different material. However, the second capacitor dielectric film 32 needs to have oxidation resistance. On the other hand, the structure of the peripheral part of this process is shown in Figure 2 (h'
) is shown.

Next, similar to the process shown in FIG. 3, an interlayer insulating film 42, metal wiring 43, and passivation insulating film 44 are formed to obtain the final structure (see FIG. 1).

Note that the present invention is not limited to the above embodiments,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

(Effects of the Invention) As described above in detail, according to the present invention, two storage electrodes, a first and a second storage electrode, of a stacked capacitor are formed,
Since the upper surface of the first charge storage electrode and the lower and upper surfaces of the second charge storage electrode can be configured as a capacitor, it is possible to obtain approximately three times the capacity with the same size compared to a conventional capacitor configuration. can.

Therefore, for a given capacity that satisfies circuit performance, it is possible to reduce the capacitor size to about 1/3 compared to conventional stacked capacitors, thereby increasing the stacked capacitor cell size and the dynamic memory integrated circuit using it. The densification of ATL can be greatly promoted.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a semiconductor memory integrated circuit device showing an embodiment of the present invention, FIG. 2 is a manufacturing process diagram of a semiconductor memory integrated circuit device showing an embodiment of the present invention, and FIG. 3 is a conventional semiconductor memory integrated circuit device. It is a manufacturing process diagram of a circuit device. 21...Substrate, 22...Selective oxide film for element isolation, 2
3... Gate insulating film, 24... Gate electrode, 25...
... Insulating film, 26... Sidewall insulating film, 27.
... Impurity diffusion layer, 28... High concentration diffusion layer, 29...
・First storage electrode, 30... First capacitor dielectric film, 31... First plate electrode, 32... Second capacitor dielectric film, 33... Opening, 34° 35, 3
6...Partial oxidation layer, 37...Second storage electrode, 38
...Third capacitor dielectric film, 39... Connection hole,
40. ...Second plate electrode, 41...End portion, 42
...Interlayer insulating film, 43...Metal wiring, 44...
Passivation insulation film. Patent applicant Okiden-Ni Kogyo Co., Ltd.

Claims (2)

[Claims] (1) In a semiconductor memory integrated circuit device having a stacked capacitor type cell, (a) a first storage electrode of a stacked capacitor connected to an impurity diffusion layer; (b) formed on the first storage electrode. (c) a first plate electrode formed on the first dielectric film; (d) a second dielectric film formed on the first plate electrode; (e) a second storage electrode of the stacked capacitor connected to the impurity diffusion layer; (f) a third dielectric film formed on the second storage electrode; ) A semiconductor memory integrated circuit device comprising a second plate electrode formed on the third dielectric film. (2) In a method for manufacturing a semiconductor memory integrated circuit device having a stacked capacitor type cell, (a) an isolation region on a substrate, a transistor whose sidewalls and directly above a gate electrode are surrounded by an insulating film, and at least a storage electrode are connected; (b) forming a first storage electrode in a predetermined shape that is at least partially connected to the diffusion layer; (c) A first dielectric film on the entire surface and a first film made of a conductive polycrystalline silicon film.
(d) forming a connection hole to serve as a connection between the diffusion layer and the second storage electrode on the diffusion layer or the second storage electrode; A hole is formed at a predetermined position on the first storage electrode through the first plate electrode, the second dielectric film, and the first dielectric film, and the surface of the hole of the diffusion layer or the first storage electrode is (e) oxidizing the exposed side portion of the opening of the first plate electrode and the exposed portion of the opening of the diffusion layer or the first storage electrode to a predetermined thickness in an oxidizing atmosphere; f) Selectively etching only the oxide film formed on the exposed surface of the diffusion layer or the first storage electrode by performing anisotropic etching on the entire surface under predetermined conditions that selectively etch only the oxide film. (g) depositing a conductor on the entire surface to form a second storage electrode connected at least in part to the diffusion layer and forming it into a predetermined shape; and (h) depositing a third conductor on the entire surface. (i) forming a dielectric film;
After depositing the third dielectric film, forming openings in the first and third dielectric films at predetermined positions in the cell periphery to expose the first plate electrode surface; j) Covering the entire surface with a conductor that will become the second plate electrode,
A method of manufacturing a semiconductor memory integrated circuit device, comprising the step of forming a predetermined shape to cover at least the storage electrode.