JPH01257364A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate maximization of the area of a storage capacitor by forming the storage capacitor pattern when a plate electrode is processed. CONSTITUTION:A conventional manufacturing method is adapted until an interlayer insulating film 5 is formed. Then a single storage capacitor 7 for a pair of memory cells having one bit line in common is formed. A capacitor insulating film 8 and a plate electrode 9 are formed on the storage capacitor 7. When an aperture for providing the contact of the bit line is formed, the plate electrode 9 and the storage capacitor 7 are processed simultaneously to divide the storage capacitor 7 into the respective storage capacitors for a pair of the memory cells. Thus, by forming the aperture, the plate electrode and a pattern at one end of the plate electrode are formed. With this constitution, the storage capacitors can extend to the aperture so that the larger storage capacitance can be realized with the same cell area.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device for RAM with a large capacity.

[Conventional technology]

The reality is that the degree of integration of DRAMs increases fourfold every three years, and this high degree of integration has been achieved through miniaturization of element dimensions. However, due to the decrease in storage capacity associated with miniaturization, adverse effects such as a decrease in the signal/noise (S/N) ratio and signal inversion due to alpha ray irradiation have become apparent, and maintaining reliability has become an issue.

Therefore, as a memory cell that can increase storage capacity, as described in Japanese Patent Publication No. 61-55258,
A stacked capacitor cell (STC
Stacked capacitors have come to be expected to replace conventional planar capacitors.

A cross-sectional view of a conventional STC cell is shown in FIG. 2. First, its manufacturing method and characteristics will be briefly explained.

An interelement isolation oxide film 2 for electrically isolating each element is grown on a single crystal substrate 1. Next, the gate oxide film 3 of the switch transistor is grown using a thermal oxidation method. Polycrystalline silicon 4 containing impurities as a gate electrode
After depositing and processing it using a known photolithography method or dry etching method, an impurity diffusion layer 6 having a conductivity type different from that of the half-substrate is formed using an ion implantation method or the like. Note that 5 is an interlayer insulating film covering the gate electrode. Next, as the storage capacitor 7, the same conductive type a polycrystalline silicon is deposited in a well-known CVD (Chemical Vapor Depot) so as to be in contact with the impurity diffusion layer 6.
si-tion) method. This storage capacity 7
Since it is also formed on the gate electrode 4 and the element isolation oxide film 2, the capacitance value can be increased compared to a conventional planar capacitor structure that uses only the substrate plane. Next, a capacitor insulating film 8 is formed on this storage capacitor 7,
Furthermore, a conductor layer that will become the plate electrode 9 is deposited to complete the MM capacitor 7.

Next, after depositing interlayer insulation 10 and opening contact holes in the diffusion layer of the substrate, bit lines 11 are formed.

As described above, the STC has the advantage that the storage capacity can be increased compared to a planar memory cell in which a capacitor is formed only on the plane of the substrate.

[Problem to be solved by the invention]

However, the conventional technology described above has a problem in that the memory cell area cannot be made much smaller because the storage capacity also decreases as the memory cell area decreases. this is,
A sufficient margin is required between the contact hole of the bit line 11 and the plate electrode 9 in order to prevent an electrical short circuit, and a margin is required for the plate electrode 9 to completely cover the storage capacitor 7. This is due to the fact that a so-called mask alignment margin is required between each layer. These margins limit the area of the storage capacitor 7, and as the memory cell area decreases, the storage capacity also becomes smaller.

An object of the present invention is to provide a storage capacitor manufacturing method for increasing the area of a storage capacitor section in an STC having the same cell area.

[Means to solve the problem]

The above object provides a method for manufacturing a semiconductor device in which a pair of semiconductor memory devices each having at least one switching transistor and one charge storage capacitor are arranged to share a bit line, wherein the charge storage capacitor is arranged to share a bit line. Together with the plate electrode formed on the upper part through an insulating film, the plate electrode is formed up to the upper part of the opening formed to make contact with the bit line, and then when forming the opening,
This is achieved by a method for manufacturing a semiconductor device, characterized in that the portions of the charge storage capacitor and the plate electrode above the opening are removed at the same time.

FIG. 1 is a sectional view of an example of a semiconductor device formed according to the present invention, and FIG. 3 is a plan view of one step of the manufacturing process. The manufacturing process up to the formation of the interlayer insulating film 5 is the same as the conventional method. That is, an oxide film 2 for isolation between elements is grown on the surface of a single crystal substrate 1, and then a gate oxide film 3 is grown. A gate electrode 4 made of polycrystalline silicon or the like is formed on this gate oxide film 3. The film thickness of these films is also the same as in the past, for example, the element isolation oxide film 2 has a thickness of 200 to 1
000nm, and the gate oxide film 3 has a thickness of 1 (1-15nm).
degree is preferred. An impurity diffusion layer 6 is formed using the gate electrode 4 as a mask, and then an interlayer insulating film 5 is formed.

Next, a storage capacitor 7 is formed. At this time, as shown in FIG. 3, the storage capacitors of a pair of memory cells sharing a bit line are formed integrally. Then, a capacitor insulating film 8 and a plate electrode 9 are formed on this. Next, when forming an opening for making a bit line contact (the position of the opening is shown as 14 in FIG. 3), the plate electrode 9 and the storage capacitor 7 are processed simultaneously, and each of the two memory cells is storage capacity. The thickness of storage capacity is 100 to 500
nm is preferred.

Note that the storage capacitor 7 does not necessarily have to be formed by integrating the storage capacitors of the pair of memory cells.

One end of the storage capacitor may be formed to extend to the position of the opening, and by forming the opening, a pattern of the one end may be formed together with the upper electrode.

In the conventional STC, as shown in FIG. 4, each storage capacitor is patterned in advance and then covered with a plate electrode, resulting in a structure with a small 6M capacitance. In contrast, in the present invention, the storage capacity can be extended to the opening, so even with the same cell area, the present invention can achieve a larger storage capacity.

Note that when processing the storage capacitor 7, the capacitor insulating film 8 formed on the surface thereof is also processed at the same time. Such a shape is not necessarily desirable in terms of the characteristics of the insulating film, and in fact, the frequency of breakdown at low voltages may increase. However, the characteristics of the capacitor insulating film can be restored by growing an oxide film, for example, by thermal oxidation, on the exposed plate electrode 9 and side walls of the storage capacitor 7 after processing the storage capacitor.

(Function) As described above, if the storage capacitor pattern is formed during processing of the plate electrode, there is no need for a margin for the plate electrode to completely cover the storage capacitor.As a result, the area of the storage capacitor can be reduced. As a result of experiments, an increase in capacity of 20 to 30% compared to the conventional system has been achieved.

The reason why such a relatively large increase in capacity could be achieved is due to the increase in surface area as well as the following factors.

As shown in FIG. 4, when a conventional rectangular patterned storage capacitor 7 is formed by photolithography, the four corners become rounded due to the light diffraction effect, and the area is substantially reduced. There are only two such corners, and the area increases accordingly.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

Example 1 First, as shown in FIG. 5(a), on a single crystal substrate 1 of a first conductivity type, an inter-element isolation oxide film 2 and a gate oxide film 3 for electrically isolating each element are formed. It is grown using the thermal oxidation method. The element isolation oxide PIA2 was 550 nm thick, and the gate oxide film was 15 nm thick. A gate electrode 4 is formed on this surface, and a second electrode is formed in the substrate using this gate electrode 4 as a mask.
A conductive type impurity diffusion layer 6 is formed. In this example, the conventional single drain structure is used, but a well-known electric field relaxation type drain structure (LDD: Light
tly DopedDrain) may also be used. Here, 5 is an interlayer insulating film covering the gate electrode. At this time,
The storage capacitor 7 formed in the next step is the impurity diffusion layer 6 of the substrate.
The insulating film is removed only from the part that comes into contact with the (Figure 5).
b)).

Next, the storage capacitor 7 is formed. This is because, as shown in FIG. 3, the storage capacitances of each of a pair of memory cells sharing a bit line are not separated. In this embodiment, polycrystalline silicon is used for the storage capacitor 7. The film thickness is 200 nm. Then, in order to make the conductivity type of this polycrystalline silicon the same as that of the impurity diffusion layer 6 formed on the substrate, phosphorus ions were introduced using an ion implantation method. However, in addition to implanting phosphorus ions, known phosphorus diffusion may be used as long as the method does not change the impurity concentration distribution of the impurity diffusion layer 6. Grow the film 8 (Fig. 5(C)
), as the capacitor insulating film 8, the polycrystalline silicon surface was thermally oxidized to form a Sin film, but the 513 deposited
A multilayer film of an N4 film and a Sin film, a high dielectric constant insulating film such as Ta, O, etc. can be used.

A conductive layer that will become the plate electrode 9 is deposited on top of this, and the part for making contact with the bit line is exposed as shown in FIG. Open by dry etching method. Therefore, the size of the opening.

Even if a mask misalignment occurs, the storage capacitance must be sufficiently separated from each other.During this processing, the terminal end of the capacitor insulating film 8 is exposed.

If this continues, there is a risk that dielectric breakdown will occur more frequently at low voltages. In order to repair this, thermal oxidation is performed after processing to grow an oxide film on the exposed side surfaces of the storage capacitor 7 and the entire surface of the plate electrode 9. This oxidation treatment restores the capacitor insulating film to its original characteristics. Polycrystalline silicon is preferable as the material for the plate electrode 9 because such oxidation treatment can be easily performed.

Next, as shown in FIG. 5(d), an interlayer insulating film 10 is formed over the entire structure, a bit line contact hole is opened, and then a bit line 11 is formed.

Embodiment 2 In the first embodiment, the side wall portion of the separated storage capacitor 7 that is not covered by the plate electrode 9 does not become a capacitor. However, by using the manufacturing method described below, it becomes possible to use that portion as a capacitor, and the increase in capacitance becomes even more remarkable. In this case, a high melting point metal such as tungsten is used as the plate electrode.

First, a structure as shown in FIG. 5(d) is formed using tungsten as the plate electrode 9.

Next, this substrate was placed in a hydrogen atmosphere containing about a few percent of water.
When heated to about 000°C, a thin oxide film 1 is formed only on the side walls of the polycrystalline silicon storage capacitor 7, as shown in FIG. 6(a).
6 has grown, and the tungsten surface is not oxidized. Tungsten 17 is deposited again on this entire surface (see Fig. 6).
b)) When this is anisotropically etched using a known dry etching method, tungsten remains only on the sidewalls of the plate electrode 9 and the storage capacitor 7 as sidewall plate electrodes, so that the exposed sidewalls can also be used as capacitors. Become.

After this, bit lines are formed as shown in FIG. 5(e).

〔Effect of the invention〕

According to the present invention, when compared with the same memory cell area,
Compared to a semiconductor device manufactured by a conventional manufacturing method, the storage capacity is increased by 20 to 30%, and the area of the memory cell is therefore reduced. This made it possible to manufacture highly integrated DRAM.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a memory cell according to an embodiment to which the present invention is applied, FIG. 2 is a cross-sectional view of a memory cell to which a conventional method is applied, and FIG. 3 is a cross-sectional view of a memory cell according to an embodiment to which the present invention is applied. 4 is a plan view of a memory cell to which the conventional method is applied; FIG.
6 and 6 are process diagrams for manufacturing a memory cell according to an embodiment of the present invention. 1... Single crystal substrate 2... Inter-element isolation oxide film 3
...Gate oxide film 4...Gate electrode 5...Interlayer insulating film 6...Impurity diffusion layer 7...Storage capacitance 8...Capacitor insulating film 9...Plate electrode 10...Interlayer Insulating film 11...bit line
14... Opening pattern 15... Bit line contact pattern 16... Thin oxidized ill 17.
... Tungsten 18 ... Sidewall plate electrode attorney Junnosuke Nakamura 2nd figure 4--day and t≠ 7-storage nI 1 14--open oJ7=butter>15-m-and" r h Pussy tough μ hub -> Fig. 3 4-7 Scratch 15-m - Go: 1. Har line Koni 7 Rip L Bakushi Fig. 4 (b) (C) Fig. 5 (d) 9-m - Furu) f Ne minute 10-11 layer interval (1 prefecture 11-m- and -), line Figure 5 (a) (b) 7--Ichiban cypress melt amount 8--Canolta (2 faults) For [ 9----button / 17: Inferior 16----ta j1 acid and membrane 17----ta 2g degree 6+8-fit S・Ishi voice bumu F electric 4 possible Compensation (C) Figure 6

Claims (1)

[Scope of Claims] 1. A method for manufacturing a semiconductor device, in which a pair of semiconductor memory devices each having at least one switching transistor and one charge storage capacitor are arranged to share a bit line. The storage capacitor is formed up to the top of the opening formed to make contact with the bit line, together with a plate electrode formed on the top of the storage capacitor through an insulating film, and then when forming the opening, . A method of manufacturing a semiconductor device, characterized in that a portion of the charge storage capacitor and the plate electrode above the opening are removed at the same time. 2. Manufacturing the semiconductor device according to claim 1, wherein the charge storage capacitors of the pair of semiconductor memory devices are formed continuously and integrally at the same time above the position of the opening, and are separated from each other by forming the opening. Method.