KR20000042406A - Semiconductor memory device - Google Patents

Abstract

PURPOSE: A semiconductor memory device having a COB(Capacitor On Bit line) structure is to improve a short-circuit margin between a bit line and a charge storage electrode contact. CONSTITUTION: A DRAM comprises an active region(31) disposed in a folded bit line structure, a word line(33) disposed in the short direction of the active region, bit lines(37) disposed in the ling direction of the active region, and a capacitor provided on an upper portion of the bit line(41). The bit line is disposed in an oblique line so that it intersects the long direction of the active region. The word line acts as a gate electrode of a transistor via a gate oxide film at a part overlapped with the active region. A bit line contact hole(35) is formed between the word lines to expose the active region by an interlayer insulating process. The bit line is electrically connected to the active region via the bit line contact hole. The active region is a substantial rectangle shape.

Description

Semiconductor memory device

The present invention relates to a semiconductor technology, and more particularly to a semiconductor memory device having a capacitor on bit line (COB) structure.

With the development of semiconductor manufacturing technology, high integration of semiconductor memory devices is accelerating, and as the design rules of semiconductor devices are reduced, the size of memory cells is correspondingly reduced. On the other hand, in response to the high integration of the semiconductor memory device, the process becomes more complicated and the structure of the semiconductor memory device also tends to be complicated. In particular, in the case of DRAM, which plays a leading role in semiconductor memory devices, stacked capacitors are typically employed to increase the capacity of the capacitors. In this case, a COB structure is usually used.

Since a semiconductor memory device having a COB structure first forms a bit line in a cell region and then forms a capacitor, the semiconductor memory device of the COB structure has an advantage of increasing the capacitance of a capacitor by forming a large charge storage electrode of the capacitor in a given cell region. On the other hand, the structure of the cell must be changed so that the bit line does not cover the position of the charge storage electrode contact for connecting the charge storage electrode of the capacitor with the active region of the semiconductor substrate.

In a conventional semiconductor memory device having a COB structure, a bit line does not cover the charge storage electrode contact, and a method of changing the position where the charge storage electrode contact is to be formed by diagonally arranging the active regions is performed. You can think of how to change it. However, diagonally arranging the active regions increases the cell region, which may be a detrimental factor in high integration, or the channel regions of the transistors are diagonally formed in the cell, thereby changing the electrical characteristics of the transistors. In particular, increasing the area of the cell due to the alignment error inevitably occurring between the active area and the word line adversely affects the productivity. Therefore, it may be desirable to change the position of the bit line.

Hereinafter, a conventional semiconductor memory device having a COB structure using a method of changing the position of a bit line will be described with reference to FIGS. 1A and 1B. For reference, FIGS. 1A and 1B illustrate different cross sections of the same device.

1A and 1B illustrate a DRAM having a typical COB structure, in which a device isolation film 2 for defining an active region on a silicon substrate 1 through a series of transistor fabrication processes, and a gate insulating film over the active region The bit line and the capacitor are formed in a state where the fine gate electrode 3, the source / drain region 4 provided in a part of the active region, and the like are formed.

To form a bit line and a capacitor, the following process is performed.

The interlayer insulating film 5 is formed on the entire structure in which the above-described transistor manufacturing process is completed, and the contact hole 6 exposing the source / drain region 4 is formed, and then the auxiliary pad 7 is formed. Subsequently, a contact hole 9 for depositing an interlayer insulating film 8 and exposing the auxiliary pad 7 is formed on the entire structure, and then a bit line 10 is formed. In the DRAM of the conventional COB structure, the auxiliary pad 7 extends to the position of the device isolation film 2, and thus the bit line 10 passes over the device isolation film 2. This is to secure a process margin when forming the subsequent charge storage electrode contact hole 12.

Subsequently, the interlayer insulating film 11 is deposited on the entire structure, the interlayer insulating films 11, 8, and 5 are selectively etched to form the charge storage electrode contact hole 12, and the charge storage is performed through a conventional capacitor manufacturing process. The electrode 13, the dielectric thin film 15, and the plate electrode 14 are formed to manufacture a DRAM cell having a COB structure.

However, the conventional semiconductor memory device having the above-described COB structure includes a photolithography process for forming the auxiliary pad 7 and contact hole formation for electrically connecting the auxiliary pad 7 to the bit line 10. In addition, there was a problem that the process is complicated. In addition, a problem arises in that the level increases by the height of the auxiliary pad 7, making it difficult to planarize in a subsequent process. This problem increases the manufacturing cost of semiconductor memory devices and lowers the yield, and therefore, when applied to highly integrated semiconductor memory devices, a huge economic loss is concerned.

The present invention is to provide a semiconductor memory device having a COB structure that can improve the short-circuit margin of the bit line and charge storage electrode contact without complicating the process and increasing the step.

1A and 1B are cross-sectional views of a DRAM having a COB structure

2 is a layout diagram of a DRAM according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31: active area

33: wordline

35: bit line contact hole

37: bitline

39: charge storage electrode contact hole

41: capacitor

In order to achieve the above technical problem, a characteristic semiconductor memory device provided from the present invention includes: an active region disposed in a folded bit line structure; A word line arranged in a short direction of the active area; A bit line disposed in the long axis direction of the active area, the bit lines disposed diagonally so as to alternate between the active areas arranged in the long axis direction and alternately in the bit line contact of the active area to cross the long axis direction; And a capacitor provided on the bit line and contacted to both sides of the bit line contact of the active region.

The present invention is designed to avoid charge storage electrode contacts in a zigzag shape in order to avoid the complexity of the process for forming a COB structure in a conventional semiconductor memory device, the process margin when forming a charge storage contact It is a technique to increase. The present invention does not require any modification of the process or a separate additional process, and can be implemented only by changing the layout of the bitline mask.

Hereinafter, preferred embodiments of the present invention will be introduced so that those skilled in the art can more easily implement the present invention.

3 is a diagram illustrating a layout of a DRAM according to an embodiment of the present invention, which will be described below with reference to the drawings.

The illustrated DRAM has a folded bit line structure in which a rectangular active region 31 is disposed, and the bit line 37 has a central portion of each of the active regions 31 adjacent in the major axis direction of the active region. The device isolation regions between the active regions 31 are arranged in a zigzag shape so as to pass diagonally.

This will be described in detail with reference to the manufacturing process.

First, an element isolation film is formed on a semiconductor substrate to define the rectangular active region 31 to form a gate oxide film. At this time, the active region 31 is arranged in a folded bit line structure. Subsequently, the word line 33 is disposed in the short direction of the active region 31, and the word line 33 serves as a gate electrode of the transistor via a gate oxide film at a portion overlapping with the active region 31.

Then, an interlayer insulating process is performed, and bit line contact holes 35 exposing the active regions 31 between the word lines 33 are formed in the active regions 31, and the bit line contacts 35 are formed. The bit line 37 is electrically connected to the active region 31 through the via. In this case, the bit line 37 is formed in the direction crossing the word line 33, passes through the central portion of each of the active regions 31 adjacent in the long axis direction of the active region 31 in an oblique line, and forms the active region 31. It is formed in a zigzag shape through the device isolation region between).

Subsequently, an interlayer insulating process is performed again, and a charge storage electrode contact hole 39 exposing the active region 31 is formed, and thereby a capacitor 41 electrically connected to the active region 31 is formed.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

According to the present invention, the process for forming the auxiliary pads can be omitted by arranging the bit lines in a zigzag form to secure the process margin, thereby simplifying the process, and the step is increased by the height formed by the height of the auxiliary pads. There is an effect that is reduced to facilitate subsequent processing.

Claims (2)

An active region arranged in a folded bitline structure; A word line arranged in a short direction of the active area; A bit line disposed in the long axis direction of the active area, the bit lines disposed diagonally so as to alternate between the active areas arranged in the long axis direction and alternately in the bit line contact of the active area to cross the long axis direction; And A capacitor provided over the bit line and contacted to both sides of the bit line contact of the active region Semiconductor memory device comprising a. The method of claim 1, And the active region has a substantially rectangular shape.