JPH06151768A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a semiconductor device, wherein memory blocks can be enhanced in degree of integration by lessening the memory block and a gap in level difference between them. CONSTITUTION:Auxiliary films 16 and 18 are provided between a semiconductor substrate 1 and a wiring layer 13 in a gap 57 between memory blocks 54 of a semiconductor device. By this setup, the memory block region 54 and the gap 57 are lessened in level difference between them.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a structure of a semiconductor device and a method of manufacturing the same that enable high integration of a memory block formed in the semiconductor device.

[0002]

2. Description of the Related Art In recent years, semiconductor devices such as DRAM (D
dynamic Random Access Memo
17, a row decoder 51, a sense amplifier 52, a column decoder 53, and a plurality of memory blocks 54 for writing information are arranged on the same substrate. Highly integrated and formed on the same substrate.

Of these, the memory block 54 is divided into a plurality of units on the same substrate. The memory block 54 in this same unit is shown in FIG.
8, a common word line (not shown) is formed on the substrate. Further, due to the demand for high integration, for example, in the case of word lines, a wiring layer is provided as an upper layer and a gap between the memory blocks 54 is provided in order to avoid a decrease in calculation speed due to an increase in wiring resistance due to miniaturization. By forming the contact 56 in the portion 57, the resistance of the wiring is reduced.

FIG. 19 shows adjacent memory blocks 54,
FIG. 5 is an enlarged plan view of 54 and a gap portion 57 thereof.

In the memory block 54, memory cells composed of a plurality of MOS transistors and capacitors are arranged in a matrix of m rows and n columns. In the figure, only the active region 22 of the memory cell, the upper electrode 8 of the capacitor, the aluminum wiring layer 13 and the word line formed in the lower layer, and the contact portion 14 which is the contact position of this aluminum wiring layer 13 are shown. It has been described.

The aluminum wiring layer 13 is formed substantially parallel to the word line formed in the lower layer in the adjacent memory block 54. Further, the contact portions 14 formed in the gap portions 57 are formed so that their positions are displaced in the row direction in order to form the aluminum wirings 13 with high integration.

Next, adjacent memory blocks 54, 54
The cross-sectional structure of the gap portion 57 will be described with reference to FIG. 20 is a sectional view taken along the line X-X in FIG.

First, referring to FIG. 20, word line 4 is formed on semiconductor substrate 1 with isolation oxide film 2 interposed.
A gate oxide film 3 is formed at a predetermined portion of the memory block 54, and the word line 4 forms a gate electrode of a MOS transistor at this portion.

Next, bit lines 5 are formed in the vertical direction in the drawing above the word lines 4 of the memory block 54 at predetermined intervals with an interlayer insulating film 10a interposed therebetween. Further, above the bit line 5, a storage node 6 which is a lower electrode of the capacitor is formed via an interlayer insulating film 10b. Bit line 5 of this storage node 6
A cylindrical storage node 7 extending upward is formed on the upper side of the above in order to increase the capacity of the capacitor.

The inside of this cylindrical storage node 7 and the region of the gap 57 are covered with an interlayer insulating film 11. A cell plate 8 serving as an upper electrode is formed between adjacent cylindrical storage nodes 7 via a dielectric film (not shown).

An upper layer of the cell plate 8 and an upper layer of the interlayer insulating film 11 in the gap 57 are provided with an interlayer insulating film 12 interposed therebetween.
A wiring layer 13 made of aluminum or the like is formed in parallel with the word line 4.

In the area of the gap 57, the wiring layer 13
Part 1 for electrically connecting the word line 4 to the word line 4
4 are provided.

Next, a manufacturing process until the contact portion 14 shown in FIG. 20 is formed will be described with reference to FIGS. 21 to 27.

First, referring to FIG. 21, isolation oxide film 2 is formed on semiconductor substrate 1 by the LOCOS method. After that, the gate oxide film 3 is formed at a predetermined portion of the memory block 54.

Next, the entire surface of the semiconductor substrate 1 is doped with impurities such as polysilicon or refractory metal (W, T
i) A word line 4 is formed by depositing polycide or the like. After that, an interlayer insulating film 10a made of SiO ₂ or the like is formed above the word lines 4.

Next, referring to FIG. 22, the interlayer insulating film 10
A refractory metal or refractory metal polycide or the like is deposited on the entire upper surface of a, and is patterned into a predetermined shape by using a photoengraving technique to form the bit line 5 in the memory block 54. After that, SiO 2 is formed on the entire surface of the semiconductor substrate 1.
_An interlayer insulating film 10b made of ₂ or the like is deposited.

Next, referring to FIG. 23, polysilicon or the like is deposited on the entire surface of the substrate, and the polysilicon is left only in the vicinity of substantially above bit line 5 by using a photolithography technique, and storage node 6 is formed. To form.

Next, referring to FIG. 24, an interlayer insulating film 11 made of SiO ₂ or the like is formed to a predetermined thickness on the entire surface of the substrate. After that, an opening 17 reaching the interlayer insulating film 10b is formed above the bit line 5 by using the photolithography technique. Next, the polysilicon 7 is formed along the inner wall of the opening 17.

Then, referring to FIG. 25, the polysilicon 7 is anisotropically etched so that the polysilicon 7 remains only on the side wall of the opening 17, thereby forming the cylindrical portion 7 of the storage node. To do. After that, polysilicon 8 is deposited on the entire surface of the substrate so as to fill the inside of the opening 17, and then only the polysilicon 8 in the gap 57 is removed by etching to form a cell plate 8 made of the upper electrode of the capacitor. It is formed. In addition, the cell plate 8,
On the contact surface of the storage node with the cylindrical portion 7, SiO ₂
And a dielectric film (not shown) made of Si ₃ N ₄ or the like is formed.

Then, referring to FIG. 26, an interlayer oxide film 12 of SiO ₂ or the like is formed to a predetermined thickness on the entire surface of the semiconductor substrate 1.

Next, referring to FIG. 27, the contact hole 14 communicating with the word line 4 is opened in the region of the gap 57 using the photolithography technique. After that, a metal wiring layer 13 made of Al or the like is deposited to a predetermined thickness on the entire surface of the substrate.
At this time, the contact hole 14 is also filled with Al, and the contact portion 14 electrically connected to the word line 4 is formed.

As described above, the semiconductor device having the sectional structure of the memory blocks 54, 54 and the gap 57 shown in FIG. 20 is completed.

[0023]

However, the above-mentioned conventional technique has the following problems.

First, referring to FIG. 26, since a predetermined memory cell is formed in the memory block 54 of the semiconductor device, a step h is formed on the upper surface of the interlayer insulating film 12 between the memory block 54 and the gap 57. Will occur. For this reason, referring to FIG. 27, when forming contact hole 14a in interlayer insulating films 11 and 12, first, to form contact hole 14a in the region of stepped portion X shown in the figure, In photolithography, it is difficult because the focal length gradually changes. Secondly, in the area of the flat portion Y shown in the figure, the resist film becomes thicker in photolithography, so the resist film is not well formed. It cannot be patterned. Therefore, a contact hole having a desired diameter cannot be opened with high precision, and it is necessary to secure a large margin for opening the contact hole.

As described above, there is a problem in that it is not possible to achieve a high degree of integration of the semiconductor device as a whole because the gap cannot be miniaturized.

The present invention has been made to solve the above problems, and it is possible to achieve high integration of the memory block by reducing the step between the memory block region and the gap. It is an object of the present invention to provide a semiconductor device and a manufacturing method thereof.

[0027]

In a semiconductor device according to a first aspect of the present invention, a semiconductor substrate having a main surface and a MOS arranged on the main surface of the semiconductor substrate with a predetermined gap. Type first and second memory blocks including a transistor and a capacitor;
And the above M provided in common to the second memory block
A word line forming an OS transistor and an upper wiring layer provided in the word line in the same direction as the arrangement direction of the word line via a predetermined interlayer film are provided. Further, an auxiliary film is included between the semiconductor substrate in the gap and the upper wiring layer.

Next, a semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the auxiliary film is formed in the regions of the first and second memory blocks. It is provided at substantially the same height as the bit line that constitutes the MOS transistor.

Next, a semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first aspect, wherein the auxiliary film in the regions of the first and second memory blocks is , Is provided at approximately the same height as the upper electrode that constitutes the capacitor.

Next, a semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the first aspect, wherein the auxiliary film includes the bit line and the capacitor forming the MOS transistor. Are provided at substantially the same height as the bit line and the upper electrode in the regions of the first and second memory blocks, respectively.

Next, a semiconductor device manufacturing method according to a fifth aspect of the present invention has the following configuration.

First, a first memory block formation region and a second memory block formation region are formed on a semiconductor substrate having a main surface with a predetermined gap. afterwards,
A word line commonly extending over the first and second memory block formation regions is formed at a predetermined position of the first and second memory block formation regions, and a MOS transistor forming a memory cell is formed. To be done.

Next, capacitors forming memory cells are formed at predetermined locations in the first and second memory block formation regions.

Thereafter, a predetermined interlayer film formed in the first and second memory block regions in the gap between the first and second memory blocks and the interlayer film formed in the gap. The auxiliary film is formed so that the heights of and are equal.

Next, a wiring layer is formed in parallel with the word line via the interlayer film on the first and second memory block formation regions in which the MOS transistor and the capacitor are formed. It

Next, in a method for manufacturing a semiconductor device according to a sixth aspect of the present invention, which is the method for manufacturing a semiconductor device according to the fifth aspect, the step of forming the auxiliary film is performed as described above. The bit line forming the MOS transistor and the bit line in the regions of the first and second memory blocks are provided at substantially the same height.

Next, in a method for manufacturing a semiconductor device according to a seventh aspect of the present invention, which is the method for manufacturing a semiconductor device according to the fifth aspect, the step of forming the auxiliary film is performed as described above. The upper electrode forming the capacitor is provided at substantially the same height as the upper electrode in the regions of the first and second memory blocks.

Next, in the method of manufacturing a semiconductor device according to claim 8 of the present invention, which is the method of manufacturing a semiconductor device according to claim 5, the step of forming the auxiliary film is performed as described above. The bit line forming the MOS transistor and the upper electrode forming the capacitor are provided at substantially the same height as the bit line and the upper electrode in the regions of the first and second memory blocks.

[0039]

According to the semiconductor device of the first aspect of the invention, the auxiliary film is provided between the semiconductor substrate and the wiring layer in the gap between the memory blocks of the semiconductor device. As a result, the step difference between the memory block region and the gap portion is reduced, and the photolithography for opening the contact hole can be performed with high accuracy. Therefore, the margin in the photolithography can be reduced, and the gap portion can be reduced. It becomes possible to miniaturize.

Next, according to the semiconductor device of the second aspect of the present invention, in the invention of the first aspect, the bit line material of the MOS transistor is replaced with the bit line of the memory block as the auxiliary film. They remain at approximately the same height. As a result, the step between the memory block and the gap is reduced, and the photolithography for opening the contact hole can be performed with high accuracy. Therefore, the margin in the photolithography can be reduced, and the gap of the gap can be reduced. It becomes possible to miniaturize.

Next, according to the semiconductor device of the third aspect of the present invention, in the invention of the first aspect, the upper electrode material of the capacitor serves as the upper electrode of the memory block as the auxiliary film. It remains at the same height. As a result, the step between the memory block and the gap is reduced, and the photolithography for opening the contact hole can be performed with high accuracy. Therefore, the margin in the photolithography can be reduced, and the fineness of the gap can be reduced. Can be realized.

Next, according to the semiconductor device of the fourth aspect of the present invention, in the invention of the first aspect, the bit line material of the MOS transistor and the upper electrode material of the capacitor are used as auxiliary films. The bit lines and the upper electrodes of the memory block are left at substantially the same height. As a result, it is possible to further reduce the step between the memory block and the gap portion as compared with the inventions according to the second and third aspects, and it is possible to further reduce the margin in photolithography. It is possible to further miniaturize the part.

According to the manufacturing method of the fifth aspect of the present invention based on the present invention, the auxiliary film is formed between the semiconductor substrate and the wiring layer in the gap between the memory blocks of the semiconductor device. As a result, the step difference between the memory block and the gap is reduced, so that the photolithography can be performed with high accuracy when the contact hole is opened, so that the margin in the photolithography can be reduced. .

Next, according to the method of manufacturing a semiconductor device of the sixth aspect of the present invention, in the invention of the fifth aspect, the auxiliary film is formed when the bit line material of the MOS transistor is formed. , Also left in the gap. This reduces the step between the memory block and the gap,
Photolithography can be performed with high accuracy when the contact hole is opened, and the margin in photolithography can be reduced.

Next, according to the method of manufacturing a semiconductor device of the seventh aspect of the present invention, in the invention of the fifth aspect, the auxiliary film is formed when the upper electrode material of the capacitor is formed. The upper electrode material also remains in the gap. As a result, the step between the memory block and the gap is reduced, and the photolithography can be performed with high accuracy when the contact hole is opened, so that the margin in the photolithography can be reduced.

Next, according to the method of manufacturing a semiconductor device of the eighth aspect of the present invention, when the bit line material of the MOS transistor and the upper electrode material of the capacitor are formed, the respective gaps are also formed. The bit line material and the upper electrode material are left.

As a result, the step difference between the memory block and the gap is further reduced as compared with the inventions according to claims 6 and 7, and photolithography can be performed with high accuracy when the contact hole is opened. Therefore, it is possible to reduce the margin in photolithography.

[0048]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment based on the present invention will be described below. FIG. 1 is an enlarged plan view of adjacent memory blocks 54 of a DRAM manufactured according to the present invention and its gap 57.

In the memory block 54, memory cells composed of a plurality of MOS transistors and capacitors are arranged in a matrix of m rows and n columns. In the drawing, the active region 22 of the memory cell, the upper electrode 8 of the capacitor, the aluminum wiring 13 and the word line formed in the lower layer, and the contact portion 14 and the gap portion 57 which are the contact positions of the aluminum wiring layer 13 are formed. Only the formed auxiliary film 23 is described for easy understanding.

The aluminum wiring layer 13 is formed substantially parallel to the word line formed in the lower layer in the adjacent memory block 54. Further, the contact portions 14 formed in the gap portion 57 are formed so as to be displaced in the row direction in order to form the aluminum wiring 13 with high integration.
The auxiliary film 23 is patterned so as not to come into contact with the contact portion 14.

Next, the sectional structure of the adjacent memory block 54 and the gap portion 57 will be described with reference to FIG.

FIG. 2 is a sectional view taken along the line X--X in FIG. Referring to FIG. 2, word line 4 is formed on semiconductor substrate 1 with isolation oxide film 2 interposed. A gate oxide film 3 is formed at a predetermined portion of the memory block region 54, and the word line 4 forms the gate electrode of the MOS transistor at this portion.

Next, above the word line 4 of the memory block 54, the bit line 5 is formed in the vertical direction in the figure with a predetermined interval therebetween via the interlayer insulating film 10a.

Also in the region of the gap 57, an auxiliary film 16 made of the same material as the bit line 5 is formed on the word line 4 via the interlayer insulating film 10a at the same height as the bit line 5.

Further, above the bit line 5, a storage node 6 forming the lower electrode of the capacitor is formed. Above the bit line 5 of this storage node 6,
A cylindrical storage node 7 is formed to increase the capacitance of the capacitor.

The inside of the cylindrical storage node 7 and the region of the gap 57 are covered with the interlayer insulating film 11. In addition, a cell plate 8 serving as an upper electrode is formed in the middle of adjacent cylindrical storage nodes 7 with a dielectric film (not shown) interposed therebetween. In addition, the gap 57
An auxiliary film 18 made of the same material as the cell plate 8 is formed on the upper interlayer insulating film 11 and has the same thickness as the cell plate 8.

Next, the cell plate 8 and the auxiliary film 1
A wiring layer 13 made of aluminum or the like is formed on the upper layer of 8 in parallel with the word line 4 with an interlayer insulating film 12 interposed therebetween. Further, in the region of the gap 57, a contact portion 14 for electrically connecting the wiring layer 13 to the word line 4 is provided. Incidentally, the auxiliary films 16 and 18 described above.
Are provided with a predetermined gap so as not to be electrically connected to the contact portion 14.

Next, the manufacturing process until the contact portion 14 shown in FIG. 2 is formed will be described with reference to FIGS.

First, referring to FIG. 3, isolation oxide film 2 is formed on semiconductor substrate 1 by the LOCOS method. After that, the gate oxide film 3 is formed at a predetermined position in the memory block region 54.

Next, the entire surface of the semiconductor substrate 1 is doped with impurities such as polysilicon or refractory metal (W, T
i) Depositing bolicide or the like to form the word line 4.
After that, an interlayer insulating film 10a made of SiO ₂ or the like is formed above the word lines 4.

Next, referring to FIG. 4, the interlayer insulating film 10a is formed.
A refractory metal (W, Ti), a refractory metal polycide, or the like is deposited on the entire upper surface, and patterned into a predetermined shape by photolithography, and the bit line 5 and the gap 57 are formed in the memory block 54. The auxiliary film 16 is formed in the area. After that, an interlayer insulating film 10b made of SiO ₂ or the like is deposited on the entire surface of the semiconductor substrate 1.

Next, referring to FIG. 5, polysilicon or the like is deposited on the entire surface of the substrate, and the bit line 5 is formed by photolithography.
The storage node 6 is formed by leaving the polysilicon only substantially above.

Next, referring to FIG. 6, S is formed on the entire surface of the substrate.
An interlayer insulating film 11 made of iO ₂ or the like is formed to a predetermined thickness. After that, an opening 17 reaching the interlayer insulating film 10b is formed above the bit line 15 by using the photolithography technique. Next, the polysilicon 7 is formed along the inner wall of the opening 17.

Next, referring to FIG. 7, the polysilicon 7 is anisotropically etched so that the polysilicon 7 remains only on the side wall of the opening 17 to form the cylindrical portion 7 of the storage node. . Then, polysilicon 8 is deposited on the entire surface of the substrate even inside the opening 17, and then the polysilicon 8 in the contact hole opening region of the gap 57 is formed.
Only the etching is removed. At this time, the gap 5
The polysilicon 8 left above 7 serves as an auxiliary film 18. As a result, the cell plate 8 serving as the upper electrode of the capacitor is formed. The contact surface between the cell plate 8 and the cylindrical portion 7 of the storage node has an S
Dielectric film (not shown) made of iO ₂ or Si ₃ N ₄
Are formed.

Next, referring to FIG. 8, an interlayer oxide film 12 of SiO ₂ or the like is formed to a predetermined thickness on the entire surface of the semiconductor substrate.

Next, the gap 57 is formed by using photolithography.
A contact hole 14 communicating with the word line 4 is opened in a predetermined region of the. After that, a wiring layer 13 made of Al or the like is deposited to a predetermined thickness on the entire surface of the substrate. At this time, the contact hole 14 is also filled with Al, and the contact portion 14 electrically connected to the word line is formed. As described above, the sectional structure of the memory blocks 54, 54 and the gap 57 having the section shown in FIG.

As described above, according to the semiconductor device of this embodiment, in the gap between the memory blocks of the semiconductor device, the auxiliary films made of the bit line material and the cell plate material are respectively provided between the semiconductor substrate and the wiring layer. It is formed at substantially the same height as the bit line and the cell plate in the region. As a result, the step difference between the memory block area and the gap is reduced, so that the area of the step portion X is reduced with reference to FIG. Further, since the photolithography can be performed with high accuracy when the contact hole is opened, the margin during the photolithography can be reduced and the flat portion Y can be shortened. Therefore, the gap portion can be reduced as a whole, and the semiconductor device can be highly integrated.

Further, since the cell plate having the fixed potential exists in the gap between the memory blocks to the maximum extent, the influence of the electric field from the Al wiring which is the upper wiring layer is influenced by the word line and the bit which are the lower wiring layer. It is also possible to increase the so-called cell plate shield effect, which makes it difficult to receive the lines and improves the operation margin of the device.

Although the bit line material and the cell plate material are used as the auxiliary film in the above-mentioned embodiment, the difference between the memory block and the gap can be reduced by using either one of them. it can.

Next, a second embodiment based on the present invention will be described. FIG. 9 is a cross-sectional view showing the structure of the adjacent memory blocks 54 and the gap portion 57 of the DRAM manufactured according to this embodiment.

First, referring to FIG. 9, a gate oxide film 3 is formed at a predetermined portion of a memory block region 54 where a word line 4 is formed on a semiconductor substrate 1 with an isolation oxide film 2 interposed therebetween. At this point, the word line 4 forms the gate electrode of the MOS transistor.

Next, above the word line 4 in the memory block region 54, the bit line 5 is formed in the vertical direction in the drawing with a predetermined space therebetween via the interlayer insulating film 10a. An auxiliary film 16 made of a bit line material is formed on the interlayer insulating film 10a in the gap 57.

Further, a storage node 6 which is a lower electrode of the capacitor is formed above the bit line 5. Above the bit line 5 of this storage node 6,
A cylindrical storage node 7 is formed to increase the capacitance of the capacitor.

The inside of the cylindrical storage node 7 and the region of the gap 57 are covered with the interlayer insulating film 11. In addition, adjacent cylindrical storage nodes 7
A cell plate 8 forming an upper electrode is formed on the inner side of the cell via a dielectric film (not shown). The material of the cell plate 8 extends on the upper surface of the interlayer insulating film 11 even above the gap 57 to form the auxiliary film 18.

Next, on the upper layers of the cell plate 8 and the auxiliary film 18, the wiring layer 13 is formed in parallel with the word line 4 with the interlayer insulating film 12 interposed therebetween. In the area of the gap 57, a contact portion 14 for electrically connecting the wiring layer 13 to the word line 4 is provided. On the side surface of the contact portion 14, an insulating side wall 20 made of SiO ₂ or the like is formed to have an insulating property with respect to the auxiliary film 16 and the auxiliary film 18.

Next, the manufacturing process until the contact portion 14 shown in FIG. 9 is formed will be described with reference to FIGS.

First, referring to FIG. 10, isolation oxide film 2 is formed on semiconductor substrate 1 by the LOCS method. After that, the gate oxide film 3 is formed at a predetermined portion of the memory block 54.

Next, the entire main surface of the semiconductor substrate 1 is doped with impurities such as polysilicon or refractory metal (T
i, W) Polycide or the like is deposited to form the word line 4. After that, an interlayer insulating film 10a made of SiO ₂ or the like is formed above the word lines 4.

Next, referring to FIG. 11, the interlayer insulating film 10
A refractory metal-containing layer or refractory polycide or the like is deposited on the entire upper surface of a and patterned into a predetermined shape by photolithography to form the bit line 5 in the memory block 54 and an auxiliary film in the region of the gap. 16 is formed. afterwards,
An interlayer insulating film 10b made of SiO ₂ or the like is deposited on the entire surface of the semiconductor substrate 1.

Next, referring to FIG. 12, polysilicon or the like is deposited on the entire surface of the substrate, and the polysilicon is left only above bit line 5 by photolithography to form storage node 6. Form.

Then, referring to FIG. 13, an interlayer insulating film 11 made of SiO ₂ or the like is formed to a predetermined thickness on the entire surface of the substrate. After that, an opening 17 reaching the interlayer insulating film 10b is formed above the bit line 5 by using the photolithography technique. Next, the polysilicon 7 is formed along the inner wall of the opening 17.

Then, referring to FIG. 14, the polysilicon 7 is anisotropically etched so that the polysilicon 7 remains only on the side wall of the opening 17 to form the cylindrical portion 7 of the storage node. After that, the polysilicon 8 is deposited on the entire surface of the substrate even inside the opening 17. As a result, the polysilicon 8 functions as the cell plate 8 in the memory block region and the auxiliary film 18 in the gap region.

The cell plate 8 and the storage node
On the contact surface with the cylindrical portion 7 of ₂And Si₃N_FourSuch
A dielectric film (not shown) made of is formed.

Then, referring to FIG. 15, an interlayer oxide film 12 of SiO ₂ or the like is formed to a predetermined thickness on the entire surface of the semiconductor substrate 1.

Next, the gap 57 is formed by using the photolithography technique.
A contact hole 14 which communicates with the word line 4 is opened in the region of FIG. After that, an insulating sidewall 20 made of SiO ₂ or the like is formed along the inner wall of the contact hole 14.

Next, referring to FIG. 16, the insulating sidewall 20 is anisotropically etched so that the insulating sidewall 20 film remains only on the sidewall of the contact hole 14 to insulate only the sidewall of the contact hole. The side wall 20 is formed. Then, the wiring layer 14 made of Al or the like is deposited to a predetermined thickness even inside the contact hole 14. At this time, Al is also filled in the contact hole 14 to form the contact portion 14 electrically connected to the word line 4.

As described above, the sectional structure of the memory block portion 54 and the gap portion 57 shown in FIG. 9 is completed.

As described above, in the semiconductor device according to this embodiment, the auxiliary film made of the bit line material and the cell plate material is provided between the semiconductor substrate and the wiring layer in the gap between the memory block regions of the semiconductor device. It is provided.
As a result, the step difference between the memory block area and the gap portion is reduced, so that the area of the step portion X is reduced with reference to FIG. Further, since the photolithography can be performed with high accuracy when the contact hole is opened, the margin at the photolithography can be reduced, and the flat portion Y can be shortened. Therefore, the gap portion can be reduced as a whole, and the semiconductor device can be miniaturized. In addition, in the present embodiment, the above-mentioned first
Compared with the embodiment of the above, in the patterning of the bit line material and the cell plate material formed as the auxiliary film, in order to provide the insulating sidewall on the sidewall of the contact hole,
The auxiliary film can be easily formed without the need for patterning for avoiding the contact holes.

Further, since the cell plate having the fixed potential exists in the gap between the memory blocks to the maximum, the influence of the electric field from the Al wiring which is the upper wiring layer is influenced by the word line and the bit which are the lower wiring layer. It is also possible to increase the so-called cell plate shield effect, which makes it difficult to receive the lines and improves the operation margin of the device.

Although the bit line material and the cell plate material are used as the auxiliary film in the above embodiment, the difference between the memory block and the gap can be reduced by using either one of them.

[0091]

According to the semiconductor device and the method of manufacturing the same according to the present invention, the auxiliary film is provided between the semiconductor substrate and the wiring layer in the gap between the memory block regions. As a result, the step difference between the memory block region and the gap portion is reduced, so that it is possible to reduce the step portion region caused by the step difference between the memory block region and the gap portion. Therefore, since the photolithography can be performed with high accuracy when the contact hole is opened due to the reduction in the stepped portion, it is possible to reduce the margin during the photolithography and also to shorten the flat portion. it can. As a result, the gap can be reduced as a whole, and the semiconductor device can be miniaturized.

Further, since the cell plate having the fixed potential exists in the gap between the memory blocks to the maximum, the influence of the electric field from the Al wiring which is the upper wiring layer is influenced by the word line and the bit which are the lower wiring layer. It is also possible to increase the so-called cell plate shield effect, which makes it difficult to receive the lines and improves the operation margin of the device.

In the method of manufacturing a semiconductor device according to the present invention, the auxiliary film is formed simultaneously with the auxiliary film by using the bit line material and the cell plate material as the auxiliary film. Since the auxiliary film can be provided, it is possible to efficiently form the auxiliary film without providing another step for forming the auxiliary film.

[Brief description of drawings]

FIG. 1 is an enlarged plan view of adjacent memory blocks and a gap between adjacent memory blocks in a first embodiment according to the present invention.

FIG. 2 is a sectional view taken along line XX in FIG.

FIG. 3 is a first diagram of the first embodiment according to the present invention.
It is sectional drawing which shows a manufacturing process.

FIG. 4 is a second view of the first embodiment according to the present invention.
It is sectional drawing which shows a manufacturing process.

FIG. 5 is a third embodiment according to the present invention.
It is sectional drawing which shows a manufacturing process.

FIG. 6 is a fourth diagram according to the first embodiment of the present invention.
It is sectional drawing which shows a manufacturing process.

FIG. 7 is a fifth embodiment according to the present invention.
It is sectional drawing which shows a manufacturing process.

FIG. 8 is a sixth embodiment according to the present invention.
It is sectional drawing which shows a manufacturing process.

FIG. 9 is a sectional structural view of a semiconductor device according to a second embodiment of the present invention.

FIG. 10 is a cross-sectional view showing the first manufacturing process in the second embodiment according to the present invention.

FIG. 11 is a sectional view showing a second manufacturing step in the second embodiment according to the present invention.

FIG. 12 is a sectional view showing a third manufacturing process in the second embodiment according to the present invention.

FIG. 13 is a sectional view showing a fourth manufacturing step in the second example according to the present invention.

FIG. 14 is a sectional view showing a fifth manufacturing process in the second embodiment according to the present invention.

FIG. 15 is a sectional view showing a sixth manufacturing step in the second example according to the present invention.

FIG. 16 is a sectional view showing a seventh manufacturing process in the second embodiment according to the present invention.

FIG. 17 is a plan view showing the overall structure of a semiconductor device.

FIG. 18 is a plan view showing the structure of a memory block in one unit.

FIG. 19 is an enlarged plan view of a semiconductor device according to a conventional technique.

20 is a cross-sectional view taken along the line XX in FIG.

FIG. 21 is a cross-sectional view showing a first step based on the manufacturing method in the conventional technique.

FIG. 22 is a cross-sectional view showing a second step based on the manufacturing method in the conventional technique.

FIG. 23 is a cross-sectional view showing a third step based on the manufacturing method in the conventional technique.

FIG. 24 is a cross-sectional view showing a fourth step based on the manufacturing method in the conventional technique.

FIG. 25 is a cross-sectional view showing a fifth step based on the manufacturing method in the conventional technique.

FIG. 26 is a cross-sectional view showing a sixth step based on the manufacturing method in the conventional technique.

FIG. 27 is a cross-sectional view showing a seventh step based on the manufacturing method in the conventional technique.

[Explanation of symbols]

 1 semiconductor substrate 2 isolation oxide film 3 gate oxide film 4 word line 5 bit line 6 storage node (lower electrode) 7 storage node (cylindrical part) 8 cell plate (upper electrode) 10, 10a, 10b, 11, 12 interlayer insulating film 13 Aluminum Wiring Layer 14 Contact Part 16 Auxiliary Bit Line 18 Auxiliary Cell Plate 20 Insulating Sidewall 22 Memory Cell Active Region 54 Memory Block 57 Gap Part In the drawings, the same reference numerals indicate the same or corresponding parts.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 7210-4M H01L 27/10 325 P

Claims (8)

[Claims] 1. A first substrate including a semiconductor substrate having a main surface, and a MOS transistor and a capacitor arranged on the main surface of the semiconductor substrate with a predetermined gap.
And a second memory block, a word line forming the MOS transistor provided in common to the first and second memory blocks, and a word line on the word line via a predetermined interlayer film. An upper wiring layer provided in the same direction as the arrangement direction,
A semiconductor device comprising: an auxiliary film between the semiconductor substrate in the gap and the upper wiring layer. 2. The semiconductor device according to claim 1, wherein the auxiliary film is provided at substantially the same height as a bit line forming the MOS type transistor in the first and second memory block regions. 3. The semiconductor device according to claim 1, wherein the auxiliary film is provided at substantially the same height as an upper electrode forming the capacitor in the first and second memory block regions. 4. In the auxiliary film, a bit line forming the MOS transistor and an upper electrode forming the capacitor are substantially the same as the bit line and the upper electrode in the first and second memory block regions, respectively. The semiconductor device according to claim 1, wherein the semiconductor device is provided at the height of. 5. A step of forming a first memory block formation region and a second memory block formation region on a semiconductor substrate having a main surface with a predetermined gap therebetween, the first and second memory block formation regions being formed. Forming a word line commonly extending over the first and second memory block forming regions at a predetermined position of the second memory block forming region, and further forming a MOS type transistor constituting a memory cell; Forming a capacitor forming a memory cell at a predetermined location of the first and second memory block formation regions, and forming a capacitor between the first and second memory block regions in the first and second memory block formation regions. Forming an auxiliary film so that a predetermined interlayer film formed in the second memory block region and the interlayer film formed in the gap have the same height; Forming a wiring layer parallel to the word line on the first and second memory block formation regions in which the transistor and the capacitor are formed, with the interlayer film interposed therebetween. Production method. 6. The step of forming the auxiliary film comprises the step of forming the MO film.
6. The method of manufacturing a semiconductor device according to claim 5, further comprising the step of providing the bit line forming the S transistor and the bit line in the regions of the first and second memory blocks at substantially the same height. 7. The step of forming the auxiliary film includes the step of providing an upper electrode forming the capacitor at substantially the same height as the upper electrodes in the regions of the first and second memory blocks. Item 6. A method for manufacturing a semiconductor device according to item 5. 8. The step of forming the auxiliary film comprises the step of forming the MO film.
6. The bit line forming an S transistor and the upper electrode forming the capacitor are provided at substantially the same height as the bit line and the upper electrode in the regions of the first and second memory blocks. Of manufacturing a semiconductor device of.