JPH0661443A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a semiconductor device wherein, while a stable operation is maintained, a high integration can be achieved and a capacitor having a prescribed capacitor capacitance is provided and to provide its manufacturing method. CONSTITUTION:A lower-part electrode 1 is constituted of a first part 2 and a second part 3. The first part 2 is formed along the surface of a nitride film 14. The second part 3 is provided with a part which comes into contact with the first part 2 and which is extended to the upper part from the surface of the first part 2 and with a part which is extended along the surface of the nitride film. A dielectric layer 5 is formed so as to cover the whole surface of the lower-part electrode 1. An upper-part electrode 4 is formed so as to cover the whole surface of the dielectric layer 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device capable of random input / output of stored information and suitable for high integration, and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, the demand for semiconductor devices has been rapidly expanding due to the remarkable spread of information devices such as computers. Further, functionally, it is required to have a large-scale storage capacity and be capable of high-speed operation. Along with this, technological developments relating to high integration of semiconductor devices and high-speed response or high reliability are being advanced.

Among semiconductor devices, a DRAM (Dynamic Random A
ccess Memory) is generally known. This DRAM
Is composed of a memory cell array, which is a storage area for accumulating a large amount of storage information, and peripheral circuits necessary for external input / output.

The structure of this DRAM will be described below. FIG. 29 is a block diagram showing a configuration of a general DRAM. Referring to FIG. 29, DRAM 550 includes memory cell array 551, row and column address buffer 552, row decoder 553, and column decoder 55.
4, a sense refresh amplifier 555, a data-in buffer 556, a data-out buffer 557, and a clock generator 558. The memory cell array 551 serves to store a data signal of stored information. The row-and-column address buffer 552 serves to receive an address signal for selecting a memory cell forming a unit memory circuit from the outside. Row decoder 553
The column decoder 554 serves to specify a memory cell by decoding the address signal. The sense refresh amplifier 555 serves to amplify and read the signal stored in the designated memory cell. The data-in buffer 556 and the data-out buffer 557 are
It plays a role of inputting or outputting data. The clock generator 558 serves to generate a clock signal. The memory cell array 551 occupies a large area on the semiconductor chip of the DRAM thus configured. Further, in this memory cell array 551, a plurality of memory cells for accumulating unit storage information are arranged in a matrix.

Next, the memory cells forming the memory cell array 551 will be described. FIG. 30 shows an equivalent circuit diagram of 4 bits of the memory cells forming the memory cell array 551. Referring to FIG. 30, the memory cell is
One MOS (Metal Oxide Semiconductor) transistor 590 and one capacitor 580 connected to this
It consists of and. The gate of the transistor 590 is electrically connected to the word line 560. Also,
Either the source or the drain of the transistor 590 is electrically connected to the bit line 563. A capacitor 580 is connected to the other source or drain of the transistor 590. That is, this memory cell is a one-transistor one-capacitor type memory cell. This type of memory cell has a simple structure and can easily improve the degree of integration of the memory cell array, and is therefore widely used in large capacity DRAMs.

FIG. 31 is a sectional view showing a schematic structure of a conventional one-transistor / one-capacitor type memory cell. Referring to FIG. 31, the memory cell includes one transfer gate transistor 540 and one capacitor 530.

Transfer gate transistor 540
Is composed of a pair of source / drain regions 508, a gate insulating film 509, and gate electrodes 510b and 510c. This transfer gate transistor 54
0 is formed in a region of the silicon substrate 506 isolated by the isolation oxide film 507. The pair of source / drain regions 508 are formed on the surface of the silicon substrate 506 at regular intervals. Gate electrodes 510b, 5
The gate insulating film 10c is formed on the surface of the silicon substrate 1 located between the pair of source / drain regions 508.
It is formed through 09. In addition, the isolation oxide film 507
On the surface of the wiring layers 510a, 5
10d is formed. Gate electrode 510b, 510
A sidewall 511 is formed on the sidewalls of the wiring c and the wiring layers 510a and 510b. Transfer gate transistor 540 and wiring layers 510a and 510d
A thick interlayer insulating film 512 is formed on the surface of the silicon substrate 506 formed with. This interlayer insulating film 51
A nitride film 514 is formed on the surface of No. 2. A contact hole 512a is formed in the interlayer insulating film 512 and the nitride film 514. This contact hole 5
A part of the surface of one source / drain region 508 is exposed from 12a. The capacitor 53 is electrically connected to the exposed source / drain region 508.
0 is formed.

The capacitor 530 is composed of a lower electrode (storage node) 501, a dielectric film 505 and an upper electrode (cell plate) 504. Lower electrode 50
1 is formed in contact with one of the source / drain regions 508 through the contact hole 512a.
The lower electrode 501 is formed so as to be in contact with the surface of the nitride film 514. A dielectric film 505 is formed so as to cover the surface of the lower electrode 501. The upper electrode 504 is formed so as to cover the dielectric film 505 and have a surface facing the surface of the lower electrode 501. The insulating film 51 covers the capacitor 530.
5a is formed. The insulating film 515a and the nitride film 5
14 and the interlayer insulating film 512, the contact hole 5
18 is formed. A part of the surface of the source / drain region 508 is exposed from the contact hole 518. The other exposed source / drain region 50
A bit line 513 is formed on the surface of the insulating film 515a so as to be in contact with the electrode 8. An insulating film 515b is formed so as to cover the bit line 513. This insulating film 51
A wiring layer 516 is formed on the surface of 5b.

As described above, the conventional one-transistor one-capacitor type memory cell is constructed.

[0010]

Generally, the capacitance of a capacitor is proportional to the facing area between electrodes and inversely proportional to the thickness of the dielectric layer. Therefore, from the viewpoint of increasing the capacitance of the capacitor, it is desirable to increase the facing area between the electrodes of the capacitor. On the other hand, when the DRAM is highly integrated, the memory cell size must be reduced. As the memory cell size is reduced, the planar area occupied by the capacitor is also reduced. In the structure of the conventional capacitor, the surface region of the lower electrode facing the upper electrode has a relatively flat shape. Further, the lower electrode has a shape extending in a plane. Therefore, the surface area of the lower electrode is reduced substantially in proportion to the rate of reduction of the plane occupation area. As a result, the facing area between the electrodes of the capacitor is reduced. That is, the amount of charge stored in the capacitor (the amount of charge stored in the 1-bit memory cell) is reduced. If the amount of charge stored in the 1-bit memory cell falls below a certain value, the operation of the DRAM as a storage area becomes unstable, and the reliability decreases. Thus, in the memory cell having the conventional capacitor structure, the DR
There is a problem that it is difficult to achieve high integration of the AM, and if the high integration is promoted, the operation of the DRAM becomes unstable and the reliability deteriorates.

The present invention has been made in order to solve the above-mentioned problems, and a semiconductor having a capacitor having a predetermined capacitance capable of achieving high integration while maintaining stable operation. An object of the present invention is to provide a device and a manufacturing method thereof.

[0012]

The semiconductor device of the present invention comprises:
A substrate, a source / drain region, a gate electrode, and a first
Of the electrode layer, the second electrode layer, the dielectric layer, and the third electrode layer. The source / drain regions and the gate electrode are provided on the substrate. The first electrode layer includes a portion on the upper surface of the substrate and extending along a predetermined plane.
The second electrode layer is in contact with the first electrode layer and includes a portion extending upward from the upper surface of the first electrode layer and a portion extending along a predetermined plane. The dielectric layer covers the surfaces of the first and second electrode layers. The third electrode layer covers the surface of the dielectric layer.

In the method of manufacturing a semiconductor device according to the present invention, the semiconductor device has a source / drain region and a gate electrode provided on the substrate, and includes a portion above the substrate and extending along a predetermined plane. The first electrode layer and the first layer are formed on the surface of the first electrode layer. The conductive layer is formed so as to cover at least a region including the surfaces of the first electrode layer and the first layer. The second layer is formed so as to cover the surface of the conductive layer. By anisotropically etching the second layer, the second layer is left as sidewall spacers on the sidewall of the conductive layer. The conductive layer is etched until the surface of the first layer is exposed under etching conditions such that the etching rate of the second layer is lower than the etching rate of the conductive layer. A second electrode layer is formed by etching the conductive layer. The first and second layers are removed. First
And a dielectric layer is formed so as to cover the surface of the second electrode layer. A third electrode layer is formed so as to cover the surface of the dielectric layer.

[0014]

In the semiconductor device of the present invention, the lower electrode of the capacitor is formed by the first electrode layer and the second electrode layer. Further, the second electrode layer has a portion extending upward from the upper surface of the first electrode layer formed relatively flat. For this reason, the surface area is increased only by the portion extending upward as compared with the conventional capacitor in which the lower electrode is formed of only a relatively flat shape. As a result, it is possible to increase the facing area between the upper electrode and the lower electrode and to increase the capacitance. Further, the surface area of the portion extending upward hardly decreases even when the planar occupation area of the capacitor decreases. . That is, even when high integration is achieved, the capacitance of the capacitor can be ensured by controlling the surface area of the portion protruding vertically upward. As described above, since it is possible to increase or secure the capacitance of the capacitor, it is possible to prevent the operation of the DRAM from becoming unstable and the reliability from being lowered due to high integration.

In the method of manufacturing a semiconductor device of the present invention, the first electrode layer is formed along a predetermined plane.
The first layer is formed on the surface of the first electrode layer. A step is formed by the first electrode layer, the first layer and the predetermined plane. The conductive layer is formed so as to cover a region including the surfaces of the first electrode layer and the first layer. Therefore, a surface step is formed on the surface of the conductive layer due to the step of the lower layer. Second to cover the surface of this conductive layer
Layers are formed. Anisotropic etching is applied to the entire surface of this second layer. As a result, the second layer is left in the shape of a sidewall spacer on the side wall of the surface step portion of the conductive layer.
The conductive layer is etched by using the sidewall spacer-shaped second layer as a mask. By this etching, a second electrode layer is formed which is in contact with the first electrode layer and includes a portion extending upward from the upper surface of the first electrode layer and a portion extending along a predetermined plane. In this way, the second electrode layer is formed in a self-aligned manner using the second layer left in the shape of the sidewall spacer as a mask. Further, the second layer is subjected to anisotropic etching on the entire surface,
It is left in the shape of a sidewall spacer. Therefore, the second
In the step of leaving the layer of as a sidewall spacer,
No mask alignment is required. In this way, highly accurate mask alignment can be omitted in the step of forming the second electrode layer and the step of leaving the second layer in a sidewall shape. This eliminates the need for a mask alignment margin for allowing a mask alignment error. Therefore, it is not necessary to design a pattern with a margin for mask alignment, and it is possible to improve the degree of integration.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows D in the first embodiment of the present invention.
2 is a plan view of a memory cell array of RAM, and FIG.
FIG. 2 is a sectional view taken along line II-II in FIG. 1. First, referring mainly to FIG. 1, word lines 10a, 10b, 10c and 10d, a bit line 13 and memory cells 30 and 40 are formed on the surface of a silicon substrate 6. The plurality of word lines 10a, 10b, 10c, 10d extend parallel to each other in the row direction. Further, the plurality of bit lines 13 extend parallel to each other in the column direction. This word line 10a, 1
A plurality of memory cells 30 and 40 are arranged and formed near the intersections of 0b, 10c and 10d and the bit line 13.

Referring to FIGS. 1 and 2, the memory cell is composed of one transfer gate transistor 40 and one capacitor 30. The transfer gate transistor 40 includes a pair of source / drain regions 8, a gate insulating film 9 and a gate electrode (word line) 1.
It is composed of 0b and 10c. The transfer gate transistor 40 is formed in a region of the silicon substrate 6 separated by the isolation oxide film 7. The pair of source / drain regions 8 are formed on the surface of the silicon substrate 6 with a predetermined gap. Gate electrodes 10b and 10c are formed on the surface of the silicon substrate 7 located between the source / drain regions 8 with a gate insulating film 9 interposed therebetween. On the surface of the isolation oxide film 7, wiring layers 10a and 10d to be word lines are formed. Further, sidewalls 11 are formed on the sidewalls of the gate electrodes 10b and 10c and the wiring layers 10a and 10b. A thick interlayer insulating film 12 is formed on the surface of the silicon substrate 6 so as to cover the transfer gate transistor 40. A buried bit line 13 is formed in the interlayer insulating film 12 so as to contact one of the source / drain regions 8. A silicon nitride film (SiN) 14 is formed on the surface of the interlayer insulating film 12. The contact hole 12a is formed in the interlayer insulating film 12 and the nitride film 14.
Are formed. A part of the surface of the other source / drain region 8 is exposed from the contact hole 12a. Capacitor 30 is formed so as to be electrically connected to the other exposed source / drain region 8.

The capacitor 30 is composed of a lower electrode (storage node) 1, a dielectric film 5 and an upper electrode (cell plate) 4. The lower electrode 1 is composed of a first portion 2 and a second portion 3. The first portion 2 is in contact with the surface of the other source / drain region 8 through the contact hole 12a. The first portion 2 is formed along the surface of the nitride film 14. The second portion 3 is formed on the surface of the nitride film 14 so as to be in contact with the first portion 2. The second portion 3 has a portion extending vertically upward and a portion extending along the surface of the nitride film 14. The portion extending vertically above the second portion 3 is the first
Extends upward from the upper surface of the portion 2. This lower electrode 1
A dielectric film 5 made of a silicon oxide film and a silicon nitride film (ON film) is formed so as to cover the. The upper electrode 4 is formed so as to cover the dielectric film 5. The insulating film 15 is formed so as to cover the capacitor 30.
Are formed. A wiring layer 16 made of aluminum (Al) or the like is formed on the surface of the insulating film 15.

Next, a method of manufacturing the capacitor 30 used in the memory cell shown in FIG. 2 will be described.

3 to 11 are enlarged cross-sectional views showing, in the order of steps, a method of manufacturing a capacitor used in a memory cell according to the first embodiment of the present invention.

First, referring to FIG. 3, an oxide film (SiO ₂ ) 12 is deposited on the surface of silicon substrate 6 by the CVD (Chemical Vapor Depostion) method. This oxide film 12
A nitride film (SiN) 14 is deposited on the surface of the substrate by the CVD method. Openings 12a are formed in the oxide film 12 and the nitride film 14 so that a part of the surface of the silicon substrate 6 is exposed. In addition, on the exposed surface of the silicon substrate 6,
A conductive layer (not shown) such as an impurity region is formed.

Referring to FIG. 4, contact hole 12a
Is formed on the surface of the nitride film 14 with a thickness of 3000 to 8000Å. An oxide film (SiO ₂ ) 21 is deposited on the surface of the polycrystalline silicon film 2 by the CVD method.

Referring to FIG. 5, oxide film 21 is patterned by photolithography and RIE. The polycrystalline silicon film 2 is etched by using the patterned oxide film 21 as a mask. By this etching, the first portion 2 of the lower electrode (storage node) is
Is formed.

Referring to FIG. 6, a polycrystalline silicon film 3 having a thickness of 2000 to 4000 Å is formed on the entire surface so as to cover the first portion 2 and the oxide film 21 with the oxide film 21 left. .

Referring to FIG. 7, this polycrystalline silicon film 3
2000 to 5 by the CVD method so as to cover the entire surface of
A high temperature oxide film (SiO ₂ ) 23 is deposited with a thickness of 000Å.

Referring to FIG. 8, high temperature oxide film 23 is anisotropically etched. By this anisotropic etching, sidewalls of the high temperature oxide film 23 are formed in the step portion of the polycrystalline silicon film 3.

Referring to FIG. 9, this sidewall 23
The polycrystalline silicon film 3 is etched by using as a mask. By this etching, second portion 3 of the lower electrode having a portion extending vertically upward with respect to the surface of silicon substrate 6 and a portion extending in the direction along the surface of nitride film 14 is formed. Thus, the lower electrode 1 is formed by the first portion 2 and the second portion 3 made of polycrystalline silicon.

Referring to FIG. 10, wet etching is performed with a hydrofluoric acid-based etching solution. By this etching, the oxide films 21 and 23 on the surface of the lower electrode 1 are formed.
Are removed. During this etching, the nitride film 1
4 serves as an etching stopper. Therefore, the surfaces of the oxide film 12 and the silicon substrate 6 are not attacked by etching.

Referring to FIG. 11, dielectric film 5 made of an ON film is formed on the entire surface of the substrate on which lower electrode 1 is formed. Polycrystalline silicon film 4 is deposited so as to cover this dielectric film 5. This polycrystalline silicon film 4 becomes an upper electrode (cell plate). The lower electrode 1, the upper electrode 4 and the dielectric film 5 form a capacitor 30.

As described above, capacitor 30 in the first embodiment includes second portion 3 in which lower electrode 1 has a portion extending vertically upward and a portion extending in the direction along the surface of nitride film 14. There is. The portion of the second portion 3 extending vertically upward extends above the surface of the first portion 2. Therefore, a large surface area can be secured as compared with the conventional capacitor structure having a relatively flat surface area. As a result, it becomes possible to obtain a large capacitance as compared with the conventional capacitor structure.

In the method of manufacturing the capacitor 30,
The second portion 3 of the lower electrode 1 can be formed in a self-aligned manner (self-aligned). Accordingly, in the manufacturing process of the capacitor 30, mask alignment is performed as shown in FIG.
The opening 12a is formed twice, and the oxide film 21 of FIG. 5 is patterned only twice. Since highly accurate mask alignment can be omitted in this way, the mask alignment margin can be suppressed. Therefore, it is possible to improve the degree of integration. In addition, it is possible to reduce costs.

Next, the DR in the second embodiment of the present invention
The memory cell structure of AM will be described.

FIG. 12 is a cross sectional view schematically showing a memory cell of a DRAM according to the second embodiment of the present invention. Referring to FIG. 12, the memory cell is composed of one transfer gate transistor 140 and one capacitor 130. The transfer gate transistor 140 includes a pair of source / drain regions 108, a gate insulating film 109, and a gate electrode (word line) 110.
b, 110c. The transfer gate transistor 140 is formed in a region isolated by the isolation oxide film 107 of the silicon substrate 106.
On the surface of the silicon substrate 106, a pair of source / drain regions 108 are formed with a predetermined interval. Gate electrodes 110b and 110c are formed on the surface of the silicon substrate 106 located between the source / drain regions 108 with a gate insulating film 109 interposed therebetween. On the surface of the isolation oxide film 107, the wiring layer 1 to be a word line is formed.
10a and 110d are formed. Gate electrode 110
b, 110c and the side walls of the wiring layers 110a, 110d,
The sidewall 111 is formed. An interlayer insulating film 112 is formed so as to cover the transfer gate transistor 140 and the like. A nitride film (SiN) 114 is formed on the surface of the interlayer insulating film 112. A contact hole 112a is formed in the interlayer insulating film 112 and the nitride film 114. A part of the surface of one of the source / drain regions 108 is exposed from the contact hole 112a. The capacitor 101 is formed so as to be electrically connected to the exposed one of the source / drain regions 108.

The capacitor 101 is composed of a lower electrode (storage node) 101, a dielectric film 105 and an upper electrode (cell plate) 104. The lower electrode 101 is composed of a first portion 102, a second portion 103a and a third portion 103b. Lower electrode 10
The first first portion 102 is formed on the surface of the nitride film 114 so as to be in contact with one of the source / drain regions 108 exposed from the contact hole 112a. The second portion 103 is in contact with the side surface of the first portion 102.
a is formed. The second portion 103a has a portion extending vertically upward and a portion extending along the surface of the nitride film 104. In addition, in the flat surface area of the first portion 102, the third portion 103 extends vertically upward.
b is formed. Lower electrode 1 formed in this way
A dielectric film 105 made of an ON film so as to cover the surface of 01.
Are formed. An upper electrode 104 made of polycrystalline silicon is formed so as to cover the dielectric film 105. The insulating film 11 is formed so as to cover the capacitor 130.
5 is formed. A wiring layer 116 made of aluminum (Al) is formed on the surface of the insulating film 115.

Next, a method of manufacturing the capacitor used in the memory cell according to the second embodiment of the present invention will be described.

13 to 20 are enlarged sectional views showing, in the order of steps, a method of manufacturing a capacitor used in a memory cell according to the second embodiment of the present invention.

First, referring to FIG. 13, a silicon substrate 1
An insulating film 112 made of silicon oxide (SiO ₂ ) is deposited on the surface of 06. A nitride film (SiN) 114 is deposited on the surface of the insulating film 112 by the CVD method. The insulating film 112 and the nitride film 114 are
The contact hole 112a is formed by the photolithography method and the RIE method. This contact hole 11
A part of the surface of the silicon substrate 106 is exposed from 2a. A conductive layer (not shown) such as an impurity region is formed on the exposed surface of the silicon substrate 106.
A polycrystalline silicon film 102 is deposited on the surface of the nitride film 114 so as to fill the contact hole 112a. Further, an oxide film (SiO ₂ ) 121 is deposited on the surface of the polycrystalline silicon film 102 by the CVD method.

Referring to FIG. 14, oxide film 121 is patterned by the photolithography method and the RIE method. The polycrystalline silicon film 102 is etched by using the patterned oxide film 121 as a mask. This etching forms the first portion 102 of the lower electrode.

Referring to FIG. 15, oxide film 121 is etched by photolithography and RIE.
By this etching, the oxide film 121 is removed from the first portion 1
02 on the surface and only its sides are left.

Referring to FIG. 16, the polycrystalline silicon film 103 is left in a state of 2000 to 4000 with the oxide film 121 left.
It is deposited with a thickness of Å. A high temperature oxide film (SiO 2) is formed by a CVD method so as to cover the surface of the polycrystalline silicon film 103.
₂ ) 123 is deposited to a thickness of 2000-5000Å.

Referring to FIG. 17, high temperature oxide film 123 is anisotropically etched. As a result, the side wall 123 of the high temperature oxide film is formed on the step portion of the polycrystalline silicon film 103.

Referring to FIG. 18, polycrystalline silicon film 1 is formed using sidewall 123 made of a high temperature oxide film as a mask.
03 is etched. By this etching,
A second portion 103a having a portion extending vertically upward and a portion extending in a direction along the surface of nitride film 114 is formed. A third portion 103b having a portion extending vertically upward is also formed on the surface region of the first portion 102. The first electrode 102, the second portion 103a, and the third portion 103b form the lower electrode 101.

Referring to FIG. 19, wet etching is performed with a hydrofluoric acid-based etching solution. By this etching, the oxide film 121 on the surface of the lower electrode 101,
123 is removed. Further, during this etching, the nitride film 114 serves as an etching stopper. Therefore, the surfaces of the oxide film 112 and the silicon substrate 106 are not attacked by etching.

Referring to FIG. 20, a dielectric film 105 made of silicon nitride (SiN) is deposited so as to cover the entire surface of the lower electrode 101. The upper electrode 10 made of polycrystalline silicon so as to cover the entire surface of the dielectric film 105.
4 are deposited. The lower electrode 101 and the dielectric film 105
And the upper electrode 104 constitutes the capacitor 130.

As described above, in the capacitor 130 according to the second embodiment of the present invention, the lower electrode 101 includes the first portion 102, the second portion 103a, and the third portion 10.
3b. Thus, the second portion 10
In addition to 3a, a third portion 103b having a portion extending so as to project vertically upward is formed. Therefore, it is possible to secure a large surface area as compared with the first embodiment. Therefore, the capacitance of the capacitor 130 is
It can be made larger than the capacitance of the capacitor 30 in the first embodiment.

In the method of manufacturing the capacitor 130, the second and third portions 103 included in the lower electrode 101 are also included.
It is possible to form a and 103b in a self-aligned manner. Therefore, it is possible to form the capacitor 130 with less mask alignment as in the first embodiment. Therefore, a mask alignment margin is not required, and the degree of integration can be improved.

In the second embodiment, the third portion 103b forming the lower electrode 101 is the second portion 10.
Although the structure formed inside 3a is shown, as in the third embodiment shown in FIG. 21, the third part 203b is formed outside the second part 203a forming the lower electrode 201. Good. As a result, in the capacitor 230 including the lower electrode 201, the dielectric film 205 and the upper electrode 204, the lower electrode 201 that contributes to the capacitance.
Surface area is increased. Therefore, it is possible to increase the capacity of the capacitor 230. Note that the reference numerals attached to FIG. 21 are indicated by the reference numerals corresponding to FIG.

The present invention is not limited to the structures shown in the second and third embodiments, but may be a structure in which a large number of vertically projecting portions are formed. This makes it possible to further increase the capacity.

Next, the DR in the fourth embodiment of the present invention
The configuration of the AM memory cell will be described.

FIG. 22 is a cross sectional view schematically showing a memory cell of a DRAM according to the fourth embodiment of the present invention. With reference to FIG. 22, the memory cell is composed of one transfer gate transistor 340 and one capacitor 330. The transfer gate transistor 340 includes a pair of source / drain regions 308, a gate insulating film 309, and a gate electrode (word line) 310b.
And 310c. The transfer gate transistor 340 is formed in a region isolated by the isolation oxide film 307 of the silicon substrate 306. On the surface of the silicon substrate 306, a pair of source / drain regions 308 are formed with a predetermined interval. Silicon substrate 3 located between the pair of source / drain regions
Gate electrodes 310b and 310c are formed on the surface of 06 via a gate insulating film 309. Isolation oxide film 3
On the surface of 07, a wiring layer 310a to be a word line is formed.
And 310d are formed. Gate electrode 310
Side walls 311 made of silicon oxide (SiO ₂ ) are formed on the side walls of b, 310c and the wiring layers 310a, 310d. The interlayer insulating film 3 made of silicon oxide (SiO ₂ ) so as to cover the transfer gate transistor 340 and the wiring layer 310a.
12 are formed. A nitride film (SiN) 314 is formed on the surface of the interlayer insulating film 312. In the interlayer insulating film 312, the buried bit line 3 is electrically connected to one of the source / drain regions 308.
13 is formed. Interlayer insulating film 312 and nitride film 31
4, a contact hole 312a is formed.
A part of the surface of the other source / drain region 308 forming the transfer gate transistor 340 is exposed from the contact hole 312a. A capacitor 330 is formed so as to be electrically connected to the other source / drain region 308.

The capacitor 330 is composed of a lower electrode (storage node) 301, a dielectric film 305 and an upper electrode (cell plate) 304. In addition, the lower electrode 301 includes a first portion 302 and a second portion 303.
It consists of and. First part 3 of the lower electrode 301
02 is in contact with the exposed portion of the other source / drain region through the contact hole 312a. Also, the first
The second portion 303 is formed so as to contact the side portion of the portion 302. The second portion 303 has a portion extending vertically upward and a portion extending in a direction along the surface of the nitride film 314. A dielectric film 305 is formed so as to cover the entire surface of the lower electrode 301. The dielectric film 305 is formed so as to also extend around the lower surface of the lower electrode 301. An upper electrode 304 is formed so as to cover the entire surface of this dielectric film 305. The upper electrode 304 is also formed so as to wrap around the lower side of the lower electrode 301. The capacitor 33 thus formed
An insulating film 315 is formed so as to cover 0. A plurality of wiring layers 316 made of aluminum (Al) or the like are formed on the surface of the insulating film 315.

Next, a method of manufacturing the capacitor used in the memory cell according to the fourth embodiment of the present invention will be described.

23 to 25 are enlarged sectional views showing, in the order of steps, a method of manufacturing a capacitor used in a memory cell according to the fourth embodiment of the present invention.

First, with reference to FIG. 23, a silicon substrate 30.
On the surface of 6, the silicon oxide (Si
An insulating film 312 of O ₂ ) is deposited. A nitride film (SiN) is formed on the surface of the insulating film 312 by the CVD method.
314 is deposited. An oxide film (SiO ₂ ) 325 is formed on the surface of the nitride film 314 by the CVD method. A contact hole 312a is formed in the insulating film 312, the nitride film 314, and the oxide film 325.
From this contact hole 312a, the silicon substrate 3
A part of the surface of 06 is exposed. A conductive layer (not shown) such as an impurity region is formed on the exposed surface of the silicon substrate 306.

Referring to FIG. 24, polycrystalline silicon film 302 is deposited on the surface of oxide film 325 so as to fill contact hole 312a. On the surface of this polycrystalline silicon film 302, an oxide film (Si
O ₂ ) 321 is deposited. The oxide film 321 is patterned by the photolithography method and the RIE method. The polycrystalline silicon film 302 is etched by using the patterned oxide film 321 as a mask. This etching forms the first portion 302 of the lower electrode. Next, with the oxide film 321 left, a polycrystalline silicon film 303 is deposited on the entire surface so as to cover the first portion 302 and the oxide film 321. This polycrystalline silicon film 30
Oxide film (SiO ₂ ) 32 on the entire surface of No. 3 by the CVD method.
3 are deposited. This oxide film 323 is anisotropically etched. By this etching, sidewalls made of the high temperature oxide film 323 are formed in the step portions of the polycrystalline silicon film 303. Using this sidewall 323 as a mask, the polycrystalline silicon film 303 is removed by etching. As a result, the second portion 303 of the lower electrode is formed. In this way, the first electrode forming the lower electrode 301 is formed.
Part 302 and the second part 303 are formed. In addition,
Second portion 303 has a portion that is in contact with first portion 302 and extends vertically upward, and a portion that extends in a direction along the surface of oxide film 325.

Referring to FIG. 25, wet etching is performed with a hydrofluoric acid-based etching solution. By this etching, the oxide film 325 on the surface of the nitride film 314 is formed.
And oxide films 321 and 323 on the surface of the lower electrode 301.
Are removed. At the time of this etching, the nitride film 314 serves as an etching stopper. Therefore, the insulating film 31
2 and the surface of the silicon substrate 306 are not attacked by etching. Next, a dielectric film 305 is formed so as to cover the entire surface of the lower electrode 301. A polycrystalline silicon film 304 is formed so as to cover the entire surface of this dielectric film 305. From the lower electrode 301, the dielectric film 305 and the upper electrode 304, the capacitor 330
Is configured.

In the structure of the capacitor 330 according to the fourth embodiment as described above, the lower surface of the lower electrode 301 also contributes to the capacitance of the capacitor. Therefore, it is possible to further increase the capacitance as compared with the capacitance of the capacitor in the first embodiment.

In the fourth embodiment, the upper electrode 304 is formed so as to wrap around the lower surface of the lower electrode 301. However, in the present invention, the shape of the lower electrode 301 is not limited to the shape shown in the fourth embodiment, and the first portion 4 as in the fifth embodiment shown in FIG.
02, the second portion 403a, and the third portion 403b, the lower electrode 401 may have the same shape as the lower electrode in the second embodiment.

Further, it is sufficient that the portion protruding vertically upward has a plurality of rows. This makes it possible to further increase the capacity.

Further, as shown in FIG. 27, the contact hole 12a may be filled with a tungsten (W) plug 17. The reference numerals shown in FIG. 27 are shown by the reference numerals corresponding to those shown in FIG. 11.

In addition, as shown in FIG. 28, a bit line electrically connected to one source / drain region 8 of the transfer gate transistor 40 is formed in the interlayer insulating film 12, the nitride film 14 and the insulating film 15a. The contact hole 18 may be formed through the contact hole 18.
Note that the reference numerals in FIG. 28 correspond to the reference numerals shown in FIG.

[0063]

In the semiconductor device of the present invention, the lower electrode of the capacitor includes the first electrode layer and the second electrode layer. The second electrode layer has a portion extending upward from the upper surface of the first electrode layer formed relatively flat. Therefore, the surface area of the portion extending upward is increased as compared with the conventional capacitor in which the lower electrode has only a relatively flat shape. As a result, the area where the lower electrode and the upper electrode face each other between electrodes is increased, and the capacitance can be increased. Further, the surface area of the portion extending vertically upward is hardly reduced even when the planar occupation area of the capacitor is reduced. That is, even when high integration is achieved, the capacitance of the capacitor can be secured by controlling the surface area of the portion protruding vertically upward. As described above, since the capacity of the capacitor can be increased or ensured, it is possible to prevent the operation of the DRAM from becoming unstable and the reliability from being deteriorated due to high integration.

In the method of manufacturing a semiconductor device of the present invention, the second electrode layer is formed in a self-aligned manner using the second layer left in the shape of the sidewall spacer as a mask. Further, the second layer is left in a sidewall spacer shape by anisotropically etching the entire surface. Therefore, mask alignment is not necessary in the step of leaving the second layer in the shape of the sidewall spacer. Thus, the second
In the step of forming the electrode layer and the step of leaving the second layer in a sidewall shape, highly accurate mask alignment can be omitted. This eliminates the need for a mask alignment margin for allowing a mask alignment error. Therefore, it is not necessary to design a pattern with a margin for mask alignment, and it is possible to improve the degree of integration.

[Brief description of drawings]

FIG. 1 is a plan structural view of a memory cell array of a DRAM according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along the line II-II in FIG. 1 showing a schematic configuration of a memory cell of a DRAM according to the first embodiment of the present invention.

FIG. 3 is an enlarged cross-sectional view schematically showing a first step of the method of manufacturing the capacitor adopted in the memory cell according to the first embodiment of the present invention.

FIG. 4 is an enlarged cross-sectional view schematically showing a second step of the method of manufacturing the capacitor adopted in the memory cell according to the first embodiment of the present invention.

FIG. 5 is an enlarged cross-sectional view schematically showing a third step of the method for manufacturing the capacitor adopted in the memory cell according to the first embodiment of the present invention.

FIG. 6 is an enlarged cross-sectional view schematically showing a fourth step of the method for manufacturing the capacitor adopted in the memory cell according to the first embodiment of the present invention.

FIG. 7 is an enlarged cross-sectional view schematically showing a fifth step of the method for manufacturing the capacitor adopted in the memory cell according to the first embodiment of the present invention.

FIG. 8 is an enlarged cross-sectional view schematically showing a sixth step of the method for manufacturing the capacitor employed in the memory cell according to the first embodiment of the present invention.

FIG. 9 is an enlarged cross-sectional view schematically showing a seventh step of the method for manufacturing the capacitor adopted in the memory cell according to the first embodiment of the present invention.

FIG. 10 is an enlarged cross-sectional view schematically showing an eighth step of the method for manufacturing the capacitor adopted in the memory cell according to the first embodiment of the present invention.

FIG. 11 is an enlarged cross-sectional view schematically showing a ninth step of the method for manufacturing the capacitor employed in the memory cell according to the first embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a schematic configuration of a memory cell of a DRAM according to a second embodiment of the present invention.

FIG. 13 is an enlarged cross-sectional view schematically showing a first step of a method of manufacturing a capacitor adopted in a memory cell according to the second embodiment of the present invention.

FIG. 14 is an enlarged cross-sectional view schematically showing a second step of the method of manufacturing the capacitor adopted in the memory cell according to the second embodiment of the present invention.

FIG. 15 is an enlarged cross sectional view schematically showing a third step of the method for manufacturing the capacitor adopted in the memory cell in the second example of the present invention.

FIG. 16 is an enlarged cross-sectional view schematically showing a fourth step of the method for manufacturing the capacitor adopted in the memory cell according to the second embodiment of the present invention.

FIG. 17 is an enlarged cross sectional view schematically showing a fifth step of the method for manufacturing the capacitor adopted in the memory cell in the second example of the present invention.

FIG. 18 is an enlarged cross sectional view schematically showing a sixth step of the method for manufacturing the capacitor adopted in the memory cell in the second example of the present invention.

FIG. 19 is an enlarged cross sectional view schematically showing a seventh step of the method for manufacturing the capacitor adopted in the memory cell in the second example of the present invention.

FIG. 20 is an enlarged cross-sectional view schematically showing an eighth step of the method for manufacturing the capacitor adopted in the memory cell according to the second embodiment of the present invention.

FIG. 21 is an enlarged cross-sectional view showing a schematic configuration of a capacitor used in a memory cell according to a third embodiment of the present invention.

FIG. 22 is a sectional view showing a schematic configuration of a memory cell of a DRAM according to a fourth embodiment of the present invention.

FIG. 23 is an enlarged cross sectional view schematically showing a first step of the method for manufacturing the capacitor adopted in the memory cell in the fourth example of the present invention.

FIG. 24 is an enlarged cross sectional view schematically showing a second step of the method for manufacturing the capacitor adopted in the memory cell in the fourth example of the present invention.

FIG. 25 is an enlarged cross sectional view schematically showing a third step of the method for manufacturing the capacitor adopted in the memory cell in the fourth example of the present invention.

FIG. 26 is an enlarged cross-sectional view showing a schematic configuration of a capacitor used in a memory cell according to a fifth embodiment of the present invention.

FIG. 27 is an enlarged cross-sectional view showing a state where a tungsten plug is used together with the capacitor of the present invention.

FIG. 28 is a cross sectional view schematically showing a state in which bit lines are formed from the upper layer in the memory cell of the DRAM in the first embodiment of the present invention.

FIG. 29 is a block diagram showing a configuration of a general DRAM.

FIG. 30 is a view showing four memory cells which form a memory cell array.
It is a figure which shows the equivalent circuit schematic for bits.

FIG. 31 is a cross-sectional view schematically showing a memory cell of a conventional DRAM.

[Explanation of symbols]

1, 101, 201, 301, 401 Lower electrode 2, 102, 202, 302, 402 First portion 3, 103a, 203a, 303, 403a Second portion 103b, 203b, 403b Third portion 4, 104, 204, 304, 404 Upper electrode 5, 105, 205, 305, 405 Dielectric film

Claims (2)

[Claims] 1. A substrate, a source / drain region and a gate electrode provided on the substrate, a first electrode layer including an upper portion of the substrate extending along a predetermined plane, and A second electrode layer that is in contact with the first electrode layer and includes a portion that extends above the upper surface of the first electrode layer and a portion that extends along the predetermined plane; and the first and second electrodes A dielectric layer covering the surface of the layer, and a third electrode layer covering the surface of the dielectric layer,
Semiconductor device. 2. A first electrode layer having a substrate, a source / drain region and a gate electrode provided on the substrate, the first electrode layer including an upper portion of the substrate and extending along a predetermined plane. Forming a first layer on the surface of the first electrode layer, and forming a conductive layer so as to cover at least a region including the surfaces of the first electrode layer and the first layer. And a step of forming a second layer so as to cover the surface of the conductive layer, and anisotropically etching the second layer to form a sidewall spacer on the sidewall of the conductive layer. Leaving the second layer, and etching the conductive layer under etching conditions such that the etching rate of the second layer is lower than the etching rate of the conductive layer until the surface of the first layer is exposed. To form the second electrode layer. A step of removing the first and second layers, a step of forming a dielectric layer so as to cover the surfaces of the first and second electrode layers, and a step of covering the surface of the dielectric layer. And a step of forming a third electrode layer on the substrate.