JPH06295995A

JPH06295995A - Semiconductor device and its manufacture

Info

Publication number: JPH06295995A
Application number: JP6015226A
Authority: JP
Inventors: Tomofumi Shono; 朋文庄野; Akira Asai; 明浅井; Masanori Fukumoto; 正紀福本
Original assignee: Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Holdings Corp
Priority date: 1993-02-12
Filing date: 1994-02-09
Publication date: 1994-10-21
Anticipated expiration: 2018-01-07
Also published as: JP3361377B2

Abstract

PURPOSE:To prevent increase of contact resistance and imperfect connection of contact part material with the drain region and the source region of a semiconductor element of a semiconductor device. CONSTITUTION:The surface region of a P-type semiconductor substrate 1 is divided into a plurality of active regions Rac by element isolation in which regions semiconductor elements like DRAM's are formed. In each active region Rac, a first diffusion region like a drain region 2, a second diffusion region like a source region 3, and wiring members like word lines are formed, and the surfaces of word lines are covered with a first insulating film 12. A second insulating film 12 is formed wherein a region just above the first diffusion region is left and a region Ret containing commonly at least two regions just above diffusion regions is eliminated. A conductive part member like a capacitive storage electrode 13 is arranged above the second diffusion region. A contact part member like a capacitive storage electrode contact 11 is formed in the self-alighment manner via the region Ret wherein the second insulating film 12 is eliminated. Thereby increase of contact resistance and imperfect connection can be prevented.

Description

Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、ＤＲＡＭメモリセル等
の半導体素子を備えた半導体装置及びその製造方法に係
り、特に、容量蓄積電極コンタクト，ビット線コンタク
ト等のコンタクト抵抗の増大防止対策に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a semiconductor element such as a DRAM memory cell and a method for manufacturing the same, and more particularly to measures for preventing an increase in contact resistance such as a capacitance storage electrode contact and a bit line contact.

【０００２】[0002]

【従来の技術】近年、半導体装置には高密度化が要求さ
れてきており、搭載される半導体素子の寸法もごく微細
なものになっている。このため、半導体素子に配線を接
続するコンタクト部材の寸法やコンタクト部材と素子の
重ね合わせ寸法は非常に小さくなる傾向にある。2. Description of the Related Art In recent years, there has been a demand for higher density semiconductor devices, and the dimensions of mounted semiconductor elements have become extremely fine. Therefore, the size of the contact member for connecting the wiring to the semiconductor element and the overlapping size of the contact member and the element tend to be very small.

【０００３】以下、図面を参照しながら、従来の半導体
装置の例について説明する。図１４（ａ）は、従来のス
タック型キャパシタセルを用いたＤＲＡＭのメモリセル
アレイの平面図であり、図１４（ｂ）はその一部を拡大
した平面図である。図１５は、図１４（ａ）のXV−XV線
における断面図である。図１４（ａ）及び図１５に示す
ように、Ｐ型半導体基板１の表面領域は、素子分離４に
より複数の活性領域Ｒacに区画されている。各活性領域
Ｒacには、ＤＲＡＭメモリセルを構成するスイッチング
トランジスタ８が形成されている。各スイッチングトラ
ンジスタ８には、不純物がドープされた２つの拡散領域
つまりドレイン領域２とソース領域３とが形成されてい
る。そして、各スイッチングトランジスタ８のソース−
ドレイン間つまりチャネル領域の上方には、チャネル電
流を制御するためのゲート電極７がゲート酸化膜６を介
して設けられている。また、素子分離４上と活性領域Ｒ
ac上とに跨って、各スイッチングトランジスタ８のゲー
ト電極７を接続するワード線５が形成されている。ワー
ド線５は、図１４（ａ）の平面図の縦方向に隣接するス
イッチングトランジスタ８を接続する線状に形成されて
いる。An example of a conventional semiconductor device will be described below with reference to the drawings. FIG. 14A is a plan view of a memory cell array of a DRAM using a conventional stack-type capacitor cell, and FIG. 14B is a partially enlarged plan view thereof. FIG. 15 is a sectional view taken along line XV-XV in FIG. As shown in FIGS. 14A and 15, the surface region of the P-type semiconductor substrate 1 is divided into a plurality of active regions Rac by the element isolation 4. A switching transistor 8 forming a DRAM memory cell is formed in each active region Rac. In each switching transistor 8, two diffusion regions doped with impurities, that is, a drain region 2 and a source region 3 are formed. The source of each switching transistor 8
A gate electrode 7 for controlling a channel current is provided between the drains, that is, above the channel region via a gate oxide film 6. In addition, on the element isolation 4 and the active region R
A word line 5 that connects the gate electrode 7 of each switching transistor 8 is formed over and above ac. The word line 5 is formed in a linear shape that connects vertically adjacent switching transistors 8 in the plan view of FIG.

【０００４】図１５の断面図において、上記ワード線５
は、便宜上、素子分離４の上ではワード線５として表示
され、活性領域Ｒacの上ではゲート電極７として表示さ
れている。各ゲート電極７の側部及び上面は、サイドウ
ォール９ａ及び上面保護膜９ｂからなる第１絶縁膜９で
被覆されており、いわゆるＬＤＤ構造となっている。し
たがって、詳細は省略するが、ドレイン領域２及びソー
ス領域３は、いずれも高濃度領域と低濃度領域とを有し
ている。ドレイン領域２の上には第２絶縁膜１２が形成
されており、この第２絶縁膜１２は、メモリセルアレイ
部の全面に堆積された後、パターニングされたものであ
り、図１４（ｂ）に拡大して示すように、各スイッチン
グトランジスタ８のソース領域３に該当する部分が除去
されている。つまり、図１５の断面図に示すように、第
２絶縁膜１２は、素子分離４に隣接する部分を除くソー
ス領域３の一部の直上領域とその周辺の第１絶縁膜９の
直上領域とを含む領域が除去されており、以下ではこの
領域を除去領域Ｒetということにする。上記第２絶縁膜
１２の上には容量蓄積電極１３が形成されている。さら
に、この容量蓄積電極１３を被覆する容量絶縁膜１４が
形成され、容量絶縁膜１４の上にプレート電極１５が形
成されている。図１４（ｂ）に示すように、ドットを施
した領域が容量蓄積電極１３とソース領域３とを接続す
る容量蓄積電極コンタクト１１の形成領域であり、通
常、この容量蓄積電極コンタクト１１の寸法とソース領
域３の寸法との間には、フォトマスクのずれを考慮し
て、マージン１６が設定されている。In the sectional view of FIG. 15, the word line 5 is used.
Are shown as word lines 5 on the element isolation 4 and as gate electrodes 7 on the active region Rac for convenience. The side surface and the upper surface of each gate electrode 7 are covered with the first insulating film 9 including the sidewall 9a and the upper surface protection film 9b, and have a so-called LDD structure. Therefore, although not described in detail, the drain region 2 and the source region 3 each have a high concentration region and a low concentration region. A second insulating film 12 is formed on the drain region 2, and the second insulating film 12 is deposited on the entire surface of the memory cell array portion and then patterned, as shown in FIG. As shown in an enlarged view, the portion corresponding to the source region 3 of each switching transistor 8 is removed. That is, as shown in the cross-sectional view of FIG. 15, the second insulating film 12 includes a region immediately above the part of the source region 3 excluding a portion adjacent to the element isolation 4 and a region immediately above the first insulating film 9 in the periphery thereof. The region including is removed, and this region will be referred to as a removal region Ret in the following. A capacitance storage electrode 13 is formed on the second insulating film 12. Further, a capacitance insulating film 14 that covers the capacitance storage electrode 13 is formed, and a plate electrode 15 is formed on the capacitance insulating film 14. As shown in FIG. 14 (b), the dotted region is the region where the capacitance storage electrode contact 11 that connects the capacitance storage electrode 13 and the source region 3 is formed. A margin 16 is set between the dimension of the source region 3 and the shift of the photomask.

【０００５】[0005]

【発明が解決しようとする課題】しかしながら、上記従
来のような半導体装置では下記のような問題があった。
図１６は、フォトリソグラフィー工程におけるずれを説
明する図であって、図１４（ｂ）に相当する部分におい
て、スイッチングトランジスタ８の各部を形成するため
のマスクと第２絶縁膜１２をパターニングするマスクと
の位置ずれが生じたときの状態を示す図である。すなわ
ち、除去領域Ｒetの端部とソース領域３の端部とのマー
ジン１６は０．０５［μｍ］と非常に小さいが、現在の
フォトリソグラフィー技術における上下のパターン重ね
合わせ精度では、除去領域Ｒetを正確な位置に形成する
ことは難しい。このため、図１６に示すように、除去領
域Ｒetが、上記マージン１６以上に上方又は下方にへシ
フトすることがある。また、このマスクの位置ずれに加
えて、除去領域Ｒetの寸法は、例えば１．１［μｍ］×
０．５［μｍ］程度と小さいため、フォトリソグラフィ
ー工程で解像度が不足してレジストパターンのテール引
きが発生し、エッチング工程で、レジストパターンのこ
のテールを引いた部分が不規則に後退して、容量蓄積電
極コンタクト１１の寸法が安定しないという傾向もあっ
た。However, the above-mentioned conventional semiconductor device has the following problems.
FIG. 16 is a diagram for explaining a shift in the photolithography process, in which a mask for forming each part of the switching transistor 8 and a mask for patterning the second insulating film 12 are formed in a part corresponding to FIG. 14B. It is a figure which shows the state when the position shift of occurs. That is, the margin 16 between the end of the removal region Ret and the end of the source region 3 is as small as 0.05 [μm], but with the upper and lower pattern overlay accuracy in the current photolithography technology, the removal region Ret It is difficult to form in the correct position. Therefore, as shown in FIG. 16, the removal region Ret may shift upward or downward beyond the margin 16. In addition to the displacement of the mask, the size of the removal region Ret is, for example, 1.1 [μm] ×
Since the size is as small as 0.5 [μm], the resolution is insufficient in the photolithography process, and the tail patterning of the resist pattern occurs. In the etching process, the tailed part of the resist pattern retreats irregularly, There was also a tendency that the dimensions of the capacitance storage electrode contact 11 were not stable.

【０００６】以上のような原因により、容量蓄積電極コ
ンタクト１１の面積が減少すると、コンタクト抵抗値が
増加したり、接続不良を来たす虞れがあった。If the area of the capacitance storage electrode contact 11 is reduced due to the above reasons, there is a possibility that the contact resistance value may increase or a connection failure may occur.

【０００７】本発明は、上記問題点に鑑み、フォトリソ
グラフィー工程におけるマスクの位置ずれやレジストパ
ターンのテール引きに起因するコンタクト不良を防止す
ることを目的としている。In view of the above problems, it is an object of the present invention to prevent a contact failure due to the displacement of the mask or the tail pulling of the resist pattern in the photolithography process.

【０００８】[0008]

【課題を解決するための手段】上記目的達成するため、
請求項１の発明の講じた手段は、半導体装置として、半
導体基板と、上記半導体基板上に形成され、半導体基板
の表面領域を半導体素子が形成される複数の活性領域に
区画する分離絶縁膜と、上記半導体基板の上記各活性領
域に形成され、半導体基板の表面領域に不純物が拡散さ
れてなる第１拡散領域及び第２拡散領域と、上記活性領
域の半導体基板上に設けられた配線部材と、上記配線部
材の表面を被覆する第１絶縁膜と、上記半導体基板，分
離絶縁膜及び第１絶縁膜の上に設けられ、上記第１拡散
領域の直上領域のうちの少なくとも一部が残存し、少な
くとも２つの第２拡散領域の直上領域を共通に含む領域
が除去された第２絶縁膜と、上記第２拡散領域の上方に
設けられた導電性部材と、上記第２絶縁膜が除去された
領域の少なくとも一部を介し、上記導電性部材と第２拡
散領域とを接続するコンタクト部材とを設ける構成とし
たものである。[Means for Solving the Problems] To achieve the above object,
According to another aspect of the present invention, a semiconductor device is provided as a semiconductor device, and an isolation insulating film formed on the semiconductor substrate and partitioning a surface region of the semiconductor substrate into a plurality of active regions in which semiconductor elements are formed. A first diffusion region and a second diffusion region formed in each active region of the semiconductor substrate and having impurities diffused in a surface region of the semiconductor substrate; and a wiring member provided on the semiconductor substrate in the active region. Provided on the first insulating film that covers the surface of the wiring member, the semiconductor substrate, the isolation insulating film, and the first insulating film, and at least a part of the region immediately above the first diffusion region remains. , A second insulating film from which a region commonly including a region immediately above at least two second diffusion regions is removed, a conductive member provided above the second diffusion region, and the second insulating film is removed. At least in the area Through the parts is obtained by a configuration in which a contact member for connecting the conductive member and the second diffusion region.

【０００９】請求項２の発明の講じた手段は、請求項１
の発明において、上記半導体基板の各活性領域にＤＲＡ
Ｍメモリセルを配設し、上記配線部材を上記ＤＲＡＭメ
モリセルのワード線とし、上記第１拡散領域をＤＲＡＭ
メモリセルのドレイン領域とし、上記第２拡散領域をＤ
ＲＡＭメモリセルのソース領域とし、上記導電性部材を
容量蓄積電極とし、上記コンタクト部材を上記容量蓄積
電極とソース領域とを接続する容量蓄積電極コンタクト
としたものである。The means taken by the invention of claim 2 is defined by claim 1.
In the invention, the DRA is provided in each active region of the semiconductor substrate.
M memory cells are arranged, the wiring member is used as a word line of the DRAM memory cell, and the first diffusion region is DRAM.
The second diffusion region is used as the drain region of the memory cell.
A source region of the RAM memory cell, the conductive member as a capacitance storage electrode, and the contact member as a capacitance storage electrode contact connecting the capacitance storage electrode and the source region.

【００１０】請求項３の発明の講じた手段は、請求項２
の発明において、上記第２絶縁膜が除去された領域が、
ワード線にほぼ平行な方向に配置された複数のソース領
域の直上領域を共通に含むように構成したものである。The means taken by the invention of claim 3 is the method of claim 2
In the invention of claim 1, the region where the second insulating film is removed is
It is configured so as to commonly include a region immediately above a plurality of source regions arranged in a direction substantially parallel to the word line.

【００１１】請求項４の発明の講じた手段は、請求項２
の発明において、上記第２絶縁膜が除去された領域が、
ワード線にほぼ直交する方向に配置された複数のソース
領域の直上領域を共通に含むように構成したものであ
る。The means taken by the invention of claim 4 is the method of claim 2.
In the invention of claim 1, the region where the second insulating film is removed is
It is configured so as to commonly include a region directly above a plurality of source regions arranged in a direction substantially orthogonal to the word line.

【００１２】請求項５の発明の講じた手段は、請求項２
の発明において、上記第２絶縁膜が除去された領域が、
ＤＲＡＭメモリセル内のすべてのソース領域の直上領域
を共通に含むように構成したものである。The means taken by the invention of claim 5 is the method of claim 2.
In the invention of claim 1, the region where the second insulating film is removed is
The structure is such that the region directly above all the source regions in the DRAM memory cell is commonly included.

【００１３】請求項６の発明の講じた手段は、請求項
２，３，４又は５の発明において、上記容量蓄積電極の
上方に配置されたビット線と、上記ドレイン領域の上を
被覆する第２絶縁膜の一部を貫通して、上記ビット線と
ドレイン領域とを接続するビット線コンタクトとを設け
る構成としたものである。According to a sixth aspect of the present invention, in the means of the second, third, fourth or fifth aspect of the present invention, the bit line disposed above the capacitance storage electrode and the drain region are covered. The bit line contact that connects the bit line and the drain region is provided by penetrating a part of the insulating film.

【００１４】請求項７の発明の講じた手段は、請求項１
の発明において、上記半導体基板の各活性領域に、電界
効果型トランジスタを配設し、上記配線部材を上記電界
効果型トランジスタのゲート電極とし、上記第１拡散領
域を電界効果型トランジスタのソース領域とし、上記第
２拡散領域を電界効果型トランジスタのドレイン領域と
し、上記導電性部材をビット線とし、上記コンタクト部
材を上記ビット線と上記電界効果型トランジスタのドレ
イン領域とを接続するビット線コンタクトとしたもので
ある。The means taken by the invention of claim 7 is the method of claim 1.
In the invention, a field effect transistor is provided in each active region of the semiconductor substrate, the wiring member serves as a gate electrode of the field effect transistor, and the first diffusion region serves as a source region of the field effect transistor. , The second diffusion region is a drain region of the field effect transistor, the conductive member is a bit line, and the contact member is a bit line contact connecting the bit line and the drain region of the field effect transistor. It is a thing.

【００１５】請求項８の発明の講じた手段は、請求項７
の発明において、上記第２絶縁膜が除去された領域が、
ゲート電極を構成する配線部材に平行な方向に配置され
た複数のドレイン領域の直上領域を共通に含むように構
成したものである。The means taken by the invention of claim 8 is claim 7
In the invention of claim 1, the region where the second insulating film is removed is
It is configured so as to commonly include a region immediately above a plurality of drain regions arranged in a direction parallel to the wiring member forming the gate electrode.

【００１６】請求項９の発明の講じた手段は、半導体装
置の構成として、半導体基板と、上記半導体基板上に形
成され、半導体基板の表面領域を半導体素子が形成され
る複数の活性領域に区画する分離絶縁膜と、上記半導体
基板の上記各活性領域に形成され、基板の表面領域に不
純物が拡散されてなる第１拡散領域及び第２拡散領域
と、上記活性領域の半導体基板上に設けられた配線部材
と、上記配線部材の表面を被覆する第１絶縁膜と、上記
半導体基板，第１絶縁膜及び分離絶縁膜の上に形成さ
れ、少なくとも２つの第２拡散領域の直上領域を共通に
含む領域が除去され、かつ上記第１拡散領域の直上領域
のうちの少なくとも一部が孤立して残存する平面パター
ンを有する第２絶縁膜と、上記第２拡散領域の上方に設
けられた導電性部材と、上記第２絶縁膜が除去された領
域のうちの少なくとも一部を介し、上記導電性部材と第
２拡散領域とを接続するコンタクト部材とを設ける構成
としたものである。According to a ninth aspect of the present invention, a semiconductor device has a structure in which a semiconductor substrate and a surface region of the semiconductor substrate are divided into a plurality of active regions in which semiconductor elements are formed. And a first diffusion region and a second diffusion region, which are formed in each of the active regions of the semiconductor substrate and in which impurities are diffused in the surface region of the substrate, and are provided on the semiconductor substrate of the active region. A wiring member, a first insulating film that covers the surface of the wiring member, and the semiconductor substrate, the first insulating film, and the isolation insulating film, and a region directly above at least two second diffusion regions is shared. A second insulating film having a planar pattern in which the region including the same is removed and at least a part of the region immediately above the first diffusion region is isolated and remains, and the conductivity provided above the second diffusion region. Parts and Through at least a portion of said second insulating film is removed region is obtained by a configuration in which a contact member for connecting the conductive member and the second diffusion region.

【００１７】請求項１１の発明の講じた手段は、請求項
１０の発明において、上記第２絶縁膜を残存部分が各第
１絶縁膜の直上領域毎に孤立した島状の平面パターンを
有するように構成したものである。According to a tenth aspect of the present invention, in the tenth aspect of the present invention, the remaining portion of the second insulating film has an island-shaped plane pattern in which each region immediately above each first insulating film is isolated. It is configured in.

【００１８】請求項１２の発明の講じた手段は、請求項
１０の発明において、上記第２絶縁膜の残存部分が、所
定方向に配置された複数の第１拡散領域の直上領域を共
通に含む線状の平面パターンを有するように構成したも
のである。According to a twelfth aspect of the present invention, in the tenth aspect of the present invention, the remaining portion of the second insulating film commonly includes a region immediately above a plurality of first diffusion regions arranged in a predetermined direction. It is configured to have a linear plane pattern.

【００１９】請求項７の発明の講じた手段は、請求項１
又は２の発明において、上記第２絶縁膜が、各活性領域
の第１拡散領域に挟まれた分離絶縁膜のうち最小分離幅
の部分の直上領域に残存しているように構成したもので
ある。The means taken by the invention of claim 7 is the method of claim 1.
Alternatively, in the second aspect of the invention, the second insulating film is configured to remain in a region directly above the minimum isolation width portion of the isolation insulating film sandwiched between the first diffusion regions of each active region. .

【００２０】請求項１３の発明の講じた手段は、半導体
装置の製造方法として、半導体基板の表面領域を半導体
素子が形成される複数の活性領域に区画する分離絶縁膜
を形成する工程と、少なくとも上記半導体基板の各活性
領域の一部を含む領域に、配線部材及びその表面を被覆
する第１絶縁膜を形成する工程と、上記活性領域に不純
物を導入して、第１拡散領域及び第２拡散領域を形成す
る工程と、上記各活性領域，第１絶縁膜及び分離絶縁膜
の上に絶縁性膜を堆積した後、堆積された絶縁性膜のう
ち、上記第１拡散領域の直上領域のうちの少なくとも一
部を残し、少なくとも２つの第２拡散領域の直上領域を
共通に含む領域を除去して、第２絶縁膜を形成する工程
と、上記第２拡散領域の上方に、導電性部材と、上記導
電性部材と上記第１拡散領域とを接続するコンタクト部
材を形成する工程とを設ける方法である。According to a thirteenth aspect of the present invention, as a method of manufacturing a semiconductor device, a step of forming an isolation insulating film for partitioning a surface region of a semiconductor substrate into a plurality of active regions in which semiconductor elements are formed, and at least: A step of forming a wiring member and a first insulating film covering the surface thereof in a region including a part of each active region of the semiconductor substrate; and introducing an impurity into the active region to form a first diffusion region and a second diffusion region. Forming a diffusion region, depositing an insulating film on each of the active regions, the first insulating film, and the isolation insulating film, and then depositing an insulating film on the region immediately above the first diffusion region in the deposited insulating film. A step of forming a second insulating film by removing at least a part of the second diffusion region and a region commonly including at least two regions immediately above the second diffusion region; and a conductive member above the second diffusion region. And the conductive member and the first It is a method of providing and forming a contact member for connecting the diffusion region.

【００２１】請求項１４の発明の講じた手段は、請求項
１３の発明において、上記配線部材としてＤＲＡＭメモ
リセルのワード線を形成し、上記第１拡散領域としてＤ
ＲＡＭメモリセルのドレイン領域を形成し、上記第２拡
散領域としてＤＲＡＭメモリセルのソース領域を形成
し、上記導電性部材として容量蓄積電極を形成し、上記
コンタクト部材として、容量蓄積電極とＤＲＡＭメモリ
セルのソース領域とを接続する容量蓄積電極コンタクト
を形成する方法である。According to a fourteenth aspect of the invention, in the invention of the thirteenth aspect, the word line of the DRAM memory cell is formed as the wiring member, and the word line D is formed as the first diffusion region.
A drain region of the RAM memory cell is formed, a source region of the DRAM memory cell is formed as the second diffusion region, a capacitance storage electrode is formed as the conductive member, and a capacitance storage electrode and a DRAM memory cell are formed as the contact member. This is a method of forming a capacitance storage electrode contact that is connected to the source region of.

【００２２】請求項１５の発明の講じた手段は、請求項
１４の発明において、上記第２絶縁膜を形成する工程で
は、堆積された絶縁性膜のうち、ワード線にほぼ平行な
方向に配置された複数のソース領域の直上領域を共通に
含む領域を除去する方法である。According to a fifteenth aspect of the present invention, in the invention of the fourteenth aspect, in the step of forming the second insulating film, the deposited insulating film is arranged in a direction substantially parallel to the word line. This is a method of removing a region that commonly includes a region directly above a plurality of source regions that have been created.

【００２３】請求項１６の発明の講じた手段は、請求項
１４の発明において、上記第２絶縁膜を形成する工程で
は、堆積された絶縁性膜のうち、ワード線にほぼ直交す
る方向に配置された複数のソース領域の直上領域を共通
に含む領域を除去する方法である。According to a sixteenth aspect of the present invention, in the invention of the fourteenth aspect, in the step of forming the second insulating film, the deposited insulating film is arranged in a direction substantially orthogonal to the word line. This is a method of removing a region that commonly includes a region directly above a plurality of source regions that have been created.

【００２４】請求項１７の発明の講じた手段は、請求項
１４の発明において、上記第２絶縁膜を形成する工程で
は、堆積された絶縁性膜のうち、ＤＲＡＭメモリセル内
のすべてのソース領域の直上領域を共通に含む領域を除
去する方法である。According to a seventeenth aspect of the invention, in the invention of the fourteenth aspect, in the step of forming the second insulating film, all the source regions in the DRAM memory cell in the deposited insulating film are formed. This is a method of removing a region that commonly includes a region directly above.

【００２５】請求項１８の発明の講じた手段は、請求項
１４，１５，１６又は１７の発明において、上記ＤＲＡ
Ｍメモリセルの周辺回路を形成する工程と、上記容量蓄
積電極の上に誘電体膜を形成する工程と、上記誘電体膜
の上に、プレート電極を形成する工程とを設け、上記第
２絶縁膜を形成する工程では、第２絶縁膜の除去領域が
プレート電極を形成しようとする領域の内部にあるよう
に形成する方法である。The means taken by the invention of claim 18 is the DRA of the invention of claim 14, 15, 16 or 17.
The step of forming a peripheral circuit of the M memory cell, the step of forming a dielectric film on the capacitance storage electrode, and the step of forming a plate electrode on the dielectric film; In the step of forming the film, the removal region of the second insulating film is formed so as to be inside the region where the plate electrode is to be formed.

【００２６】請求項１９の発明の講じた手段は、請求項
１３の発明において、上記配線部材として電界効果型ト
ランジスタのゲート電極を形成し、上記第１拡散領域と
して電界効果型トランジスタのソース領域を形成し、上
記第２拡散領域として電界効果型トランジスタのドレイ
ン領域を形成し、上記導電性部材としてビット線を形成
し、上記コンタクト部材として、上記ビット線と電界効
果型トランジスタのドレイン領域とを接続するビット線
コンタクトを形成する方法である。According to a nineteenth aspect of the present invention, in the invention of the thirteenth aspect, a gate electrode of a field effect transistor is formed as the wiring member, and a source region of the field effect transistor is formed as the first diffusion region. And forming a drain region of the field effect transistor as the second diffusion region, forming a bit line as the conductive member, and connecting the bit line and the drain region of the field effect transistor as the contact member. It is a method of forming a bit line contact.

【００２７】請求項２０の発明の講じた手段は、請求項
１９の発明において、上記第２絶縁膜を形成する工程で
は、ゲート電極を構成する配線部材にほぼ平行な方向に
配置された複数のドレイン領域の直上領域を共通に含む
領域を除去する方法である。According to a twentieth aspect of the invention, in the invention of the nineteenth aspect, in the step of forming the second insulating film, a plurality of elements arranged in a direction substantially parallel to a wiring member forming a gate electrode are provided. This is a method of removing a region that commonly includes a region directly above the drain region.

【００２８】[0028]

【作用】以上の構成により、請求項１の発明では、導電
性部材と第２拡散領域とを接続するコンタクト部材が第
２拡散領域に接触する面積が十分広く確保される。した
がって、コンタクト抵抗が低く抑制される。With the above construction, in the invention of claim 1, the contact member connecting the conductive member and the second diffusion region has a sufficiently large area in contact with the second diffusion region. Therefore, the contact resistance is suppressed low.

【００２９】請求項２の発明では、ＤＲＡＭメモリセル
において、容量蓄積電極とソース領域とを接続する容量
蓄積電極コンタクトの抵抗が低く抑制されることにな
る。According to the second aspect of the invention, in the DRAM memory cell, the resistance of the capacitance storage electrode contact that connects the capacitance storage electrode and the source region is suppressed low.

【００３０】請求項３又は４の発明では、残存する第２
絶縁膜と除去領域とがライン＆スペースの関係となるの
で、除去領域の形状が安定する。In the invention of claim 3 or 4, the remaining second
Since the insulating film and the removal region have a line-and-space relationship, the shape of the removal region is stable.

【００３１】請求項５の発明では、絶縁膜の除去領域が
最も広くなるので、コンタクト部材と第２拡散領域との
コンタクト面積が特に広く確保されることになる。According to the fifth aspect of the present invention, the area where the insulating film is removed is the widest, so that the contact area between the contact member and the second diffusion area is particularly wide.

【００３２】請求項６の発明では、ビット線上置き型の
ＤＲＡＭメモリセル構造に対し、上記各発明の作用が得
られることになる。According to the sixth aspect of the present invention, the effects of the above-described respective aspects can be obtained for the DRAM memory cell structure of the bit line top type.

【００３３】請求項７の発明では、電界効果型トランジ
スタにおいて、ビット線コンタクトのコンタクト抵抗の
増大や接続不良が防止されることになる。According to the invention of claim 7, in the field effect transistor, an increase in contact resistance of the bit line contact and a connection failure can be prevented.

【００３４】請求項８又は１１の発明では、残存する第
２絶縁膜と除去領域とがライン＆スペースの関係となる
ので、除去領域の形状が安定する。In the invention of claim 8 or 11, since the remaining second insulating film and the removal region have a line-and-space relationship, the shape of the removal region is stable.

【００３５】請求項９の発明では、第２絶縁膜の残存部
分が孤立して残存するので、従来のように第２拡散領域
の一部の直上となる第２絶縁膜の除去領域が孤立したパ
ターンとなるのとは異なり、導電性部材のコンタクト部
材を形成するためのコンタクト用面積が十分確保され
る。According to the ninth aspect of the invention, since the remaining portion of the second insulating film remains isolated, the removed region of the second insulating film, which is directly above a part of the second diffusion region, is isolated as in the conventional case. Unlike the pattern, the contact area for forming the contact member of the conductive member is sufficiently secured.

【００３６】請求項１０の発明では、第２絶縁膜が島状
となることで、導電性部材と第２拡散領域とのコンタク
ト面積が特に広く確保される。According to the tenth aspect of the invention, since the second insulating film has an island shape, a contact area between the conductive member and the second diffusion region is particularly wide.

【００３７】請求項１２の発明では、分離絶縁膜のうち
最小分離幅の部分が第２絶縁膜によって被覆されている
ことで、上方の部材の形成時に、オーバーエッチング等
による分離絶縁膜の損傷が防止され、各活性領域間の分
離機能が良好に維持されることになる。According to the twelfth aspect of the present invention, since the portion of the isolation insulating film having the minimum isolation width is covered with the second insulating film, the isolation insulating film is not damaged by overetching or the like when the upper member is formed. Therefore, the separation function between the respective active regions is maintained well.

【００３８】請求項１３の発明では、導電性部材と第２
拡散領域とのコンタクト部材を形成する際に、第２拡散
領域全体がほとんど露出した状態でコンタクト部材が堆
積されるので、コンタクト部材が第２拡散領域に自己整
合的に形成され、フォトリソグラフィーにおけるマスク
の位置合わせ制度に拘らず、広いコンタクト面積が確保
されることになる。そして、フォトリソグラフィー工程
で形成されるコンタクト部材の形状が良好となる。ま
た、第２絶縁膜と第２拡散領域との重ね合わせマージン
が広くなるので、製造が容易となる。In the thirteenth aspect of the invention, the conductive member and the second
When forming the contact member with the diffusion region, the contact member is deposited in a state where the entire second diffusion region is almost exposed, so that the contact member is formed in the second diffusion region in a self-aligned manner, and is used as a mask in photolithography. A large contact area will be secured regardless of the registration system. Then, the shape of the contact member formed in the photolithography process becomes good. Moreover, since the overlapping margin between the second insulating film and the second diffusion region is widened, the manufacturing is facilitated.

【００３９】請求項１４の発明では、ＤＲＡＭメモリセ
ルの容量蓄積コンタクトを形成する際に、上記請求項１
３の発明の作用が得られることになる。According to a fourteenth aspect of the present invention, when the capacitance storage contact of the DRAM memory cell is formed, the above-mentioned first aspect is adopted.
The effect of the invention of No. 3 is obtained.

【００４０】請求項１５又は１６の発明では、ＤＲＡＭ
メモリセルの容量蓄積電極コンタクトを形成する際に、
残存する第２絶縁膜と除去領域とがライン＆スペースの
関係となっているので、コンタクトの形成が最も安定す
る。According to the fifteenth or sixteenth aspect of the invention, the DRAM is provided.
When forming the capacitor storage electrode contact of the memory cell,
Since the remaining second insulating film and the removed region have a line-and-space relationship, contact formation is most stable.

【００４１】請求項１７の発明では、ＤＲＡＭメモリセ
ルの容量蓄積電極コンタクトを形成する際に、最も広い
コンタクト面積が確保され、かつ容量蓄積電極コンタク
トの形状が良好となる。According to the seventeenth aspect of the present invention, when the capacitance storage electrode contact of the DRAM memory cell is formed, the widest contact area is secured and the shape of the capacitance storage electrode contact becomes good.

【００４２】請求項１８の発明では、プレート電極をパ
ターニングする際に、プレート電極を除去する領域の下
方には必ず第２絶縁膜が残存している状態となるので、
オーバーエッチングによる第２絶縁膜の下方の部材の損
傷が防止されることになる。According to the eighteenth aspect of the present invention, when the plate electrode is patterned, the second insulating film always remains below the region where the plate electrode is removed.
Damage to the member below the second insulating film due to overetching is prevented.

【００４３】請求項１９の発明では、電界効果型トラン
ジスタにおいて、ビット線コンタクトを形成する際に、
上記請求項１３の発明の作用が得られることになる。According to the nineteenth aspect of the invention, in forming the bit line contact in the field effect transistor,
The effect of the invention of claim 13 is obtained.

【００４４】請求項２０の発明では、ビット線コンタク
トを形成する際に、残存する第２絶縁膜と除去領域とが
ライン＆スペースの関係となっているので、コンタクト
の形成が最も安定する。According to the twentieth aspect of the invention, when the bit line contact is formed, the remaining second insulating film and the removed region have a line-and-space relationship, so that the contact is most stably formed.

【００４５】[0045]

【Example】

（第１実施例）以下、本発明の第１実施例の半導体装置
について、図面を参照しながら説明する。図１（ａ），
（ｂ）は、第１実施例に係るスタック型キャパシタセル
を用いたＤＲＡＭのメモリセルアレイ部を示す平面図で
あり、上記図１３（ａ），（ｂ）に対応する図である。
また、図２は、図１のII−II線における断面図であっ
て、上記図１４に対応する図である。ただし、いずれも
ビット線が形成されていない段階における状態を示す。
ここで、上記図１３（ａ），（ｂ）及び図１４に示す要
素と同符号のものは同じ要素である。ここで、上記従来
例と同様に、各活性領域には、第１拡散領域として１つ
のドレイン領域２が形成され、第２拡散領域として２つ
のソース領域３が形成されている。図１（ａ），（ｂ）
において、ハッチングを施した領域が第２絶縁膜１２の
残存領域であり、それ以外の領域が第２絶縁膜１２が除
去された除去領域Ｒetとなっている。この除去領域Ｒet
は、各スイッチングトランジスタ８の各ソース領域３つ
まり複数の拡散領域の直上領域に亘っており、第２絶縁
膜１２はドレイン領域２及びその周囲の素子分離４及び
第１絶縁膜９の直上となる領域に限られている。そし
て、ドットが施された容量蓄積電極コンタクト１１は、
この図ではソース領域３と完全に一致している。第１実
施例では、パターニングで残された第２絶縁膜１２の寸
法は、１．４［μｍ］×１．２［μｍ］であり、除去領
域Ｒetとソース領域３との重ね合わせマージンは０．３
［μｍ］と、非常に大きくなっている。(First Embodiment) A semiconductor device according to a first embodiment of the present invention will be described below with reference to the drawings. Figure 1 (a),
FIG. 13B is a plan view showing a memory cell array portion of a DRAM using the stack type capacitor cell according to the first embodiment, and is a view corresponding to FIGS. 13A and 13B.
2 is a cross-sectional view taken along the line II-II of FIG. 1 and corresponds to FIG. 14 described above. However, each shows the state at the stage where the bit line is not formed.
Here, components having the same reference numerals as those shown in FIGS. 13A, 13B and 14 are the same components. Here, as in the above-described conventional example, one drain region 2 is formed as a first diffusion region and two source regions 3 are formed as a second diffusion region in each active region. 1 (a), (b)
In, the hatched region is the remaining region of the second insulating film 12, and the other region is the removed region Ret where the second insulating film 12 is removed. This removal area Ret
Extends over each source region 3 of each switching transistor 8, that is, over the plurality of diffusion regions, and the second insulating film 12 is over the drain region 2, the element isolation 4 around it, and the first insulating film 9. Limited to the area. Then, the dot-shaped capacitance storage electrode contact 11 is
In this figure, it completely matches with the source region 3. In the first embodiment, the dimension of the second insulating film 12 left by patterning is 1.4 [μm] × 1.2 [μm], and the overlap margin between the removal region Ret and the source region 3 is 0. .3
[Μm], which is very large.

【００４６】次に、第１実施例における半導体装置の製
造工程について、図３（ａ）〜（ｅ）に基づき説明す
る。Next, the manufacturing process of the semiconductor device in the first embodiment will be described with reference to FIGS.

【００４７】同図（ａ）は、半導体基板１上に素子分離
４を形成し、素子分離４で囲まれる活性領域Ｒac内に、
ゲート酸化膜６と、ゲート電極７（素子分離４の上では
ワード線５と表示されている）と、第１絶縁膜９と、ド
レイン領域２と、ソース領域３とを形成する各工程を終
了した状態を示す断面図である。ここまでは、ＬＤＤ構
造のトランジスタを形成するための公知技術を用いて行
われる。In FIG. 3A, the element isolation 4 is formed on the semiconductor substrate 1, and the active region Rac surrounded by the element isolation 4 is
The respective steps of forming the gate oxide film 6, the gate electrode 7 (denoted as the word line 5 on the element isolation 4), the first insulating film 9, the drain region 2, and the source region 3 are completed. It is sectional drawing which shows the state. Up to this point, a known technique for forming a transistor having an LDD structure is used.

【００４８】そして、同図（ｂ）に示すように、減圧Ｃ
ＶＤ法でＨＴＯ膜（高温で堆積したシリコン酸化膜）を
約１００［ｎｍ］の厚みで堆積する。さらに、同図
（ｃ）に示すように、このＨＴＯ膜のうちドレイン領域
２の直上領域とドレイン領域２に隣接する素子分離４及
び第１絶縁膜９の一部の直上領域とを含む領域を残し，
他の領域を除去する。すなわち、フォトリソグラフィー
工程で、ＨＴＯ膜を除去しようとする部分が開口された
フォトレジストパターンを形成し、このフォトレジスト
パターンをエッチングマスクとして、ＣＦ₄、ＣＨ
Ｆ₃、Ａｒガスを用いて第２絶縁膜１２をエッチング
し、開口部にある第２絶縁膜１２を除去する。すると、
ドレイン領域２の直上領域とドレイン領域２に隣接する
第１絶縁膜９及び素子分離４の一部の直上領域とが残存
し、その他の部分つまりソース領域３，ワード線５上の
第１絶縁膜９の大部分及び素子分離４の大部分がそのま
ま露出する。この露出した部分の直上領域が除去領域Ｒ
etとなる。Then, as shown in FIG.
An HTO film (silicon oxide film deposited at high temperature) is deposited with a thickness of about 100 [nm] by the VD method. Further, as shown in FIG. 2C, a region of the HTO film including a region directly above the drain region 2 and a region immediately above the drain region 2 and a part of the element isolation 4 and the first insulating film 9 is formed. Leave,
Remove other areas. That is, in the photolithography process, a photoresist pattern having an opening for removing the HTO film is formed, and CF ₄ , CH 2 is used as an etching mask for the photoresist pattern.
The second insulating film 12 is etched using F ₃ and Ar gas to remove the second insulating film 12 in the opening. Then,
The region immediately above the drain region 2 and the first insulating film 9 adjacent to the drain region 2 and the region immediately above the part of the element isolation 4 remain, and the other parts, that is, the source region 3 and the first insulating film on the word line 5 are left. Most of 9 and most of element isolation 4 are exposed as they are. The area directly above this exposed portion is the removal area R
It becomes et.

【００４９】次に同図（ｄ）に示すように、減圧ＣＶＤ
法でｐｏｌｙ−Ｓｉ膜を約６００［ｎｍ］堆積する。次
にＰ⁺を７０［ＫｅＶ］で１×１０¹⁶［／ｃｍ²］注入
したのち、フォトリソグラフィー工程でレジストパター
ンを形成し、このレジストパターンをエッチングマスク
としてｐｏｌｙ−Ｓｉ膜をエッチングして、容量蓄積電
極１３を形成する。このとき、除去領域Ｒet内に含まれ
るソース領域３に、容量蓄積電極１３とソース領域３と
を接続する容量蓄積電極コンタクト１１が自己整合的に
形成される。Next, as shown in FIG. 3D, low pressure CVD
Method is used to deposit a poly-Si film of about 600 nm. Next, after implanting P ⁺ with 1 × 10 ¹⁶ [/ cm ² ] at 70 [KeV], a resist pattern is formed by a photolithography process, and the poly-Si film is etched using this resist pattern as an etching mask to form a capacitor. The storage electrode 13 is formed. At this time, the capacitance storage electrode contact 11 that connects the capacitance storage electrode 13 and the source region 3 is formed in the source region 3 included in the removal region Ret in a self-aligned manner.

【００５０】次に、同図（ｅ）に示すように、減圧ＣＶ
Ｄ法でＳｉ₃Ｎ₄膜を約６［ｎｍ］堆積したのち、約８
５０［℃］、約１５［分］のパイロ酸化で、Ｓｉ₃Ｎ₄
膜上にＳｉ０₂膜を形成して、容量絶縁膜１４を形成す
る。そして、減圧ＣＶＤ法でＤＰＳ（Ｐ⁺添加ｐｏｌｙ
−Ｓｉ）膜を約１５０［ｎｍ］堆積したのち、フォトリ
ソグラフィー工程でレジストパターンを形成し、このレ
ジストパターンをエッチングマスクとしてＤＰＳ膜をエ
ッチングして、プレート電極１５を形成する。Next, as shown in FIG. 6 (e), the reduced pressure CV
About 6 [nm] of Si ₃ N ₄ film is deposited by D method, and then about 8
Si ₃ N _{4 is obtained by} pyrooxidation at 50 [° C] and about 15 [min].
A SiO ₂ film is formed on the film to form the capacitive insulating film 14. Then, DPS (P ⁺ addition poly
After depositing a -Si) film for about 150 nm, a resist pattern is formed by a photolithography process, and the DPS film is etched using this resist pattern as an etching mask to form the plate electrode 15.

【００５１】以上のように、本実施例では、除去領域Ｒ
etが複数のソース領域３の直上領域を共通に含んでいる
ので、容量蓄積電極１３を形成するためのｐｏｌｙ−Ｓ
ｉ膜を堆積する際、各ソース領域３の間の素子分離や第
１絶縁膜９が露出している。そして、ｐｏｌｙ−Ｓｉ膜
を堆積すると、ソース領域３上にのみ容量蓄積電極コン
タクト１１が自己整合的に形成されることとなる。ここ
で、図１（ｂ）に示すように、上記実施例では、第２絶
縁膜１２の残存部分の寸法は１．４［μｍ］×１．２
［μｍ］であり、除去領域Ｒetの占める面積を従来より
非常に大きくすることができる。このため、フォトリソ
グラフィー工程での解像度の不足を防止することができ
る。また、容量蓄積電極コンタクト１１の寸法はソース
領域３の寸法で決定され、除去領域Ｒetには依存しな
い。したがって、除去領域Ｒetの端部とソース領域３の
端部とのマージンは、例えば上記実施例では、従来例の
０．０５［μｍ］より広く０．３［μｍ］だけ確保でき
る。このため、フォトリソグラフィー工程でのレジスト
パターンのテール引きによるエッチング工程でのレジス
トパターンの不規則な後退や、除去領域Ｒetの端部とソ
ース領域３の端部とのシフトが発生したとしても、容量
蓄積電極コンタクト１１の形状は良好となり、その寸法
や抵抗値は一定となる。つまり、接続不良やコンタクト
抵抗の増大を有効に防止することができる。As described above, in this embodiment, the removal region R
Since et includes a region directly above the plurality of source regions 3 in common, poly-S for forming the capacitance storage electrode 13 is formed.
When depositing the i film, the element isolation between the source regions 3 and the first insulating film 9 are exposed. Then, when the poly-Si film is deposited, the capacitance storage electrode contact 11 is formed only on the source region 3 in a self-aligned manner. Here, as shown in FIG. 1B, in the above embodiment, the size of the remaining portion of the second insulating film 12 is 1.4 [μm] × 1.2.
[Μm], and the area occupied by the removal region Ret can be made much larger than in the conventional case. Therefore, it is possible to prevent insufficient resolution in the photolithography process. The size of the capacitance storage electrode contact 11 is determined by the size of the source region 3 and does not depend on the removal region Ret. Therefore, the margin between the end of the removal region Ret and the end of the source region 3 can be secured by 0.3 [μm], which is wider than 0.05 [μm] of the conventional example in the above-described embodiment. Therefore, even if the resist pattern is irregularly recessed in the etching process due to the tailing of the resist pattern in the photolithography process or the edge of the removal region Ret and the edge of the source region 3 are shifted, The shape of the storage electrode contact 11 is good, and its size and resistance value are constant. That is, it is possible to effectively prevent connection failure and increase in contact resistance.

【００５２】なお、上記実施例では説明を省略したが、
ドレイン領域２及びソース領域３は、いずれも高濃度に
不純物が拡散された高濃度領域と低濃度に不純物が拡散
された低濃度領域とを有する。上記実施例では、第１拡
散領域は、低濃度領域及び高濃度領域を含むドレイン領
域２であり、第２拡散領域は、低濃度領域及び高濃度領
域を含むソース領域である。Although not described in the above embodiment,
Each of the drain region 2 and the source region 3 has a high concentration region in which impurities are diffused in high concentration and a low concentration region in which impurities are diffused in low concentration. In the above embodiment, the first diffusion region is the drain region 2 including the low concentration region and the high concentration region, and the second diffusion region is the source region including the low concentration region and the high concentration region.

【００５３】（第２実施例）次に、第２実施例について
説明する。図４（ａ）は第２実施例に係る半導体装置の
平面図であり、図４（ｂ）は図４（ａ）の一部を拡大し
た図である。本実施例においても、半導体装置の活性領
域Ｒacに形成される半導体素子は、スタック型キャパシ
タセルＤＲＡＭメモリセルのスイッチングトランジスタ
であり、その基本的な構造は、上記第１実施例と同じで
ある。つまり、第１実施例における図２に相当する断面
構造は図２と同じであるので、図示を省略する。ただ
し、本実施例では、図４（ａ），（ｂ）に示すように、
第２絶縁膜１２はワード線５にほぼ平行な方向に沿って
線状に残存している。すなわち、第２絶縁膜１２の残存
部分は、ワード線５に平行な方向に配置されたすべての
ドレイン領域２の直上領域とその周辺の第１絶縁膜９及
び素子分離４の直上領域とを含んでいる。したがって、
除去領域Ｒetは、ワード線５に平行な方向に配置された
すべてのソース領域３の直上領域とソース領域３の周辺
の第１絶縁膜９及び素子分離４の直上領域とを含んでい
る。(Second Embodiment) Next, a second embodiment will be described. FIG. 4A is a plan view of the semiconductor device according to the second embodiment, and FIG. 4B is an enlarged view of a part of FIG. 4A. Also in this embodiment, the semiconductor element formed in the active region Rac of the semiconductor device is the switching transistor of the stack type capacitor cell DRAM memory cell, and its basic structure is the same as that of the first embodiment. That is, the sectional structure corresponding to FIG. 2 in the first embodiment is the same as that in FIG. However, in this embodiment, as shown in FIGS.
The second insulating film 12 remains linearly along a direction substantially parallel to the word line 5. That is, the remaining portion of the second insulating film 12 includes the regions immediately above all the drain regions 2 arranged in the direction parallel to the word lines 5 and the regions immediately above the first insulating film 9 and the element isolation 4 around the drain regions 2. I'm out. Therefore,
The removal region Ret includes a region directly above all the source regions 3 arranged in a direction parallel to the word line 5 and a region immediately above the first insulating film 9 and the element isolation 4 around the source region 3.

【００５４】したがって、第２実施例では、上記第１実
施例と同様に、容量蓄積電極用コンタクト１１を形成す
るためのスペースが十分確保され、接続不良やコンタク
ト抵抗の増大を防止することができる。特に、第１実施
例と比較して、残存する第２絶縁膜１２と除去領域Ｒet
とが大きなライン＆スペースの関係となっているので、
除去領域Ｒetのパターンが安定する。また、除去領域Ｒ
etの占める面積が第１実施例よりも減小するので、フォ
トリソグラフィー工程で、除去領域Ｒetの下方の部材か
らの光の反射に起因する第２絶縁膜１２の残部における
フォトレジストパターンの変形を抑制することができ
る。Therefore, in the second embodiment, similar to the first embodiment, a sufficient space for forming the capacitor storage electrode contact 11 is secured, and it is possible to prevent connection failure and increase in contact resistance. . In particular, as compared with the first embodiment, the remaining second insulating film 12 and the removal region Ret
Since and have a big line & space relationship,
The pattern of the removal area Ret becomes stable. In addition, the removal area R
Since the area occupied by et is smaller than that in the first embodiment, in the photolithography process, the deformation of the photoresist pattern in the remaining portion of the second insulating film 12 due to the reflection of light from the member below the removal region Ret is prevented. Can be suppressed.

【００５５】（第３実施例）次に、第３実施例について
説明する。図５（ａ）は第３実施例に係る半導体装置の
平面図、図５（ｂ）は図５（ａ）の一部を拡大した図、
図６は図５（ａ）のVI−VI線における断面図である。本
実施例においても、半導体装置の活性領域Ｒacには、Ｄ
ＲＡＭメモリセルのスイッチングトランジスタが配設さ
れており、ＤＲＡＭメモリセル自体の基本的な構造は上
記第１，第２実施例とほぼ同様である。(Third Embodiment) Next, a third embodiment will be described. 5A is a plan view of the semiconductor device according to the third embodiment, FIG. 5B is an enlarged view of a part of FIG. 5A,
FIG. 6 is a sectional view taken along line VI-VI in FIG. Also in this embodiment, D is formed in the active region Rac of the semiconductor device.
The switching transistor of the RAM memory cell is provided, and the basic structure of the DRAM memory cell itself is almost the same as that of the first and second embodiments.

【００５６】ここで、第３実施例の特徴として、第２絶
縁膜１２は、ワード線５に直交する方向に配置された２
つのソース領域３の直上領域を共通に含む領域（周辺の
第１絶縁膜９及び素子分離４の直上領域も含む）が除去
されている。したがって、上記第１，第２実施例と同様
に、容量蓄積コンタクト１１の形状が改善され、コンタ
クト面積も広く確保されて、コンタクト抵抗の増大を抑
制しうる。Here, as a characteristic of the third embodiment, the second insulating film 12 is arranged in a direction orthogonal to the word line 5.
A region that includes a region directly above the one source region 3 in common (including a region directly above the first insulating film 9 and the element isolation 4 in the periphery) is removed. Therefore, similarly to the first and second embodiments, the shape of the capacitance storage contact 11 is improved, the contact area is secured wide, and the increase in contact resistance can be suppressed.

【００５７】また、本実施例では、図６に示すように、
第２絶縁膜１２の残存部分が素子分離４の最小分離幅と
なる領域２２を含む構造となっている。これに対し、図
７に示すように、素子分離４の最小分離幅となる領域２
２で第２絶縁膜１２が除去されている場合には、第２絶
縁膜１２のパターニングの際に、第２絶縁膜１２のオー
バーエッチングにより、ワード線５と平行な方向で相隣
接するソース領域３間を電気的に絶縁分離する素子分離
４の膜厚が減小し、素子分離４の分離機能の低下を生じ
る虞れがある。本実施例では、このような素子分離４の
素子分離機能の低下を有効に防止することができる。In this embodiment, as shown in FIG.
The remaining portion of the second insulating film 12 has a structure including a region 22 having the minimum isolation width of the element isolation 4. On the other hand, as shown in FIG. 7, the region 2 having the minimum isolation width of the element isolation 4 is formed.
When the second insulating film 12 is removed in step 2, the source regions adjacent to each other in the direction parallel to the word line 5 are formed by over-etching the second insulating film 12 when patterning the second insulating film 12. The film thickness of the element isolation 4 for electrically insulating and isolating the elements 3 from each other may be reduced, and the isolation function of the element isolation 4 may be deteriorated. In this embodiment, it is possible to effectively prevent such a decrease in the element isolation function of the element isolation 4.

【００５８】なお、図８に示すように、複数のＤＲＡＭ
メモリセルのソース領域３間を折線状に接続する領域の
直上となる領域が除去領域Ｒetとなるように構成しても
よい。この場合、ワード線５の方向にほぼ直交する方向
に配置された複数のソース領域３の直上領域を共通に含
む領域が除去領域Ｒetとなっている。In addition, as shown in FIG.
The removal region Ret may be formed immediately above the region connecting the source regions 3 of the memory cells in a polygonal line shape. In this case, the removal region Ret is a region that commonly includes the regions directly above the plurality of source regions 3 arranged in the direction substantially orthogonal to the direction of the word lines 5.

【００５９】（第４実施例）次に、第４実施例について
説明する。図９は第４実施例に係る半導体装置の平面
図、図１０は図９のX −X 線における断面図である。同
図において、領域ＲmemoにはＤＲＡＭメモリセルが配設
され、領域Ｒperiには周辺回路のトランジスタが配設さ
れている。ＤＲＡＭメモリセルアレイ部の構造は、上記
第１実施例と同じである。一方、周辺回路において、第
２絶縁膜１２は、トランジスタのゲート電極を構成する
配線部材１９を被覆する第１絶縁膜９と、素子分離４
と、活性領域Ｒacとを含む領域の直上領域で残存してい
る。ただし、同図の状態は、ＤＲＡＭメモリセルのビッ
ト線及び周辺回路のトランジスタのビット線及びワード
線が形成されていない状態を示す。(Fourth Embodiment) Next, a fourth embodiment will be described. 9 is a plan view of a semiconductor device according to the fourth embodiment, and FIG. 10 is a sectional view taken along line XX of FIG. In the figure, DRAM memory cells are arranged in the region Rmemo, and transistors of peripheral circuits are arranged in the region Rperi. The structure of the DRAM memory cell array portion is the same as that of the first embodiment. On the other hand, in the peripheral circuit, the second insulating film 12 is separated from the first insulating film 9 covering the wiring member 19 forming the gate electrode of the transistor and the element isolation 4
And an area immediately above the area including the active area Rac. However, the state of the figure shows a state in which the bit line of the DRAM memory cell and the bit line and word line of the transistor of the peripheral circuit are not formed.

【００６０】また、図１０に示すように、本実施例で
は、第２絶縁膜１２が形成された後プレート電極を形成
した時点で、第２絶縁膜１２の除去領域Ｒetがプレート
電極１５を形成しようとする領域に完全に含まれるよう
にしている。したがって、プレート電極１５を構成する
膜を堆積した後エッチングしてパターニングする際に、
エッチング下地には、常に第２絶縁膜１２が存在しする
ことになる。これに対し、第２絶縁膜１２の除去領域Ｒ
etがプレート電極１５を形成しようとする領域の外方に
はみ出た構造となっている場合には、図１１に示すよう
に、プレート電極１５をパターニングする際に、オーバ
ーエッチングによって、領域２０のように素子分離４の
膜厚が減小したり、領域２１のように第１絶縁膜９の膜
厚が減小してゲート電極７が破損を受ける虞れがある。
本実施例では、このような不具合を有効に防止すること
ができる。Further, as shown in FIG. 10, in the present embodiment, when the plate electrode is formed after the second insulating film 12 is formed, the removal region Ret of the second insulating film 12 forms the plate electrode 15. It is intended to be fully contained within the area of interest. Therefore, when patterning by etching after depositing the film forming the plate electrode 15,
The second insulating film 12 is always present on the etching base. On the other hand, the removal region R of the second insulating film 12
In the case where et has a structure protruding outside the region where the plate electrode 15 is to be formed, as shown in FIG. In addition, the film thickness of the element isolation 4 may be reduced, or the film thickness of the first insulating film 9 may be reduced as in the region 21, and the gate electrode 7 may be damaged.
In this embodiment, such a problem can be effectively prevented.

【００６１】（第５実施例）次に、第５実施例について
説明する。図１２は第５実施例に係る半導体装置の平面
図、図１３はそのXIII−XIII線における断面図であり、
ビット線下置き型ＤＲＡＭメモリセルの構造を示す。本
実施例では、上記各実施例と同様に、ゲート電極７（ワ
ード線５）の上に第１絶縁膜９が形成され、ソース領域
３，ドレイン領域２，第１絶縁膜９及び素子分離４の上
に第２絶縁膜１２が堆積されている。そして、この第２
絶縁膜１２の上に、ドレイン領域３に接続されるビット
線３０が設けられる。その際、第２絶縁膜１２が、少な
くとも各ＤＲＡＭメモリセルのソース領域３の直上領域
とその周囲の第１絶縁膜９及び素子分離４の直上領域と
で残存し、ワード線５に直交する方向に配置された各ド
レイン領域２の直上領域とその周囲の第１絶縁膜９及び
素子分離４の直上領域とで除去されている。そして、こ
の除去領域Ｒetを介して、ビット線コンタクト３１を設
けるようにしている。また、ビット線３０の上に層間絶
縁膜３２を設け、さらにその上に容量蓄積電極１３を形
成した後、ソース領域３上の第２絶縁膜１２を貫通して
容量蓄積電極コンタクト１１を形成するようにしてい
る。(Fifth Embodiment) Next, a fifth embodiment will be described. 12 is a plan view of the semiconductor device according to the fifth embodiment, and FIG. 13 is a sectional view taken along line XIII-XIII thereof.
1 shows the structure of a bit line lower type DRAM memory cell. In this embodiment, as in the above embodiments, the first insulating film 9 is formed on the gate electrode 7 (word line 5), and the source region 3, the drain region 2, the first insulating film 9 and the element isolation 4 are formed. A second insulating film 12 is deposited on the. And this second
A bit line 30 connected to the drain region 3 is provided on the insulating film 12. At that time, the second insulating film 12 remains at least in the region immediately above the source region 3 of each DRAM memory cell and in the region immediately above the first insulating film 9 and the element isolation 4 around the source region 3, and is orthogonal to the word line 5. Of the drain region 2 and the regions immediately above the first insulating film 9 and the element isolation 4 around it. Then, the bit line contact 31 is provided via the removal region Ret. Further, an interlayer insulating film 32 is provided on the bit line 30, a capacitance storage electrode 13 is further formed thereon, and then a capacitance storage electrode contact 11 is formed through the second insulating film 12 on the source region 3. I am trying.

【００６２】したがって、上記第５実施例では、ビット
線３０のコンタクト面積が十分確保され、接続不良や断
線等の虞れを防止することができる。Therefore, in the fifth embodiment described above, the contact area of the bit line 30 is sufficiently secured, and it is possible to prevent the possibility of connection failure or disconnection.

【００６３】なお、上記各実施例では、半導体素子とし
てＤＲＡＭメモリセルを配設した半導体装置について説
明したが、本発明はかかる実施例に限定されるものでは
なく、他の半導体素子についても適用し得るものであ
る。In each of the above embodiments, the semiconductor device in which the DRAM memory cell is provided as the semiconductor element has been described, but the present invention is not limited to this embodiment and is applied to other semiconductor elements. I will get it.

【００６４】また、上記各実施例では、第２絶縁膜１２
の除去領域Ｒetが、複数の活性領域Ｒacの各ドレイン領
域２の直上領域又はソース領域３の直上領域を共通に含
む場合について説明したが、本発明はかかる実施例に限
定されるものではない。一つの活性領域Ｒac内に３つ以
上の拡散領域を有する場合、例えば第１拡散領域が２つ
で第２拡散領域が一つの場合、同じ活性領域内の２つの
第１拡散領域の直上領域を共通に含む領域で第２絶縁膜
１２を除去するようにしてもよい。In each of the above embodiments, the second insulating film 12 is also used.
However, the present invention is not limited to such an embodiment, although the removal region Ret in common includes a region directly above the drain region 2 or a region directly above the source region 3 of the plurality of active regions Rac. When there are three or more diffusion regions in one active region Rac, for example, when there are two first diffusion regions and one second diffusion region, a region directly above two first diffusion regions in the same active region is used. The second insulating film 12 may be removed in a region including the same.

【００６５】[0065]

【発明の効果】以上説明したように、請求項１の発明に
よれば、半導体装置の構成として、半導体基板上に分離
絶縁膜を設け、分離絶縁膜で囲まれる各活性領域に、第
１拡散領域及び第２拡散領域と配線部材とを設けるとと
もに、配線部材の表面を第１絶縁膜で被覆し、少なくと
も２つの第２拡散領域の直上領域を共通に含む領域が除
去された第２絶縁膜を設け、その上に導電性部材とその
コンタクト部材とを設ける構成としたので、コンタクト
部材が第２拡散領域に接触する面積を十分広く確保する
ことができ、よって、コンタクト抵抗の増大や接続不良
を有効に防止することができる。As described above, according to the invention of claim 1, as the structure of the semiconductor device, the isolation diffusion film is provided on the semiconductor substrate, and the first diffusion region is provided in each active region surrounded by the isolation insulation film. A second insulating film in which a region and a second diffusion region and a wiring member are provided, the surface of the wiring member is covered with a first insulating film, and a region which includes a region directly above at least two second diffusion regions in common is removed. Since the conductive member and its contact member are provided thereon, it is possible to secure a sufficiently large area in which the contact member contacts the second diffusion region, thus increasing the contact resistance and poor connection. Can be effectively prevented.

【００６６】請求項２の発明によれば、請求項１の発明
において、各活性領域にＤＲＡＭメモリセルを配設し、
配線部材をワード線とし、第１，第２拡散領域をそれぞ
れドレイン領域，ソース領域とし、導電性部材を容量蓄
積電極とし、コンタクト部材を容量蓄積電極コンタクト
としたので、容量蓄積電極コンタクトの抵抗を低く抑制
することができる。According to the invention of claim 2, in the invention of claim 1, a DRAM memory cell is provided in each active region,
Since the wiring member is the word line, the first and second diffusion regions are the drain region and the source region, the conductive member is the capacitance storage electrode, and the contact member is the capacitance storage electrode contact, the resistance of the capacitance storage electrode contact is It can be suppressed low.

【００６７】請求項３の発明によれば、請求項２の発明
において、第２絶縁膜が除去された領域が、ワード線に
ほぼ平行な方向に配置された複数のソース領域の直上領
域を共通に含むように構成したので、残存する第２絶縁
膜と除去領域とをライン＆スペースの関係として、除去
領域の形状が安定する。According to the invention of claim 3, in the invention of claim 2, the region from which the second insulating film is removed shares a region directly above a plurality of source regions arranged in a direction substantially parallel to the word line. Since the remaining second insulating film and the removal region are brought into line-and-space relationship with each other, the shape of the removal region is stabilized.

【００６８】請求項４の発明によれば、請求項２の発明
において、第２絶縁膜が除去された領域が、ワード線に
ほぼ直交する方向に配置された複数のソース領域の直上
領域を共通に含むように構成したので、残存する第２絶
縁膜と除去領域とをライン＆スペースの関係として、除
去領域の形状が安定する。According to the invention of claim 4, in the invention of claim 2, the region from which the second insulating film is removed shares a region directly above a plurality of source regions arranged in a direction substantially orthogonal to the word line. Since the remaining second insulating film and the removal region are brought into line-and-space relationship with each other, the shape of the removal region is stabilized.

【００６９】請求項５の発明によれば、請求項２の発明
において、第２絶縁膜が除去された領域が、すべてのソ
ース領域の直上領域を共通に含むように構成したので、
コンタクト部材と第２拡散領域とのコンタクト面積を特
に広く確保することができる。According to the invention of claim 5, in the invention of claim 2, the region where the second insulating film is removed is configured so as to include the region directly above all the source regions in common.
It is possible to secure a particularly large contact area between the contact member and the second diffusion region.

【００７０】請求項６の発明によれば、請求項２，３，
４又は５の発明において、容量蓄積電極の上方にビット
線を設け、ドレイン領域の上を被覆する第２絶縁膜の一
部を貫通してビット線コンタクトを設ける構成としたの
で、ビット線上置き型のＤＲＡＭメモリセル構造に対
し、上記各発明の作用が得られることになる。According to the invention of claim 6, claims 2, 3,
In the invention of 4 or 5, the bit line is provided above the capacitance storage electrode, and the bit line contact is provided through a part of the second insulating film covering the drain region. With respect to the DRAM memory cell structure of, the effects of each of the above inventions can be obtained.

【００７１】請求項７の発明によれば、請求項１の発明
において、各活性領域に電界効果型トランジスタを配設
し、配線部材をゲート電極とし、第１，第２拡散領域を
それぞれソース領域，ドレイン領域とし、導電性部材を
ビット線とし、コンタクト部材をビット線コンタクトと
したので、ビット線コンタクトのコンタクト抵抗の増大
や接続不良を防止することができる。According to the invention of claim 7, in the invention of claim 1, the field effect transistor is arranged in each active region, the wiring member serves as a gate electrode, and the first and second diffusion regions respectively serve as source regions. Since the drain region is used, the conductive member is a bit line, and the contact member is a bit line contact, it is possible to prevent an increase in contact resistance of the bit line contact and a connection failure.

【００７２】請求項８の発明によれば、請求項７の発明
において、第２絶縁膜が除去された領域が、ゲート電極
を構成する配線部材に平行な方向に配置された複数のド
レイン領域の直上領域を共通に含むように構成したの
で、残存する第２絶縁膜と除去領域とがライン＆スペー
スの関係となり、除去領域のパターンの安定化を図るこ
とができる。According to the invention of claim 8, in the invention of claim 7, the region from which the second insulating film is removed is a plurality of drain regions arranged in a direction parallel to the wiring member forming the gate electrode. Since the region directly above is commonly included, the remaining second insulating film and the removal region have a line-and-space relationship, and the pattern of the removal region can be stabilized.

【００７３】請求項９の発明によれば、半導体装置の構
成として、半導体基板上に分離絶縁膜を設け、分離絶縁
膜で囲まれる各活性領域に、第１拡散領域及び第２拡散
領域と配線部材とを設けるとともに、配線部材の表面を
第１絶縁膜で被覆し、孤立して残存する平面パターンを
有する第２絶縁膜を設け、その上に導電性部材とそのコ
ンタクト部材とを設ける構成としたので、導電性部材の
コンタクト部材を形成するためのコンタクト用面積を十
分確保することができ、よって、コンタクト抵抗の増大
や接続不良を有効に防止することができる。According to the invention of claim 9, as a structure of a semiconductor device, an isolation insulating film is provided on a semiconductor substrate, and each active region surrounded by the isolation insulating film has a first diffusion region, a second diffusion region and a wiring. A second insulating film having a plane pattern that remains isolated by covering the surface of the wiring member with the first insulating film, and providing the conductive member and its contact member thereon. Therefore, it is possible to secure a sufficient contact area for forming the contact member of the conductive member, and thus it is possible to effectively prevent an increase in contact resistance and connection failure.

【００７４】請求項１０の発明によれば、請求項９の発
明において、第２絶縁膜の残存部分が各第２拡散領域の
直上領域毎に孤立した島状の平面パターンを有するよう
に構成したので、導電性部材と第２拡散領域とのコンタ
クト面積を特に広く確保することができる。According to the invention of claim 10, in the invention of claim 9, the remaining portion of the second insulating film has an island-shaped plane pattern isolated for each region immediately above each second diffusion region. Therefore, it is possible to secure a particularly large contact area between the conductive member and the second diffusion region.

【００７５】請求項１１の発明によれば、請求項９の発
明において、第２絶縁膜の残存部分が、所定方向に配置
された複数の第１拡散領域を共通に含む線状の平面パタ
ーンを有するように構成したので、残存する第２絶縁膜
と除去領域とがライン＆スペースの関係となり、除去領
域のパターンの安定化を図ることができる。According to the invention of claim 11, in the invention of claim 9, the remaining portion of the second insulating film has a linear planar pattern which commonly includes a plurality of first diffusion regions arranged in a predetermined direction. Since the second insulating film and the removed region have a line-and-space relationship, the pattern of the removed region can be stabilized.

【００７６】請求項１２の発明によれば、請求項１，２
又は７の発明において、第２絶縁膜の残存部分が、各活
性領域の第１拡散領域に挟まれた分離絶縁膜のうち最小
分離幅の部分を含むように構成したので、製造工程中に
おける分離絶縁膜の損傷を防止することができ、よっ
て、各活性領域間の分離機能を良好に維持することがで
きる。According to the invention of claim 12, claims 1 and 2 are provided.
Alternatively, in the invention of Item 7, since the remaining portion of the second insulating film is configured to include the portion of the minimum isolation width of the isolation insulating film sandwiched between the first diffusion regions of each active region, the isolation during the manufacturing process is performed. It is possible to prevent damage to the insulating film, and thus maintain a good separation function between the active regions.

【００７７】請求項１３の発明によれば、半導体装置の
製造方法として、半導体基板上に分離絶縁膜と第１絶縁
膜と第１拡散領域及び第２拡散領域とを形成した後、上
記各活性領域，第１絶縁膜及び分離絶縁膜の上に絶縁性
膜を堆積し、少なくとも２つの第２拡散領域の直上領域
を共通に含む領域を除去して第２絶縁膜を形成し、さら
に、第２拡散領域の上方に導電性部材とコンタクト部材
とを形成するようにしたので、コンタクト部材を第２拡
散領域に自己整合的に形成することができ、よって、広
いコンタクト面積の確保と製造の容易化とを図ることが
できる。According to a thirteenth aspect of the present invention, as a method of manufacturing a semiconductor device, after forming an isolation insulating film, a first insulating film, a first diffusion region and a second diffusion region on a semiconductor substrate, each of the above-mentioned activities is performed. An insulating film is deposited on the region, the first insulating film, and the isolation insulating film, and a region that commonly includes a region immediately above at least two second diffusion regions is removed to form a second insulating film. Since the conductive member and the contact member are formed above the second diffusion region, it is possible to form the contact member in the second diffusion region in a self-aligned manner, thus ensuring a wide contact area and facilitating manufacturing. Can be promoted.

【００７８】請求項１４の発明によれば、請求項１３の
発明において、配線部材としてＤＲＡＭメモリセルのワ
ード線を形成し、第１，第２拡散領域としてそれぞれド
レイン領域，ソース領域を形成し、導電性部材として容
量蓄積電極を形成し、コンタクト部材として容量蓄積電
極コンタクトを形成するようにしたので、ＤＲＡＭメモ
リセルの容量蓄積コンタクトを形成する際に、上記請求
項１４の発明の効果を得ることができる。According to the invention of claim 14, in the invention of claim 13, the word line of the DRAM memory cell is formed as the wiring member, and the drain region and the source region are formed as the first and second diffusion regions, respectively. Since the capacitance storage electrode is formed as the conductive member and the capacitance storage electrode contact is formed as the contact member, the effect of the invention of claim 14 is obtained when the capacitance storage contact of the DRAM memory cell is formed. You can

【００７９】請求項１５によれば、請求項１４の発明に
おいて、第２絶縁膜を形成する工程では、堆積された絶
縁性膜のうち、ワード線にほぼ平行な方向に配置された
複数のソース領域の直上領域を共通に含む領域を除去す
るようにしたので、ＤＲＡＭメモリセルの容量蓄積電極
コンタクトを形成する際に、残存する第２絶縁膜と除去
領域とをライン＆スペースの関係として、コンタクトの
形成の安定化を図ることができる。According to a fifteenth aspect, in the invention of the fourteenth aspect, in the step of forming the second insulating film, a plurality of sources of the deposited insulating film are arranged in a direction substantially parallel to the word line. Since the region including the region directly above the region is removed in common, when the capacitance storage electrode contact of the DRAM memory cell is formed, the remaining second insulating film and the removed region have a line-and-space relationship to form a contact. Can be stabilized.

【００８０】請求項１６の発明の講じた手段は、請求項
１４の発明において、第２絶縁膜を形成する工程では、
堆積された絶縁性膜のうち、ワード線にほぼ直交する方
向に配置された複数のソース領域の直上領域を共通に含
む領域を除去するようにしたので、請求項１６の発明と
同様の効果を得ることができる。According to a sixteenth aspect of the invention, in the method of the fourteenth aspect, in the step of forming the second insulating film,
Of the deposited insulating film, a region which includes a region directly above a plurality of source regions arranged in a direction substantially orthogonal to the word line in common is removed. Therefore, an effect similar to that of the invention of claim 16 is obtained. Obtainable.

【００８１】請求項１７の発明によれば、請求項１４の
発明において、第２絶縁膜を形成する工程では、堆積さ
れた絶縁性膜のうち、すべてのドレイン領域の直上領域
を共通に含む領域を除去するようにしたので、ＤＲＡＭ
メモリセルの容量蓄積電極コンタクトを形成する際に、
最も広いコンタクト面積を確保することができる。According to the seventeenth aspect of the present invention, in the fourteenth aspect of the present invention, in the step of forming the second insulating film, a region of the deposited insulating film that includes a region directly above all drain regions in common. So that the DRAM is removed.
When forming the capacitor storage electrode contact of the memory cell,
The widest contact area can be secured.

【００８２】請求項１８の発明によれば、請求項１４，
１５，１６又は１７の発明において、ＤＲＡＭメモリセ
ルの周辺回路を形成し、容量蓄積電極の上に誘電体膜と
プレート電極を順次形成するとともに、第２絶縁膜を形
成する工程では、第２絶縁膜の除去領域がプレート電極
を形成しようとする領域の内部にあるようにしたので、
第２絶縁膜の下方の部材の損傷を有効に防止することが
できる。According to the invention of claim 18, claim 14,
In the invention of 15, 16, or 17, the peripheral circuit of the DRAM memory cell is formed, the dielectric film and the plate electrode are sequentially formed on the capacitance storage electrode, and the second insulating film is formed in the step of forming the second insulating film. Since the removal area of the film is inside the area where the plate electrode is to be formed,
It is possible to effectively prevent damage to a member below the second insulating film.

【００８３】請求項１９の発明によれば、請求項１３の
発明において、配線部材として電界効果型トランジスタ
のゲート電極を形成し、第１，第２拡散領域としてそれ
ぞれソース領域，ドレイン領域を形成し、導電性部材と
してビット線を形成し、コンタクト部材としてビット線
コンタクトを形成するようにしたので、ビット線コンタ
クトを形成する際に、上記請求項１４の発明の効果を得
ることができる。According to the invention of claim 19, in the invention of claim 13, the gate electrode of the field effect transistor is formed as the wiring member, and the source region and the drain region are formed as the first and second diffusion regions, respectively. Since the bit line is formed as the conductive member and the bit line contact is formed as the contact member, the effect of the invention of claim 14 can be obtained when the bit line contact is formed.

【００８４】請求項２０の発明によれば、請求項１９の
発明において、第２絶縁膜を形成する工程では、ゲート
電極を構成する配線部材にほぼ平行な方向に配置された
複数のドレイン領域の直上領域を共通に含む領域を除去
するようにしたので、残存する第２絶縁膜と除去領域と
がライン＆スペースの関係となり、コンタクトの形成の
安定化を図ることができる。According to the twentieth aspect of the invention, in the nineteenth aspect of the invention, in the step of forming the second insulating film, a plurality of drain regions arranged in a direction substantially parallel to the wiring member forming the gate electrode are formed. Since the region including the region immediately above is commonly removed, the remaining second insulating film and the removed region have a line-and-space relationship, and the contact formation can be stabilized.

[Brief description of drawings]

【図１】第１実施例に係るビット線上置き型ＤＲＡＭの
メモリセルアレイ部の平面図である。FIG. 1 is a plan view of a memory cell array portion of a bit line top type DRAM according to a first embodiment.

【図２】図１のII−II線における断面図である。FIG. 2 is a sectional view taken along line II-II in FIG.

【図３】第１実施例に係るＤＲＡＭメモリセルアレイ部
の製造工程における変化を示す断面図である。FIG. 3 is a cross-sectional view showing a change in a manufacturing process of the DRAM memory cell array portion according to the first embodiment.

【図４】第２実施例に係るビット線上置き型ＤＲＡＭの
メモリセルアレイ部の平面図である。FIG. 4 is a plan view of a memory cell array portion of a bit line top type DRAM according to a second embodiment.

【図５】第３実施例に係るビット線上置き型ＤＲＡＭの
メモリセルアレイ部の平面図である。FIG. 5 is a plan view of a memory cell array portion of a bit line top type DRAM according to a third embodiment.

【図６】図５のVI−VI線における断面図である。6 is a sectional view taken along line VI-VI in FIG.

【図７】素子分離の最小分離幅の部分に第２絶縁膜が形
成されていない場合の図６と同じ部位における断面図で
ある。7 is a cross-sectional view of the same portion as FIG. 6 in the case where a second insulating film is not formed in a portion having a minimum isolation width for element isolation.

【図８】第３実施例の変形例に係るＤＲＡＭのメモリセ
ルアレイ部の平面図である。FIG. 8 is a plan view of a memory cell array section of a DRAM according to a modification of the third embodiment.

【図９】第４実施例に係るビット線上置き型ＤＲＡＭの
メモリセルアレイ部の平面図である。FIG. 9 is a plan view of a memory cell array portion of a bit line top type DRAM according to a fourth embodiment.

【図１０】図９のX −X 線における断面図である。10 is a cross-sectional view taken along line XX of FIG.

【図１１】第２絶縁膜の除去部領域がプレート電極を形
成しようとする領域の外方にはみ出している場合におけ
る図１０と同じ部位における断面図である。11 is a cross-sectional view of the same portion as FIG. 10 in the case where the removed portion region of the second insulating film extends outside the region where the plate electrode is to be formed.

【図１２】第５実施例に係るビット線下置き型ＤＲＡＭ
のメモリセルアレイ部の平面図である。FIG. 12 is a bit line lower type DRAM according to a fifth embodiment.
3 is a plan view of the memory cell array section of FIG.

【図１３】図１２のXIII−XIII線における断面図であ
る。13 is a sectional view taken along line XIII-XIII in FIG.

【図１４】従来のビット線上置き型ＤＲＡＭのメモリセ
ルアレイ部の平面図である。FIG. 14 is a plan view of a memory cell array portion of a conventional bit line top type DRAM.

【図１５】図１４のXV−XV線における断面図である。15 is a sectional view taken along line XV-XV in FIG.

【図１６】フォトリソグラフィー工程におけるマスクず
れが生じた場合における第２絶縁膜の除去領域Ｒetの状
態を示す平面図である。FIG. 16 is a plan view showing a state of a second insulating film removal region Ret when a mask shift occurs in a photolithography process.

[Explanation of symbols]

１半導体基板２ドレイン領域（拡散領域）３ソース領域（拡散領域）４素子分離（分離絶縁膜）５ワード線（配線部材）６ゲート酸化膜７ゲート電極８スイッチングトランジスタ（半導体素子）９ａサイドウォール９ｂ上面保護膜９第１絶縁膜１１容量蓄積電極コンタクト（コンタクト部材）１２第２絶縁膜１３容量蓄積電極（導電性部材）１４容量絶縁膜（誘電体膜）１５プレート電極３０ビット線（導電性部材）３１ビット線コンタクト（コンタクト部材）３２層間絶縁膜 1 semiconductor substrate 2 drain region (diffusion region) 3 source region (diffusion region) 4 element isolation (isolation insulating film) 5 word line (wiring member) 6 gate oxide film 7 gate electrode 8 switching transistor (semiconductor device) 9a sidewall 9b Top surface protective film 9 First insulating film 11 Capacitive storage electrode contact (contact member) 12 Second insulating film 13 Capacitive storage electrode (conductive member) 14 Capacitive insulating film (dielectric film) 15 Plate electrode 30 Bit line (conductive member) ) 31 bit line contact (contact member) 32 interlayer insulating film

Claims

[Claims]

1. A semiconductor substrate, an isolation insulating film formed on the semiconductor substrate for partitioning a surface region of the semiconductor substrate into a plurality of active regions in which semiconductor elements are formed, and each of the active regions of the semiconductor substrate. A first diffusion region and a second diffusion region which are formed and are formed by diffusing impurities in a surface region of the semiconductor substrate; a wiring member provided on the semiconductor substrate in the active region; and a wiring member covering the surface of the wiring member. 1 insulating film, and the semiconductor substrate, the isolation insulating film, and the first insulating film, and at least a part of the region immediately above the first diffusion region is left over, and at least two second diffusion films are formed. A second insulating film from which a region including a region directly above the region is removed, a conductive member provided above the second diffusion region, and at least a part of the region from which the second insulating film is removed. Through the conductive The semiconductor device is characterized in that a contact member for connecting the member and the second diffusion region.

2. The semiconductor device according to claim 1, wherein a DRAM memory cell is provided in each active region of the semiconductor substrate, and the wiring member is a word line of the DRAM memory cell, The first diffusion region is a drain region of the DRAM memory cell, the second diffusion region is a source region of the DRAM memory cell, the conductive member is a capacitance storage electrode, and the contact member is the capacitance. A semiconductor device, which is a capacitance storage electrode contact that connects a storage electrode and a source region.

3. The semiconductor device according to claim 2, wherein the region from which the second insulating film has been removed includes a region directly above a plurality of source regions arranged in a direction substantially parallel to the word line. Characteristic semiconductor device.

4. The semiconductor device according to claim 2, wherein the region from which the second insulating film has been removed includes a region directly above a plurality of source regions arranged in a direction substantially orthogonal to the word line. Characteristic semiconductor device.

5. The semiconductor device according to claim 2, wherein the region where the second insulating film is removed includes a region directly above all the source regions in the DRAM memory cell in common.

6. The semiconductor device according to claim 2, 3, 4 or 5, wherein a bit line disposed above the capacitance storage electrode and a part of a second insulating film covering the drain region are provided. A semiconductor device having a bit line contact penetrating therethrough to connect the bit line to the drain region.

7. The semiconductor device according to claim 1, wherein a field effect transistor is provided in each active region of the semiconductor substrate, and the wiring member is a gate electrode of the field effect transistor. The first diffusion region is a source region of a field effect transistor, the second diffusion region is a drain region of a field effect transistor, the conductive member is a bit line, and the contact member is A bit line contact connecting the bit line and a drain region of the field effect transistor.

8. The semiconductor device according to claim 7, wherein the region from which the second insulating film is removed shares a region directly above a plurality of drain regions arranged in a direction parallel to a wiring member forming a gate electrode. A semiconductor device comprising:

9. A semiconductor substrate, an isolation insulating film formed on the semiconductor substrate for partitioning a surface region of the semiconductor substrate into a plurality of active regions in which semiconductor elements are formed, and each of the active regions of the semiconductor substrate. A first diffusion region and a second diffusion region formed by diffusing impurities in a surface region of the substrate;
A diffusion region, a wiring member provided on the semiconductor substrate in the active region, a first insulating film covering the surface of the wiring member, and formed on the semiconductor substrate, the first insulating film, and the isolation insulating film. A second insulating film having a plane pattern in which a region commonly including a region directly above at least two second diffusion regions is removed, and at least a part of the region immediately above the first diffusion region remains isolated. A contact connecting the conductive member and the second diffusion region via at least a part of the conductive member provided above the second diffusion region and the region where the second insulating film is removed. A semiconductor device comprising: a member.

10. The semiconductor device according to claim 9, wherein the second insulating film has an island-shaped plane pattern in which a remaining portion is isolated in each region immediately above each first diffusion region. .

11. The semiconductor device according to claim 9, wherein the second insulating film has a linear planar pattern in which the remaining portion commonly includes a region immediately above a plurality of first diffusion regions arranged in a predetermined direction. A semiconductor device characterized by the above.

12. The semiconductor device according to claim 1, wherein the second insulating film is a region directly above a portion of the minimum isolation width of the isolation insulating film sandwiched between the first diffusion regions of each active region. A semiconductor device characterized by remaining in.

13. A step of forming an isolation insulating film for partitioning a surface region of a semiconductor substrate into a plurality of active regions in which semiconductor elements are formed, and wiring in a region including at least a part of each active region of the semiconductor substrate. A step of forming a first insulating film covering the member and its surface; a step of introducing impurities into the active region to form a first diffusion region and a second diffusion region; After depositing the insulating film on the film and the isolation insulating film, of the deposited insulating film, at least a region immediately above the first diffusion region is left and at least two regions immediately above the second diffusion region are shared. Forming a second insulating film by removing the region including the conductive member, and a conductive member and a contact member connecting the conductive member and the first diffusion region above the second diffusion region. And the process of forming The method of manufacturing a semiconductor device according to claim.

14. The method of manufacturing a semiconductor device according to claim 13, wherein a word line of a DRAM memory cell is formed as the wiring member, a drain region of the DRAM memory cell is formed as the first diffusion region, and the second region is formed. A source region of the DRAM memory cell is formed as a diffusion region, a capacitance storage electrode is formed as the conductive member, and a capacitance storage electrode contact connecting the capacitance storage electrode and the source region of the DRAM memory cell is formed as the contact member. A method of manufacturing a semiconductor device, comprising:

15. The method of manufacturing a semiconductor device according to claim 14, wherein in the step of forming the second insulating film, a plurality of deposited insulating films are arranged in a direction substantially parallel to the word line. A method of manufacturing a semiconductor device, comprising: removing a region which commonly includes a region directly above a source region.

16. The method of manufacturing a semiconductor device according to claim 14, wherein in the step of forming the second insulating film, a plurality of deposited insulating films are arranged in a direction substantially orthogonal to the word line. A method of manufacturing a semiconductor device, comprising: removing a region which commonly includes a region directly above a source region.

17. The method of manufacturing a semiconductor device according to claim 14, wherein in the step of forming the second insulating film, a region directly above all source regions in the DRAM memory cell in the deposited insulating film is formed. A method of manufacturing a semiconductor device, which comprises removing a region which is commonly included.

18. The method for manufacturing a semiconductor device according to claim 14, 15, 16 or 17, wherein a step of forming a peripheral circuit of the DRAM memory cell and a step of forming a dielectric film on the capacitance storage electrode. And a step of forming a plate electrode on the dielectric film, wherein in the step of forming the second insulating film, the removed region of the second insulating film is inside the region where the plate electrode is to be formed. A method for manufacturing a semiconductor device, which is characterized in that it is formed as described above.

19. The method of manufacturing a semiconductor device according to claim 13, wherein a gate electrode of a field effect transistor is formed as the wiring member, and a source region of the field effect transistor is formed as the first diffusion region, A drain region of the field effect transistor is formed as the second diffusion region, a bit line is formed as the conductive member, and a bit line contact connecting the bit line and the drain region of the field effect transistor is formed as the contact member. A method of manufacturing a semiconductor device, comprising:

20. The method of manufacturing a semiconductor device according to claim 19, wherein, in the step of forming the second insulating film, a plurality of drain regions are provided directly above a plurality of drain regions arranged in a direction substantially parallel to a wiring member forming a gate electrode. A method for manufacturing a semiconductor device, which comprises removing a region including a region in common.