JPH07296589A - Semiconductor storage - Google Patents

Abstract

PURPOSE:To reduce occupancy area of a bit line and to improve an integrated degree of a memory cell array by sharing the bit line to memory cells adjacent in the direction of column. CONSTITUTION:The memory cells M1 and M2 adjacent in the direction of row are connected to word lines WL0, WL1 alternately, and constitute access gate transistors 2 and 3. When the cell M1 is selected, the word line WL0 and complementary bit lines B0,/B0 are used, and an address (0, 0) is shown. Further, when the cell M2 is selected, the word line WL1 and the complementary bit lines B1,/B1 are used, and the address (1, 1) is shown. Then, when the complementary bit lines B0,/B0, an even address may be selected as the word line always, and when the complementary bit lines B1,/B1, an odd address may be selected as the word line always. Thus, the occupancy area of the bit line is reduced, and the area of the memory cell array is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as a static RAM (hereinafter referred to as SRAM) having a higher degree of integration by sharing a bit line between adjacent memory cells.

[0002]

BACKGROUND OF THE INVENTION The development of SRAM began in 1969. Since then, the demand is rapid because the refresh operation is unnecessary and the operation timing is easy, even though it has the disadvantage that the integration degree is about 1/4 and the cost is higher than that of the dynamic RAM (hereinafter referred to as DRAM). Has spread to.

The structure of a conventional semiconductor memory device will be described with reference to the drawings. First, an SRAM using complementary bit lines will be described with reference to FIGS. 6 and 7. FIG. 6 is a diagram showing a conventional SRAM using complementary bit lines that connect two bit lines to each memory cell. FIG. 7 is a diagram showing the configuration of the memory cell of FIG.

In FIG. 6, 1 is a memory cell (M1 to M
9) 2 and 3 are access gate transistors of the memory cell 1. In addition, WL0, WL1 and WL2 are word lines made of polysilicon wiring, B0 and / B0 and B1.
And / B1 and B2 and / B2 are complementary bit lines made of aluminum wiring or the like.

In FIG. 7, 4 and 5 are power supplies Vcc and 6
Reference numerals 7 and 7 are high resistances serving as load elements, 8 and 9 are memory nodes, 10 and 11 are driver transistors of the memory cell 1, and 12 and 13 are GND. Note that WL is a word line, and B and / B are complementary bit lines.

Next, SRA using a single bit line
M will be described with reference to FIGS. 8 and 9. Figure 8
FIG. 6 is a diagram showing a conventional SRAM using a single bit line that connects one bit line to each memory cell.
Further, FIG. 9 is a diagram showing a configuration of the memory cell of FIG.

In FIG. 8, 1 is a memory cell (M1 to M
9) and 2 are access gate transistors of the memory cell 1. Also, WL0, WL1, WL2, and WL3 are word lines made of polysilicon wiring, B0, B1, and B.
2 and B3 are single bit lines made of aluminum wiring or the like.

In FIG. 9, 4 and 5 are power supplies Vcc and 6
Reference numerals 7 and 7 are high resistances serving as load elements, 8 and 9 are memory nodes, 10 and 11 are driver transistors of the memory cell 1, and 12 and 13 are GND. In addition, WL is a word line and B is a single bit line.

The above-described conventional SRAM has the memory cell 1
Two complementary bit lines B0, / B0, or one single bit line for each column (row) (for example, M1, M4, M7 in FIG. 6 or M1, M4, M7 in FIG. 8). Since B0 is provided, the size cannot be reduced because of the bit line even when it is desired to reduce the size in the direction parallel to the word line.
On the other hand, when the number of rows is large, there is a drawback that the overall size becomes large.

Therefore, an SRAM has been proposed in which the dimension in the direction parallel to the word lines can be reduced, and the overall dimension can be reduced when the number of columns is larger than the number of rows. Next, the proposed SRAM is shown in FIG. FIG. 10 is a diagram showing a conventional improved SRAM using complementary bit lines disclosed in, for example, Japanese Unexamined Patent Publication No. 2-270194.

However, the SRAM shown in FIG.
For example, the memory cells M1, M straddling the word line WL1
It is structurally unrealizable because the access gate transistors 2 and 3 of No. 3 and the access gate transistors 2 and 3 of the memory cells M4 and M6 are formed across the word line WL3.

Since the word line WL1 is provided as shown in FIG. 11, for example, the memory cell M3 cannot be connected to the word line WL0 across the word line WL1. That is, n + is injected into the word line made of polysilicon, so that n + does not enter below the word line. In addition, 14 shows a contact.

[0013]

In the conventional semiconductor memory device as described above, a complementary bit line connecting two bit lines for each memory cell is used, or one bit for each memory cell. Since a single bit line connecting the lines is used, there is a problem that the area of the memory cell array is large. Further, in the conventional semiconductor memory device in which the bit line is shared, the access gate transistor is attempted to be straddled over the word line, but there is a problem that it is structurally unrealizable.

The present invention has been made to solve the above-mentioned problems, and since it is composed of metal wiring,
An object of the present invention is to obtain a semiconductor memory device in which the area occupied by a bit line, which is difficult to reduce the pattern size, can be reduced to reduce the area of the memory cell array, and which can be structurally realized.

[0015]

A semiconductor memory device according to claim 1 of the present invention is a semiconductor memory device having a memory cell array composed of a plurality of memory cells arranged in a matrix in the column and row directions, A bit line shared by the memory cells adjacent in the column direction,
Word lines that are alternately selected for each memory cell in the column direction are provided.

A semiconductor memory device according to a second aspect of the present invention comprises a complementary bit line shared by adjacent memory cells in the column direction, and two sets of word lines sandwiching each memory cell. Is.

A semiconductor memory device according to a third aspect of the present invention includes a single bit line shared by odd-numbered and even-numbered adjacent memory cells in the column direction.

A semiconductor memory device according to a fourth aspect of the present invention further comprises a circuit for selectively controlling a word line by a bit line selection signal.

[0019]

In the semiconductor memory device according to the first aspect of the present invention, since the bit line is shared by the memory cells adjacent to each other in the column direction, the occupied area of the bit line can be reduced and the integration degree of the memory cell array can be increased. it can.

In the semiconductor memory device according to the second aspect of the present invention, since the complementary bit lines are shared by the memory cells adjacent in the column direction, the area occupied by the complementary bit lines is reduced and the integration degree of the memory cell array is increased. be able to.

In the semiconductor memory device according to the third aspect of the present invention, since the single bit line is shared by the memory cells adjacent in the column direction, the area occupied by the single bit line is reduced and the integration degree of the memory cell array is increased. be able to.

In the semiconductor memory device according to the fourth aspect of the present invention, since the word line can be selectively controlled by the bit line selection signal, the operation timing when the bit line is shared can be simplified.

[0023]

【Example】

Example 1. The configuration of the first embodiment of the present invention will be described with reference to FIG. 1 is a diagram showing a structure of an SRAM using complementary bit lines according to a first embodiment of the present invention. The structure other than the complementary bit lines is the same as that of the conventional device of FIG. 6 described above. In each figure, the same reference numerals indicate the same or corresponding parts.

In FIG. 1, complementary bit lines / B0 and B0
1, / B1 and B2, / B2 and B3 are shared,
Hereinafter, it is the same that the complementary bit lines are shared by the memory cells adjacent in the column direction.

As can be seen from FIG. 1, the memory cells 1 adjacent to each other in the row (column) direction, for example, the memory cells M1 and M2 are
Since the access gate transistors 2 and 3 are formed by alternately connecting to the upper and lower word lines WL0 and WL1, the access gate transistors 2 and 3 are not formed across the word lines. Therefore,
The first embodiment can be structurally realized because the number of complementary bit lines is reduced, the area of the memory cell array can be reduced accordingly, and it is not necessary to form the access gate transistor across the word lines.

Next, the operation of the above-described first embodiment will be described with reference to FIG. FIG. 2 is a diagram for explaining the memory cell decoder system according to the first embodiment of the present invention.

In FIG. 2, for example, when the memory cell M1 is selected, the word line WL0 and the complementary bit lines B0 and / B0 are selected.
Is used and is represented as an address "0,0". Further, for example, when the memory cell M2 is selected, the word line WL1 and the complementary bit lines B1 and / B1 are used and are represented by the address "1,1".
The same applies when other memory cells are selected.

Here, looking at the complementary bit lines B0 and / B0, the addresses are "0,0", "2,0", "4,0",
Lined with "...". Also, when viewed from the complementary bit lines B1 and / B1, the addresses are "1,1", "3,1", "5,1",
Lined with "...".

That is, when the complementary bit lines B0 and / B0 are used, the word line must be an even address (WL0, WL2, WL).
4, ...) and complementary bit lines B1, / B1
, The word line must be an odd address (WL1, WL3,
WL5, ...) may be selected.

Further, as will be described later, these word lines (WL0 and WL1), (WL2 and WL3), (W
The selection signals of L4 and WL5) (... Even address and odd address) may be the same signal transmitted from the same word line driver (decoder) (generally referred to as split word line).

According to the first embodiment, the complementary bit lines of the memory cells adjacent to each other in the row direction of the matrix memory cell array are shared, and the word lines are selected by alternately connecting the memory cells adjacent to each other in the row direction. As a result, the number of complementary bit lines can be reduced, and an SRAM having a small memory cell array area can be manufactured.

Example 2. The configuration of the second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a diagram showing the configuration of an SRAM using a single bit line according to the second embodiment of the present invention, and is the same as that of the conventional device of FIG. 8 described above except for the single bit line. In each figure, the same reference numerals indicate the same or corresponding parts.

In FIG. 3, single bit lines B0 and B
1 is shared. In the second embodiment, the bit lines and the word lines are further halved as compared with the first embodiment, and the layout pattern of the memory cell array has a margin (the number of lines is reduced) and the area of the memory cell array is reduced. be able to.

In FIG. 3, for example, when the memory cell M1 is selected, the word line WL0 and the single bit line B are selected.
Use 0. When selecting the memory cell M2, the word line WL1 and the single bit line B0 are used. The same applies when other memory cells are selected.

Example 3. A third embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a diagram showing the configuration of the third embodiment of the present invention. FIG. 5 is a diagram for explaining the operation of the third embodiment of the present invention.

In FIG. 4, reference numeral 15 is a Y0 address buffer, 16 is a Y0 decoder, and 17 is a word line driver (decoder). Further, 18 and 19 are P-channel transistors, and 20 and 21 are N-channel transistors. The memory cell portion is the same as that of the first embodiment and will be described.

In the third embodiment, one of two word lines is activated by using a Y address for selecting a bit line. As shown in FIG. 2, generally, the Y address (lower) selectively decodes the bit line (column direction), and the X address (upper) selectively decodes the word line (row direction).

FIG. 5 shows the level matrix of each part of the circuit shown in FIG. For example, when the Y0 input, which is the input of the Y0 address buffer 15, is 0 (low level), the outputs Y0 and / Y0 of the Y0 decoder 16 are Y0 = 0 and / Y0 = 1.

Then, the P-channel transistor 18
Is turned on, the N-channel transistor 20 is turned off, the selection signal of the word line driver 17 is transmitted to the word line WL0, and becomes active. The P-channel transistor 19
Is turned off, the N-channel transistor 21 is turned on, the word line WL1 becomes the GND level, and the word line WL1 is not selected.

On the other hand, when the Y0 input is 1 (high level), the above is reversed. By doing so, it becomes possible to select an even address or an odd address of the word line as desired depending on the selection condition of the Y address.

The third embodiment can simplify the operation timing as described above, and can be applied to the second embodiment. The transistor configuration shown in FIG. 4 is an example, and is incorporated in the logic portion of the word line driver 17, or the word line driver is connected to the left and right of the memory cell portion to individually set Y.
You may make it take a decoder and a logic.

[0042]

As described above, the semiconductor memory device according to the first aspect of the present invention is a semiconductor memory device having a memory cell array composed of a plurality of memory cells arranged in a matrix in the column and row directions. ,
Since the bit lines shared by the memory cells adjacent to each other in the column direction and the word lines alternately selected for each memory cell in the column direction are provided, the area occupied by the bit lines is reduced to reduce the memory cell array size. This has the effect of increasing the degree of integration.

In the semiconductor memory device according to the second aspect of the present invention, as described above, the complementary bit line shared by the memory cells adjacent to each other in the column direction and the two word lines sandwiching each memory cell are provided. Since it is provided, the area occupied by the complementary bit lines can be reduced and the integration degree of the memory cell array can be increased.

As described above, the semiconductor memory device according to the third aspect of the present invention includes the single bit line shared by the odd-numbered and even-numbered adjacent memory cells in the column direction. This has an effect that the occupied area can be reduced and the degree of integration of the memory cell array can be increased.

As described above, the semiconductor memory device according to the fourth aspect of the present invention further includes a circuit for selectively controlling the word line by the bit line selection signal, so that the operation timing when the bit line is shared is simple. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the first embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a second embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a third embodiment of the present invention.

FIG. 5 is a diagram for explaining the operation of the third embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a conventional semiconductor memory device.

FIG. 7 is a diagram showing a configuration of a memory cell of a conventional semiconductor memory device.

FIG. 8 is a diagram showing a configuration of another conventional semiconductor memory device.

FIG. 9 is a diagram showing a configuration of a memory cell of another conventional semiconductor memory device.

FIG. 10 is a diagram showing a configuration of another conventional semiconductor memory device.

11 is a diagram showing the structure of another conventional semiconductor memory device of FIG.

[Description of Reference Signs] 1 memory cell, 2 and 3 access gate transistors, 15 Y0 address buffer, 16 Y0 decoder, 17 word line driver, 18, 19 P-channel transistor, 20, 21 N-channel transistor.

Claims (4)

[Claims] 1. A semiconductor memory device having a memory cell array composed of a plurality of memory cells arranged in a matrix in a column and row directions, and a bit line shared by memory cells adjacent in the column direction, and A semiconductor memory device comprising word lines alternately selected for respective memory cells in a column direction. 2. The semiconductor memory device according to claim 1, wherein the bit line is a complementary bit line, and the word line is a set of two sandwiching each memory cell. 3. The semiconductor memory device according to claim 1, wherein the bit line is a single bit line and is shared by odd-numbered memory cells and even-numbered memory cells. 4. The circuit according to claim 1, further comprising a circuit for selectively controlling a word line according to a bit line selection signal.
4. The semiconductor memory device according to claim 3.