JPH03265167A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To realize low resistance and low capacity of a word line and to enable rapid selection of an arbitrary memory cell by using an aluminum layer which constitutes a memory cell group selecting signal line of division word line method for forming contact with the word line at a desired interval via contact holes. CONSTITUTION:A semiconductor device is composed of a division word line 1, an auxiliary word line 2 which consists of an aluminum layer for realizing low resistance of the line 1, a contact hole 3 for connecting the lines 1, 2, a memory cell group selecting line 4 which consists of an aluminum layer, a memory cell group 5a, an X decoder 6, and a sub-X decoder 7 for decoding the line 1 inside the memory cell group 5a. In a semiconductor memory device adopting a two layer aluminum line process, a first layer aluminum can be used as a bit line and a second layer aluminum can be used as a memory cell group selecting line of division word line selecting method. Since a second layer aluminum wiring is used only for the selecting line 4 of the memory cell group 5a in the memory cell region, other regions can be used freely. Therefore, it is possible to use the second layer aluminum line for forming contact with the word line at a desired interval via contact holes and to reduce wiring resistance.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device using a 2N aluminum interconnection process, in which a word line for selecting an arbitrary memory cell can be operated at high speed. This is related to the improvement of

[Conventional technology]

FIG. 3 is a conventional schematic diagram showing a method of connecting a word line formed of polysilicon and an aluminum layer at a desired interval (hereinafter referred to as the word line aluminum staking method). 1 is a word line made of polysilicon, 2 is a word line made of aluminum, 3 is a contact hole connecting the word lines 1 and 2, 5 is a memory cell area, and 6 is an X decoder. Note that in the actual device, word line 2 is located directly above word line 1, but
In FIG. 3, these positions are shown shifted for convenience of explanation.

FIG. 4 is a schematic diagram showing a conventional divided word line method in which the word line selection method is divided into arbitrary memory cell groups. In the figure, 53 is a divided memory cell group, and 1 is the memory cell group. 7 is a sub-X decoder for decoding the divided word line 1 in the divided memory cell group a, 4 is a selection line for selecting the memory cell group 5a, and 7 is a selection line for selecting the memory cell group 5a. It is configured. Note that in this figure as well, the divided word lines 1 and the memory cell group selection lines 4 are shown shifted in position as in FIG. 3.

Next, the operation will be explained.

The purpose of the word line aluminum piling method in Figure 3 is:
-The gate input capacitance of the memory cells connected to the word line is very large, and the resistance of the polysilicon 1 forming the word line is large, so by reducing the capacitance and the resistance of the polysilicon 1 itself, In this method, the polysilicon word line 1 and the aluminum layer N2 are connected via a contact hole 3 at a desired interval, and the above-mentioned purpose, that is, reduction of capacitance and resistance, is distantly related.

In addition, in the divided word line method shown in FIG. 4, in order to reduce the number of memory cells connected to - word lines, the memory cell array is divided into certain memory cell groups, and group selection is performed to first select a memory cell group. A line 4 is provided, and a sub-X decoder 7 for decoding the divided word line in the memory cell group is provided. As a result, the gate capacitance per word line is reduced, and the wiring length can be shortened by limiting the wiring area of the word line only within an arbitrary memory cell group.As a result, the wiring resistance is also reduced, achieving high-speed operation of the word line. has been done.

[Problem to be solved by the invention]

In the past, the two methods mentioned above were generally implemented as measures for high-speed word line operation, but as memory capacity increases, the word line wiring becomes longer, so the aluminum stake method alone is not sufficient. There was a problem in that the resistance of the polysilicon itself forming the word line could not be reduced.

Furthermore, the divided word line method also has a problem in that an increase in the wiring length of the memory cell group selection line due to an increase in the number of memory cells impedes high-speed operation of the word line.

This invention was made in order to solve the above-mentioned problems, and it is a semiconductor that can realize low resistance and low capacitance of word lines, and thereby can select any memory cell at high speed. The purpose is to obtain a storage device.

[Means to solve the problem]

In the semiconductor memory device according to the present invention, a memory cell array consisting of a plurality of memory cells is divided into predetermined memory cell groups, and a memory cell group selection line for selecting the memory cell group, and a In a memory device using a divided word line selection method having divided word lines for selecting cells, a conductive band layer constituting the word line and a metal wiring layer constituting a memory cell group selection line are connected at a desired interval. It is something.

[Effect]

In this invention, since the algorithm layer that constitutes the memory cell group selection signal line of the divided word line method is used for word line staking, the wiring area of the divided word line is only within the memory cell group, and the wiring length can be shortened. Not only that, but also the wiring resistance can be reduced. As a result, even if the memory capacity increases, high-speed word line operation can be maintained in a memory device that requires high-speed operation.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view for explaining a semiconductor memory device according to an embodiment of the present invention. In the figure, l is a divided word line formed of a polysilicon layer, and 2 is a lower resistance of the divided word line 1. The auxiliary word line 3 made of an aluminum layer is a contact hole for connecting the divided word line 1 and the auxiliary word line 2, and is formed at a predetermined interval in the direction of the word line. 4 is a memory cell group selection line made of an aluminum layer, 5a is a memory cell group, 6 is an X decoder, and 7 is a sub-X decoder for decoding the divided word line 1 within the divided memory cell group a. Note that although the divided word line 1, auxiliary word line 2, and memory cell group selection line 4 are shown shifted in position in this figure, in the actual device, the auxiliary word line 2 is formed in the direction of the divided word line. , this auxiliary word line 2 is made of the same aluminum layer as the memory cell group selection line 4.

FIG. 2 shows the circuit timing waveforms showing the rise time of the word line when the word line aluminum piling method and divided word line selection method of the present invention are used together, and when the conventional divided word line selection method is used. This is a comparison between using only the selection method.

Next, the effects will be explained.

In a semiconductor memory device using a two-layer aluminum wiring process, the first layer of aluminum can be used for bit lines, and the second layer of aluminum can be used for memory cell group selection lines in a divided word line selection method. In addition, in the memory cell area, the second N-th Al ξ
Since the wiring is used only for the selection line 4 of the memory cell group 5a, other areas can be used freely.

Therefore, in FIG. 1, the divided word line 1 is staked out using the metal layer that forms the bottom of the memory cell group selection line 4, that is, the second layer aluminum, and the auxiliary word line 2 of the aluminum layer is
By realizing this, the divided word line selection method and the word line aluminum stake driving method can be used together.

As a result, memory capacity has increased, and word line wiring resistance has increased.
Even if the gate capacitance increases, the word line can operate at high speed by combining the above two methods. Furthermore, it can be seen from FIG. 2 that by implementing the present invention, the rise time of the word line is sped up by about 10%.

In this way, in this embodiment, the aluminum layer of the memory cell group selection line 4 is used as a metal layer for staking the word line 1, so in other words, the aluminum staking method and the divided word line selection method are used together. Therefore, even as the capacity of memory cells increases, high-speed operation of word lines for selecting arbitrary memory cells becomes possible.

〔Effect of the invention〕

As described above, according to the semiconductor memory device according to the present invention,
Since the aluminum layer that forms the bottom of the memory cell group selection signal line in the divided word line method is used for word line reinforcement, the wiring area for the divided word line is only within the memory cell group, which not only shortens the wiring length, but also The wiring resistance can be reduced. As a result, even if the memory capacity increases, the word line can maintain high-speed operation in a memory device that requires high-speed operation.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing a tank bottom using a combination of the divided word line selection method and the word line aluminum piling method according to an embodiment of the present invention, and FIG. 2 shows the word line rise time using the method of the present invention. Figure 3 is a schematic diagram showing the conventional word line aluminum stake driving method, and Figure 4 is the conventional divided word line selection method. FIG. 3 is a schematic diagram showing a line selection method. 1... Divided word line formed of polysilicon, 2.
... Word line formed of aluminum, 3... Word line l
and 2, 4... memory cell group selection line, 5 memory cell area, 5a... memory cell group, 6... X decoder, 7 sub-X decoder. The same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A memory cell array consisting of a plurality of memory cells is divided into predetermined memory cell groups, and a memory cell group selection line for selecting the memory cell group and a memory cell group selection line for selecting a memory cell within the memory cell group are provided. In a semiconductor memory device of a divided word line selection method having a divided word line, a conductive layer is arranged at a constant interval in the word line direction and constitutes the word line and the memory cell selection line. 1. A semiconductor memory device comprising a plurality of connection parts that connect to a metal wiring layer.