JPS6263948U

JPS6263948U -

Info

Publication number: JPS6263948U
Application number: JP15534985U
Authority: JP
Priority date: 1985-10-11
Filing date: 1985-10-11
Publication date: 1987-04-21

Description

[Brief explanation of the drawing]

第１図は本考案の半導体記憶装置の平面図、第
２図は第１図の―線断面図、第３図は従来例
の平面図、第４図は従来例の断面図、第５図は比
較例の平面図、第６図は第５図の―線断面図
である。１……平坦領域、２……ワードライン（信号線
）、３……低抵抗配線層、４……コンタクト孔、
５……ビツトライン、６……メモリセル。 FIG. 1 is a plan view of the semiconductor memory device of the present invention, FIG. 2 is a sectional view taken along the line -- in FIG. 1, FIG. 3 is a plan view of the conventional example, FIG. 4 is a sectional view of the conventional example, and FIG. 5 6 is a plan view of a comparative example, and FIG. 6 is a sectional view taken along the line -- in FIG. 1... Flat region, 2... Word line (signal line), 3... Low resistance wiring layer, 4... Contact hole,
5...Bit line, 6...Memory cell.

Claims

[Claims for Utility Model Registration] In a semiconductor memory device in which a signal line is formed of a polycrystalline semiconductor material and is composed of a memory cell composed of one capacitor and one transistor, a flat surface for contact outside the memory cell is provided for each plurality of cells. A semiconductor memory device in which a signal line and a low resistance wiring layer arranged in parallel with the signal line are connected in the flat area.