JPS61149340U - - Google Patents
Info
- Publication number
- JPS61149340U JPS61149340U JP3176985U JP3176985U JPS61149340U JP S61149340 U JPS61149340 U JP S61149340U JP 3176985 U JP3176985 U JP 3176985U JP 3176985 U JP3176985 U JP 3176985U JP S61149340 U JPS61149340 U JP S61149340U
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- cell
- channel
- gate array
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009792 diffusion process Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
第１図は、本考案の一実施例を示す平面的位置
関係図であり、第２図は、第１図のＡ―Ａ線の断
面を示す断面図である。第３図は、一従来例を示
す平面的位置関係図であり、第４図は、第３図の
Ｂ―Ｂ線による断面を示す断面図である。
１１……基板、１２……拡散層、１３……ゲー
ト、１４……セル内の配線、１５……中間配線、
１６……チヤンネル配線、１７……絶縁層、１８
……コンタクトホール。
FIG. 1 is a planar positional diagram showing an embodiment of the present invention, and FIG. 2 is a sectional view taken along line AA in FIG. 1. FIG. 3 is a planar positional relationship diagram showing a conventional example, and FIG. 4 is a sectional view taken along the line BB in FIG. 3. 11... Substrate, 12... Diffusion layer, 13... Gate, 14... Wiring within the cell, 15... Intermediate wiring,
16...Channel wiring, 17...Insulating layer, 18
...Contact hole.
Claims (1)
れてセルをなし、セル内の配線およびチヤンネル
配線ならびに前記セル内の配線と前記チヤンネル
配線を結ぶ中間配線により各々の前記セルを集積
配線してなるゲートアレーに於いて、 前記セル内の配線および前記チヤンネル配線な
らびに前記中間配線が各々別の層をなし、各々の
層と層の間や層と拡散層やゲートの間をコンタク
トホールにより導通配線してなる事を特徴とする
ゲートアレー。[Claims for Utility Model Registration] A transistor is formed by a diffusion layer and a gate of a substrate to form a cell, and each cell is formed by a wiring within the cell, a channel wiring, and an intermediate wiring connecting the wiring within the cell and the channel wiring. In a gate array formed by integrated wiring of A gate array characterized by conductive wiring through contact holes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3176985U JPS61149340U (en) | 1985-03-06 | 1985-03-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3176985U JPS61149340U (en) | 1985-03-06 | 1985-03-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61149340U true JPS61149340U (en) | 1986-09-16 |
Family
ID=30532671
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3176985U Pending JPS61149340U (en) | 1985-03-06 | 1985-03-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61149340U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH022163A (en) * | 1988-06-13 | 1990-01-08 | Matsushita Electron Corp | Master-slice type semiconductor integrated circuit device and its manufacture |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5929440A (en) * | 1982-08-11 | 1984-02-16 | Hitachi Ltd | Semiconductor integrated circuit device |
-
1985
- 1985-03-06 JP JP3176985U patent/JPS61149340U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5929440A (en) * | 1982-08-11 | 1984-02-16 | Hitachi Ltd | Semiconductor integrated circuit device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH022163A (en) * | 1988-06-13 | 1990-01-08 | Matsushita Electron Corp | Master-slice type semiconductor integrated circuit device and its manufacture |