JPH0231150U - - Google Patents
Info
- Publication number
- JPH0231150U JPH0231150U JP10958688U JP10958688U JPH0231150U JP H0231150 U JPH0231150 U JP H0231150U JP 10958688 U JP10958688 U JP 10958688U JP 10958688 U JP10958688 U JP 10958688U JP H0231150 U JPH0231150 U JP H0231150U
- Authority
- JP
- Japan
- Prior art keywords
- row address
- line
- write area
- lines
- column address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010408 film Substances 0.000 claims description 5
- 239000010409 thin film Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Thin Film Transistor (AREA)
Description
第１図〜第５図は本考案の一実施例を示したも
ので、第１図は薄膜マスクＲＯＭのメモリ・マト
リツクス部の一部分の平面図、第２図および第３
図は第１図の―線および―線に沿う断面
図、第４図は薄膜マスクＲＯＭの製造工程図、第
５図は薄膜マスクＲＯＭの回路図である。
１０……絶縁基板、１１……ロー・アドレスラ
イン、１２……絶縁膜、１３……カラム・アドレ
スライン、１４……接地ライン、１５……半導体
膜、Ａ……書込み領域、Ｔ……薄膜トランジスタ
。
1 to 5 show an embodiment of the present invention, in which FIG. 1 is a plan view of a portion of the memory matrix portion of a thin film mask ROM, and FIGS.
The figures are cross-sectional views taken along lines - and - in Fig. 1, Fig. 4 is a manufacturing process diagram of the thin film mask ROM, and Fig. 5 is a circuit diagram of the thin film mask ROM. 10...Insulating substrate, 11...Row address line, 12...Insulating film, 13...Column address line, 14...Grounding line, 15...Semiconductor film, A...Writing area, T...Thin film transistor .
Claims (1)
ドレスラインと、このロー・アドレスラインと直
交しかつ互いに隣り合う複数本のカラム・アドレ
スラインおよび接地ラインとを、その間に絶縁膜
をはさんで配列形成し、前記ロー・アドレスライ
ンと、隣り合うカラム・アドレスラインおよび接
地ラインとの対向部分をそれぞれ１ビツト分の書
込み領域とするとともに、この各書込み領域のう
ちの所定の書込み領域に、前記絶縁膜を介して前
記ロー・アドレスラインと対向しかつ両側部にお
いて前記カラム・アドレスラインおよび接地ライ
ンに接続された半導体膜を形成したことを特徴と
する薄膜マスクＲＯＭ。 On an insulating substrate, a plurality of row address lines parallel to each other and a plurality of column address lines and ground lines that are perpendicular to the row address lines and adjacent to each other are placed on an insulating substrate, with an insulating film sandwiched between them. The opposing portions of the row address line and the adjacent column address line and ground line are each used as a write area for one bit, and a predetermined write area of each write area is filled with the A thin film mask ROM characterized in that a semiconductor film is formed opposite to the row address line via an insulating film and connected to the column address line and the ground line on both sides.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10958688U JPH0231150U (en) | 1988-08-23 | 1988-08-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10958688U JPH0231150U (en) | 1988-08-23 | 1988-08-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0231150U true JPH0231150U (en) | 1990-02-27 |
Family
ID=31345964
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10958688U Pending JPH0231150U (en) | 1988-08-23 | 1988-08-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0231150U (en) |
-
1988
- 1988-08-23 JP JP10958688U patent/JPH0231150U/ja active Pending
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