JPH01146399U - - Google Patents
Info
- Publication number
- JPH01146399U JPH01146399U JP3904888U JP3904888U JPH01146399U JP H01146399 U JPH01146399 U JP H01146399U JP 3904888 U JP3904888 U JP 3904888U JP 3904888 U JP3904888 U JP 3904888U JP H01146399 U JPH01146399 U JP H01146399U
- Authority
- JP
- Japan
- Prior art keywords
- capacitors
- rows
- columns
- group
- tentacles
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
Description
第１図ａは本考案のメモリ部の断面図、第１図
ｂは第１図ａの平面図、第１図ｃは接触電極と触
針の配列を示す図、第２図は書き込みまたは読み
出し回路とキヤパシタの接続を示す図。
図中、１……絶縁基板、２……共通電極、３…
…絶縁膜、４……キヤパシタ電極、５……接触電
極、６……外部基板、７……触針、８……スライ
ド面。
Figure 1a is a sectional view of the memory section of the present invention, Figure 1b is a plan view of Figure 1a, Figure 1c is a diagram showing the arrangement of contact electrodes and stylus, and Figure 2 is for writing or reading. A diagram showing the connection between a circuit and a capacitor. In the figure, 1... insulating substrate, 2... common electrode, 3...
... Insulating film, 4 ... Capacitor electrode, 5 ... Contact electrode, 6 ... External substrate, 7 ... Stylus, 8 ... Slide surface.
Claims (1)
たキヤパシタ群と、外部基板上に、一定間隔に配
列した触手群と、書き込みまたは読み出し回路と
を有し、相隣れる前記触手は、行および列ともに
キヤパシタの複数個おきに配列され、かつ、行方
向には１列、列方向に１行同一方にずれたキヤパ
シタに対応するように配列され、前記外部基板を
一軸方向に移動することによつて情報の書き込み
または読み出しを行うメモリ装置。 A group of capacitors arranged at regular intervals in both rows and columns on a substrate, a group of tentacles arranged at regular intervals on an external substrate, and a writing or reading circuit, and the adjacent tentacles are arranged in rows and columns. Both are arranged at intervals of a plurality of capacitors, and are arranged so as to correspond to capacitors shifted one column in the row direction and one row in the column direction, and by moving the external board in the uniaxial direction. A memory device that writes or reads information.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3904888U JPH01146399U (en) | 1988-03-26 | 1988-03-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3904888U JPH01146399U (en) | 1988-03-26 | 1988-03-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01146399U true JPH01146399U (en) | 1989-10-09 |
Family
ID=31265575
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3904888U Pending JPH01146399U (en) | 1988-03-26 | 1988-03-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01146399U (en) |
-
1988
- 1988-03-26 JP JP3904888U patent/JPH01146399U/ja active Pending
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