JPS5995378U

JPS5995378U - display panel

Info

Publication number: JPS5995378U
Application number: JP19190782U
Authority: JP
Inventors: 沖　賢一; 泰史大川; 高原　和博; 権藤　浩之; 三浦　照信
Original assignee: 富士通株式会社
Priority date: 1982-12-17
Filing date: 1982-12-17
Publication date: 1984-06-28

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図ａは従来の表示パネルの構成を説明するための模
式的な斜視図で、第１図すはその一部拡大図、第２図は
上述の表示パネルの従来の構成を示す電気的等価回路図
、第３図は本考案に基づ（表示パネルの構造を示す・も
ので、第３図ａは基板の表面を示す斜視図、第３図す、
　　ｃは表示パネルの基板の表面１と裏面１ａとを接続
する構造例を示す斜視図、第３図ｄ、　　ｅは基板の裏
面を示す平面図と側面図である。図において、１は表示パネル基板表面、１ａは表示パネ
ル基板裏面、２，３はトランジスタ、４　　　　　゛は
コンデンサ、５は画素電極、６は表示媒体、７は透明共
通前面電極、８１よテクテイブマトリックス回路、９は
アドレス回路、１０は表示領域、１１は接続端子、１２
は基板縁の溝、１３はスルーホール、１４は接続配線、
１５は接続ピンをそれぞれ示す。FIG. 1a is a schematic perspective view for explaining the configuration of a conventional display panel, FIG. 1 is a partially enlarged view, and FIG. The equivalent circuit diagram, FIG. 3, is based on the present invention (showing the structure of the display panel), and FIG. 3a is a perspective view showing the surface of the board, and FIG.
3c is a perspective view showing an example of a structure for connecting the front surface 1 and the back surface 1a of the substrate of the display panel, and FIGS. 3 d and 3 e are a plan view and a side view showing the back surface of the substrate. In the figure, 1 is the front surface of the display panel substrate, 1a is the back surface of the display panel substrate, 2 and 3 are transistors, 4 is a capacitor, 5 is a pixel electrode, 6 is a display medium, 7 is a transparent common front electrode, 81 is a protective matrix circuit, 9 is an address circuit, 10 is a display area, 11 is a connection terminal, 12
is a groove on the edge of the board, 13 is a through hole, 14 is a connection wiring,
15 indicates connection pins, respectively.

Claims

[Scope of utility model registration request]

A common electrode is provided on a plurality of pixel electrodes regularly arranged on the surface of a common substrate via a display medium, and an active matrix circuit for the pixel electrodes is integrally formed, and the back surface of the substrate is An address circuit for distributing display information to each of the pixel electrodes is formed to be connected to the active matrix circuit.