JPH0288206U - - Google Patents
Info
- Publication number
- JPH0288206U JPH0288206U JP16960388U JP16960388U JPH0288206U JP H0288206 U JPH0288206 U JP H0288206U JP 16960388 U JP16960388 U JP 16960388U JP 16960388 U JP16960388 U JP 16960388U JP H0288206 U JPH0288206 U JP H0288206U
- Authority
- JP
- Japan
- Prior art keywords
- chip resistor
- insulating substrate
- dimension
- resistor
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Details Of Resistors (AREA)
- Non-Adjustable Resistors (AREA)
Description
第１図は本考案の一実施例による３連チツプ抵
抗器の平面図、第２図は本発明考案の他の実施例
による多連チツプ抵抗器の平面図、第３図は多連
チツプ抵抗器の抗折強度データを示す図、第４図
は従来の多連チツプ抵抗器の一部を示す図である
。
１……絶縁性基板、２ａ〜４ｂ，２０ａ，２０
ｂ，３０ａ，３０ｂ……電極、５，６，７……抵
抗体、１０ａ，１０ｂ，１１ａ，１１ｂ……切欠
き。
FIG. 1 is a plan view of a triple chip resistor according to an embodiment of the present invention, FIG. 2 is a plan view of a multiple chip resistor according to another embodiment of the present invention, and FIG. 3 is a plan view of a multiple chip resistor according to another embodiment of the present invention. FIG. 4 is a diagram showing a part of a conventional multiple chip resistor. 1... Insulating substrate, 2a to 4b, 20a, 20
b, 30a, 30b... electrode, 5, 6, 7... resistor, 10a, 10b, 11a, 11b... notch.
Claims (1)
形成された抵抗体とが、絶縁性基板上に複数組並
設されてなる多連チツプ抵抗器において、 前記絶縁性基板には、前記抵抗体が並設された
第１の方向と直交する第２の方向の両側部に、相
互に対向するように切欠きが形成されており、 この切欠き形成部の第２方向の寸法が、前記絶
縁性基板の第２方向の全寸法に対して、５０〜９
０％となつている 多連チツプ抵抗器。[Claims for Utility Model Registration] A multiple chip resistor in which a plurality of sets of opposing electrodes and a resistor formed to connect these electrodes are arranged in parallel on an insulating substrate, Notches are formed in the magnetic substrate so as to face each other on both sides in a second direction perpendicular to the first direction in which the resistors are arranged, and The dimension in two directions is 50 to 9 with respect to the total dimension in the second direction of the insulating substrate.
Multi-chip resistor with 0%.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16960388U JPH0288206U (en) | 1988-12-27 | 1988-12-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16960388U JPH0288206U (en) | 1988-12-27 | 1988-12-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0288206U true JPH0288206U (en) | 1990-07-12 |
Family
ID=31459814
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16960388U Pending JPH0288206U (en) | 1988-12-27 | 1988-12-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0288206U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001143913A (en) * | 1999-11-11 | 2001-05-25 | Matsushita Electric Ind Co Ltd | Multiple chip resistor |
-
1988
- 1988-12-27 JP JP16960388U patent/JPH0288206U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001143913A (en) * | 1999-11-11 | 2001-05-25 | Matsushita Electric Ind Co Ltd | Multiple chip resistor |