JPS63188908U - - Google Patents
Info
- Publication number
- JPS63188908U JPS63188908U JP8179687U JP8179687U JPS63188908U JP S63188908 U JPS63188908 U JP S63188908U JP 8179687 U JP8179687 U JP 8179687U JP 8179687 U JP8179687 U JP 8179687U JP S63188908 U JPS63188908 U JP S63188908U
- Authority
- JP
- Japan
- Prior art keywords
- end electrodes
- resistor
- substrate
- electrodes
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 3
- 239000012528 membrane Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Non-Adjustable Resistors (AREA)
Description
第１図ないし第４図は本考案にかかるチツプ型
ネツトワーク抵抗器の実施例を示し、第１図は第
１実施例の概略構造を示す斜視図、第２図はその
等価回路図であり、第３図は第２実施例の概略構
造を示す斜視図、第４図はその等価回路図である
。また、第５図および第６図は従来例としてのチ
ツプ型抵抗器を示し、第５図はその概略構造を示
す斜視図、第６図はその等価回路図である。
１０……チツプ型ネツトワーク抵抗器、１１…
…絶縁基板、１４，１５……端部電極、１６……
抵抗膜。
1 to 4 show an embodiment of a chip type network resistor according to the present invention, FIG. 1 is a perspective view showing a schematic structure of the first embodiment, and FIG. 2 is an equivalent circuit diagram thereof. , FIG. 3 is a perspective view showing the schematic structure of the second embodiment, and FIG. 4 is its equivalent circuit diagram. 5 and 6 show a chip resistor as a conventional example, FIG. 5 is a perspective view showing its schematic structure, and FIG. 6 is an equivalent circuit diagram thereof. 10... Chip type network resistor, 11...
...Insulating substrate, 14, 15... End electrode, 16...
Resistive film.
Claims (1)
るとともに、前記基板の主面上で対向する端部電
極間に抵抗膜を形成し、かつ少なくとも２つの隣
接する端部電極を前記抵抗膜および対向する端部
電極を介して接続したことを特徴とするチツプ型
ネツトワーク抵抗器。 Three or more end electrodes are formed at the end of the insulating substrate, a resistive film is formed between the opposing end electrodes on the main surface of the substrate, and at least two adjacent end electrodes are connected to the resistor. A chip-type network resistor characterized in that it is connected through a membrane and opposing end electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8179687U JPS63188908U (en) | 1987-05-28 | 1987-05-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8179687U JPS63188908U (en) | 1987-05-28 | 1987-05-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63188908U true JPS63188908U (en) | 1988-12-05 |
Family
ID=30933858
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8179687U Pending JPS63188908U (en) | 1987-05-28 | 1987-05-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63188908U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52135048A (en) * | 1975-12-11 | 1977-11-11 | Toyo Dengu Seisakushiyo Kk | Method of making chip resistors |
-
1987
- 1987-05-28 JP JP8179687U patent/JPS63188908U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52135048A (en) * | 1975-12-11 | 1977-11-11 | Toyo Dengu Seisakushiyo Kk | Method of making chip resistors |