JPS62149234U - - Google Patents
Info
- Publication number
- JPS62149234U JPS62149234U JP1350987U JP1350987U JPS62149234U JP S62149234 U JPS62149234 U JP S62149234U JP 1350987 U JP1350987 U JP 1350987U JP 1350987 U JP1350987 U JP 1350987U JP S62149234 U JPS62149234 U JP S62149234U
- Authority
- JP
- Japan
- Prior art keywords
- electrodes
- insulating layer
- main surface
- substrate
- disposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 1
Landscapes
- Emergency Protection Circuit Devices (AREA)
Description
第１図Ａ，Ｂ，Ｃはそれぞれこの考案の実施例
の表面図、裏面図および側面図、第２図Ａは第１
図に示す構造に即した回路図、第２図Ｂは同第１
図の等価回路図である。
１……セラミツク誘電体基板、２〜５……電極
、６，７……絶縁層、８……チツプ型電圧非直線
抵抗、９……印刷型抵抗。
Figures 1A, B, and C are respectively a front view, a back view, and a side view of the embodiment of this invention, and Figure 2A is the first embodiment of the invention.
A circuit diagram according to the structure shown in the figure, Figure 2B is the same as the circuit diagram shown in Figure 1.
FIG. 2 is an equivalent circuit diagram of FIG. DESCRIPTION OF SYMBOLS 1... Ceramic dielectric substrate, 2-5... Electrode, 6, 7... Insulating layer, 8... Chip type voltage nonlinear resistance, 9... Printed type resistor.
Claims (1)
た第１、第２の電極と、この第１、第２の電極に
対向して上記基板の他方主面に形成された第３、
第４の電極と、上記第１、第２の電極間の上記一
方主面に形成された第１の絶縁層と、上記第３、
第４の電極間の上記他方主面に形成された第２の
絶縁層と、上記第１、第２の電極に接続され上記
第１の絶縁層上に配置された電圧非直線抵抗と、
上記第３、第４の電極に接続され上記第２の絶縁
層上に配置された抵抗とを有する複合型サージ吸
収器。 a dielectric substrate, first and second electrodes formed on one main surface of the substrate, and a third electrode formed on the other main surface of the substrate opposite to the first and second electrodes;
a fourth electrode, a first insulating layer formed on the one principal surface between the first and second electrodes;
a second insulating layer formed on the other main surface between the fourth electrodes; a voltage nonlinear resistor connected to the first and second electrodes and disposed on the first insulating layer;
and a resistor connected to the third and fourth electrodes and disposed on the second insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1350987U JPS6345811Y2 (en) | 1987-01-30 | 1987-01-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1350987U JPS6345811Y2 (en) | 1987-01-30 | 1987-01-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62149234U true JPS62149234U (en) | 1987-09-21 |
| JPS6345811Y2 JPS6345811Y2 (en) | 1988-11-29 |
Family
ID=30802634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1350987U Expired JPS6345811Y2 (en) | 1987-01-30 | 1987-01-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6345811Y2 (en) |
-
1987
- 1987-01-30 JP JP1350987U patent/JPS6345811Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6345811Y2 (en) | 1988-11-29 |
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