JPH06350057A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To enable high-speed operation by decreasing the resistance of a bit line of a memory cell region. CONSTITUTION:A plurality of conductive regions 11 laid out crossing a memory cell region have odd arrays extended to one end side, and even arrays to the other end side, and both ends are bent to form bends 12. Each array of conductive regions 11 which form a pair with one array in between is laid out with an auxiliary conductive region 13 adjacent to each bend 12. Conductive regions 11 are laid out with a plurality of gate electrodes 14 crossing the conductive regions 11 and with selective gate electrodes 16 extending over bends 12 and auxiliary conductive regions 13 of conductive regions 11. An aluminum wiring 21 laid out at every auxiliary conductive region 13 is connected to an auxiliary conductive region 12 to constitute a bit line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a structure of a memory cell of a read only memory.

[0002]

2. Description of the Related Art A read-only memory such as a mask ROM corresponds to a plurality of memory cells arranged in rows and columns.
A plurality of bit lines and word lines are arranged to cross each other. Generally, in the case of a ROM, one MOS transistor is associated with one memory cell, and data is determined by whether or not a transistor designated based on address data is turned on.
In such a read-only memory, for example, JP-A-3-
As disclosed in Japanese Patent No. 179775, there has been proposed a structure called a flat cell in which there is no isolation region for separating memory cells from each other and a bit line is formed of a diffusion layer.

FIG. 3 is a plan view of a memory cell portion of a conventional NOR type mask ROM, and FIG. 4 is a sectional view taken along line XX of FIG. On the surface portion of the P type silicon substrate 1, a plurality of conductive regions 2 in which N type impurities serving as bit lines are diffused are formed.
Are arranged in parallel with each other at regular intervals. The conductive region 2 is formed of P-type impurity ions such as arsenic (As).
It is formed by implanting ions and is configured to serve as a source and a drain of a transistor forming a memory cell.
On the silicon substrate 1 on which the conductive region 2 is formed, a plurality of gate electrodes 3 serving as word lines are arranged so as to intersect with the conductive region 2 via the gate insulating film 4, and the conductive region 2 forms an N channel. Form a MOS transistor T1. Then, in the channel region of the transistor T1 (the substrate region below the gate electrode 3), an impurity implantation region 5 for selectively injecting P-type impurities into a high concentration is formed in association with the write data. As a result, the threshold voltage of the specific transistor T1 can be changed,
It becomes possible to store data associated with the difference in operating characteristics of each transistor T1.

In the above memory device, since there is no isolation region such as LOCOS between the transistors forming the memory cell and the size of the memory cell can be reduced, it is suitable for large capacity. However, the silicon substrate 1 has N
Since the bit line is formed by the conductive region 2 formed by diffusing the type impurities, there is a problem that the resistance value and parasitic capacitance of the bit line itself become large, and high speed operation cannot be supported.

As a method for solving such a problem of the resistance value of the bit line and the parasitic capacitance, for example, Japanese Patent Laid-Open No. 4-3119
A semiconductor memory device as disclosed in Japanese Patent Publication No. 00 has been proposed. 5 and 6 are a plan view and a circuit diagram of the semiconductor memory device. Transistor T of memory cell
1, the same as in FIG. 3, the N-type conductive regions 2 formed in parallel to each other on the surface of the P-type substrate, and the gate electrodes 3 arranged in parallel to each other so as to intersect with the conductive regions 2. Composed of and.

Conductive region 2 is arranged so as to cross the memory cell region, and the odd columns extend to one end side and the even columns extend to the other end side. In the peripheral portion of the memory cell region where the conductive region 2 is formed, the auxiliary conductive region 6 adjacent to the end of the conductive region 2 is formed.
Are arranged corresponding to every two columns. The extended portion of the conductive region 2 is formed to be long (or short) every other row,
Corresponding to this, the auxiliary conductive region 6 is formed in an L shape. Then, two selection gate electrodes 7 made of polycrystalline silicon are arranged side by side between the extended portions of the conductive regions 2 and the auxiliary conductive regions 6 along with the gate electrodes 3. As a result, the selection transistor T2 having the extended portion of the conductive region 3 and the auxiliary conductive region 6 as the source and the drain is formed.

On the gate electrode 3 and the selection gate electrode 7, an aluminum wiring 8 to be a bit line is arranged in parallel with the conductive region 2 so as to correspond to each auxiliary conductive region 6, and the gate electrode 3 and the selection electrode are selected. It is connected to the auxiliary conductive region 6 through the contact hole 9 in the gap portion of the gate electrode 7. Therefore, when the selection transistor T2 is selectively turned on by the selection operation of the selection gate electrode 7, that is, by increasing the voltage of one of the pair of selection gate electrodes 7, the conductive region 2 passes through the auxiliary conductive region 6. Connected to the aluminum wiring 8 (bit line).

Transistor T1 constituting each memory cell
The gate electrodes 3 continuous in each row form word lines of n rows, and an n-bit selection signal WL based on row address data.
It is selectively activated by 1 to WLn. Similarly, the select transistor T2 has a common select gate electrode 7 for each row, and the select gate electrode 7 forms a select control line, and 4-bit select control signals SL1 to SL4 based on column address data. ON / OFF control is selectively performed by. The aluminum wiring 8 forms a main bit line and selects signals BL1 to BL4 based on column address data.
In response to this, it is selectively activated. That is, a power supply potential and a ground potential are applied to the two aluminum wirings 8 corresponding to the address data, and at the same time, the two selection transistors T2 connected to the aluminum wirings 8 are selectively turned on to turn on a specific conductive region. 2 is connected to the aluminum wiring 8 and the adjacent two rows of conductive regions 12 are activated. Here, for each aluminum wiring 8, the voltage applied in the selected state is not determined to be the power supply voltage or the ground voltage, and the power supply voltage and the ground voltage are switched depending on the combination of the selected bit lines. I am trying.

[0009]

In the above semiconductor memory device, the main bit line is the aluminum wiring 8.
Therefore, the resistance and capacitance of the bit line are reduced as compared with the case where the conductive region 2 is used as the bit line. However, since the conductive region 2 which is the sub bit line is connected to the aluminum wiring 8 which is the main bit line via the selection transistor T2, when the resistance value of this selection transistor T2 is high, the resistance value of the bit line is reduced. Although it is small, it has a problem that it cannot support high-speed operation.

Therefore, an object of the present invention is to reduce the resistance value of the bit line and also reduce the resistance value of the connection transistor connected to the bit line so that the operating speed can be increased.

[0011]

The present invention has been made in order to solve the above-mentioned problems, and a first characteristic is that a semiconductor substrate of one conductivity type and a surface portion of this semiconductor substrate are provided. A plurality of rows of conductive regions of opposite conductivity type arranged in parallel with each other at regular intervals, and two rows of the conductive regions adjacent to the ends of these conductive regions and forming a pair with one row sandwiched therebetween. A plurality of auxiliary conductive regions arranged corresponding to the plurality of gate electrodes, a plurality of gate electrodes intersecting the conductive region and arranged in parallel on the semiconductor substrate, an end of the conductive region and the auxiliary conductive region. And a conductive line arranged on the gate electrode and electrically connected to the auxiliary conductive region, respectively, and an end portion of the plurality of conductive regions is provided. , Alternately extended to one or the other side, Bent to the conductive region side portion adjacent is that the said auxiliary conductive regions are arranged along the bent portion.

A second feature is that the end portions of the plurality of conductive regions are alternately extended to one side or the other side, and the auxiliary conductive regions are two rows of extended portions of the conductive regions. In between, it is arranged along each said conductive region.

[0013]

According to the first feature of the present invention, the end portion of the conductive region is bent and arranged, and the auxiliary conductive region is arranged along this bent portion, so that the conductive region and the auxiliary conductive region face each other. Can be made longer, and the gate width of the select transistor formed between the conductive region and the auxiliary conductive region can be set wider. And according to the second feature,
By arranging the auxiliary conductive region between the portions where the ends of the conductive regions are extended, the width of the select gate electrode can be increased and the gate width of the select transistor between the conductive region and the auxiliary conductive region can be set wide. . Therefore, the on-resistance value of the select transistor that selectively connects the conductive region and the conductive line is reduced.

[0014]

1 is a plan view of a memory cell portion of a semiconductor memory device according to the present invention. The plurality of conductive regions 11 having the N-type conductivity are arranged in parallel to each other so as to cross the memory cell region on the P-type substrate, and the odd-numbered columns are extended outside one of the memory cell regions. The even columns extend outside the other region. The extended portions of these conductive regions 11 are bent so as to wrap around the ends of the adjacent conductive regions 11 to form bent portions 12. Also,
The conductive regions 11 form a pair sandwiching one row, and one of them extends longer than the other. In the region of the conductive region 11 outside the bent portion 12, the N-type auxiliary conductive region 13 is arranged apart from the bent portion 12 by a certain distance. The auxiliary conductive region 13 is associated with each of the two rows of conductive regions 11 forming a pair, and has a crank shape so that the distance between each of the conductive regions 11 and the bent portion 12 is constant.

On the substrate on which the conductive region 11 and the auxiliary conductive region 13 are formed, a plurality of gate electrodes 14 made of polycrystalline silicon are arranged in parallel with each other so as to intersect with the conductive region 11. As a result, the memory cell transistor T1 is configured with the adjacent conductive regions 11 as the source and the drain. The transistor T1 has the same structure as in FIG. 3, and a P-type impurity implantation region is selectively formed in the channel region of the transistor T1 so as to correspond to the data stored in the memory cell. Furthermore, the gate electrode 1
On both sides of 4, the selection gate electrodes 15 made of polycrystalline silicon are arranged in twos each so as to extend between the bent portion 12 of the conductive region 11 and the auxiliary conductive region 13. As a result, the selection transistor T2 having the conductive region 11 and the auxiliary conductive region 13 as the source and the drain is formed. By the way, by forming the bent portion 12, the conductive region 1 is formed.
When the distance between 1 or the auxiliary conductive region 13 becomes short, conduction occurs due to the action of the select gate electrode 15 even in a portion which should not act as a select transistor. Therefore, a high concentration P is formed in a portion other than where the selection transistor T2 is formed.
Type impurity implantation region 16 is provided, and the selection transistor T2
Conduction between the conductive regions 11 or the auxiliary conductive regions 13 in other portions is prevented.

Then, on the gate electrode 14 and the select gate electrode 15, aluminum wirings 17 serving as bit lines are arranged in parallel with the conductive region 11 via an insulating film. The aluminum wiring 17 is arranged for each pair of the conductive regions 11, that is, corresponding to the auxiliary conductive region 13, and is electrically connected to the auxiliary conductive region 14 through the contact hole 18 provided in the insulating film.

The above semiconductor memory device has the same circuit configuration as that of FIG. 6, and the selection control signal WL1 based on the row address data is applied to the word line formed by the gate electrode 14.
To WLn, and selection control signals SL1 to SL4 based on column address data are applied to the selection control line formed by the selection gate electrode 15. Then, a pair of bit lines is designated based on the column address data, and a power supply potential and an installation potential are applied to activate a specific memory cell transistor T1. Here, the gate width of the select transistor T2 is the conductive region 1
Since it is determined by the length of the bent portion 12 at the end of No. 1, if the bent portion 12 is set to be long, the resistance when the selection transistor T2 is turned on can be lowered.

FIG. 2 is a plan view showing another embodiment of the present invention. The memory cell region in which the memory cell transistor T1 is formed has the same structure as that of FIG. 1, and on the plurality of N-type conductive regions 11 arranged in parallel with each other, the plurality of gate electrodes 14 intersecting the conductive regions 11. Are arranged. Conductive region 1 arranged across the memory cell region
In No. 1, the odd columns extend to one end side of the memory cell region, and the even columns extend to the other end side. Between these extended portions 19 is parallel to the conductive region 11 and
An auxiliary conductive region 20 is formed adjacent to the end 19 of each conductive region 11. Further, two select gate electrodes 21 made of polycrystalline silicon are arranged in parallel with the gate electrodes 14 so as to intersect with the extended portions 19 of the conductive regions 11 and the auxiliary conductive regions 20. As a result, the selection transistor T2 having the selection gate electrode 21 as the gate and the auxiliary conductive region 20 and the extended portions 19 of the conductive regions 11 on both sides thereof as the source and the drain is formed. Although four transistors are formed by the two select gate electrodes 21 on both sides of the auxiliary conductive region 20, a P-type high-concentration impurity implantation region 22 is formed in the channel region of two of these transistors. I am trying not to operate it. Therefore, the selection operation of the selection gate electrode 21 can selectively operate the selection transistor T2,
Any of the conductive regions 11 adjacent to both sides of the auxiliary conductive region 20 can be electrically connected to the auxiliary conductive region 20.

Then, similarly to FIG. 1, on the gate electrode 11 and the select gate electrode 21, the aluminum wiring 23 serving as a bit line corresponds to the auxiliary conductive region 20 and the conductive region 1 is formed.
1 is arranged in parallel with 1 and is electrically connected to the auxiliary conductive region 20 through the contact hole 24. In the above semiconductor memory device, since the gate width of the selection transistor T2 is determined by the width of the selection gate electrode 21, the auxiliary conductive region 20 is formed long and the width of the selection gate electrode 21 is widened. The resistance when T2 is in the ON state can be lowered. In such a case, the gate width of the select transistor T2 can be widened without widening the intervals of the arrangement of the conductive regions 11 or the gate electrodes 14, so that the degree of integration of the memory cell region is not reduced. By the way, when the width of the select gate electrode 21 is increased, the action of the select gate electrode 21 may cause conduction between the conductive regions 11 even in a portion where the auxiliary conductive region 20 is not formed. P-type impurity implantation region 25 is provided in the
Continuity is prevented in parts other than 2.

In the above embodiments, the case where one auxiliary conductive region 13, 20 is connected to each bit line (aluminum wiring 18, 24) has been illustrated, but a plurality of auxiliary conductive regions are provided for each bit line. It is also possible to connect two or more conductive regions by connecting them. In this case, the selection transistor T2 can perform block selection, that is, selection to the conductive region connected to the bit line.

[0021]

According to the present invention, the resistance of the select transistor can be reduced in addition to the reduction of the resistance and the capacitance due to the reduction of the length of the conductive region. Therefore, the effect of reducing the resistance of the bit line can be fully utilized, the data determination period can be shortened, and high-speed operation can be supported.

Further, even if the gate width of the select transistor is widened, it is not necessary to widen the interval between the conductive regions of the memory cell region or the arrangement of the gate electrodes, and this does not hinder the improvement in the degree of integration.

[Brief description of drawings]

FIG. 1 is a plan view showing a memory cell portion of a semiconductor memory device of the present invention.

FIG. 2 is a plan view showing another embodiment of the present invention.

FIG. 3 is a plan view showing a memory cell portion of a conventional semiconductor memory device.

4 is a cross-sectional view of the memory cell of FIG.

FIG. 5 is a plan view showing a memory cell portion of a semiconductor memory device in which the resistance of a bit line is reduced.

FIG. 6 is a circuit diagram of the semiconductor memory device of FIG.

[Description of Reference Signs] 1 silicon substrate 2, 11 conductive region 3, 14 gate electrode 4 gate insulating film 5, 16, 22, 25 impurity implantation region 6, 13, 20 auxiliary conductive region 7, 15, 21 select gate electrode 8, 17,23 Aluminum wiring 9,18,24 Contact hole T1, T2 Transistor

Claims (2)

[Claims] 1. A semiconductor substrate of one conductivity type, a plurality of rows of conductive regions of opposite conductivity type arranged in parallel on a surface portion of the semiconductor substrate at regular intervals, and end portions of these conductive regions. A plurality of auxiliary conductive regions arranged corresponding to the conductive regions in two rows adjacent to each other and sandwiching one line therebetween, and arranged in parallel to each other on the semiconductor substrate so as to intersect with the conductive regions. A plurality of gate electrodes, a selection gate electrode disposed between the end of the conductive region and the auxiliary conductive region, and arranged on the gate electrode to electrically connect to the auxiliary conductive region. And a conductive wire to be connected,
The ends of the plurality of conductive regions are alternately extended to one side or the other side, and the extended portions are bent toward the adjacent conductive regions, and the auxiliary conductive regions are arranged along the bent portions. A semiconductor memory device characterized by the above. 2. A semiconductor substrate of one conductivity type, a plurality of rows of conductive regions of opposite conductivity type arranged in parallel on a surface portion of the semiconductor substrate at regular intervals, and end portions of these conductive regions. A plurality of auxiliary conductive regions arranged corresponding to the conductive regions in two rows adjacent to each other and sandwiching one line therebetween, and arranged in parallel to each other on the semiconductor substrate so as to intersect with the conductive regions. A plurality of gate electrodes, a selection gate electrode disposed between the end of the conductive region and the auxiliary conductive region, and arranged on the gate electrode to electrically connect to the auxiliary conductive region. And a conductive wire to be connected,
The ends of the plurality of conductive regions are alternately extended to one side or the other side, and the auxiliary conductive regions are arranged along the respective conductive regions between two extended portions of the conductive regions. A semiconductor memory device characterized by the above.