KR100317318B1 - Nonvolatile memory device and method for fabricating the same - Google Patents

Abstract

PURPOSE: A non-volatile memory device and a method for fabricating the same are provided to prevent a damage of a diffusion region between a selection transistor and a memory cell transistor and reduce a cell size. CONSTITUTION: A field oxide layer(33) is formed on a semiconductor substrate(31). A P well(32) is formed on a predetermined region of the semiconductor substrate(31). A selection gate line is formed on a selection transistor region. The first gate oxide layer(34a) is formed under the selection gate line. The second polysilicon layer(37) is formed on the selection gate line. An insulating layer(36) is formed under the second polysilicon layer(37). A floating gate is patterned on a cell transistor region. The second gate oxide layer is formed under the floating gate. A control gate line is formed thereon. An insulating layer(36) is formed under the control gate line. A plurality of source region and a plurality of drain region are formed an active region of the substrate(31). The first planarization protection layer(40) including the first contact hole is formed on the first selection gate line, the source region, and the drain region. A contact plug(42) is formed within the first contact hole. A conductive layer pattern(43) is contacted with the contact plug(42). The second planarization protection layer(45) including the second contact hole is formed on the conductive layer pattern(43). A metal line(46) is formed on the second planarization protection layer(45).

Description

Nonvolatile memory device and manufacturing method thereof {NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME}

The present invention relates to a nonvolatile memory device, and more particularly, to a nonvolatile memory device capable of preventing damage to a diffusion region between a selection transistor and a memory cell transistor and reducing a cell size, and a method of manufacturing the same.

A nonvolatile memory device is a metal on insulator (MOS) memory device in which information stored in a cell is retained even when a power supply is turned off. An application field of the nonvolatile memory device is to store a power-on program. It is used in a medium (for example, a built-in computer bios program, various equipment set-up programs, etc.), an operating program storage device of a vending machine / vending machine, a font storage medium such as a computer / printer, or a game machine.

In general, the nonvolatile memory may be classified into a mask ROM, a PROM, an EPROM, an EEPROM, and a flash EEPROM. Electrically Erasable and Programmable Read Only Memory) will be described.

First, a conventional nonvolatile memory device will be described with reference to the accompanying drawings.

FIG. 1 is a layout diagram of a conventional nonvolatile memory device, FIG. 2 is a structural diagram of line I-I of FIG. 1, FIG. 3 is a structure diagram of line II-II of FIG. 1, and FIG. 4 is of III-III of FIG. 1. This is a structural diagram on board.

1 through 4, a conventional EEPROM cell has a semiconductor substrate 10 composed of an active region and a field region, and an active region is defined as a selection transistor region A and a cell transistor region B. As shown in FIG. The first and second gate oxide films 12a and 12b having different thicknesses on the selection transistor region A and the cell transistor region B of the semiconductor substrate 10, and the first and second gate oxide films 12a and 12b of the selection transistor region A, respectively. The selection gate line 13a formed in one direction on the predetermined region of the two-gate oxide film 12a and the same direction as the selection gate line 13a on the predetermined region of the second gate oxide film 12b of the cell transistor region B. And a floating gate pattern 13b and an insulating layer 14 formed at predetermined intervals, and a control gate line 15a formed on the insulating layer 14 in the same direction as the floating gate pattern 13b.

In this case, an impurity diffusion region 17 opposite to the semiconductor substrate 10 is formed on both lower semiconductor substrates 10 of the selection gate line 13a, the floating gate pattern 13b, and the control gate line 15a. Is formed. In this case, the impurity diffusion region 17 is an impurity region to be used as a source and a drain.

In addition, the bit line 20 is formed to intersect the selection gate line 13a and the control gate line 15a.

Here, reference numerals 18 and 21 are first and second interlayer insulating films, 19 are bit line contact holes, 22 are select gate contact regions, and 23 are common source contact regions.

Referring to the accompanying drawings, a method of manufacturing a conventional nonvolatile memory device configured as described above is as follows.

5A to 5G are cross-sectional views of a process along the line IV-IV of FIG. 1.

First, in the conventional method of manufacturing a nonvolatile memory device, as shown in FIG. 5A, a field insulating film 11 is formed in a field region of a semiconductor substrate 10 defined as a selection transistor region A, a cell transistor region B, and a field region. To form. Thereafter, first and second gate oxide films 12a and 12b having different thicknesses are formed in the selection transistor region A and the cell transistor region B, respectively. At this time, the first gate oxide film 12a of the selection transistor region A is thicker than the second gate oxide film 12b of the cell transistor region B.

At this time, the second gate oxide film 12b formed in the cell transistor region B with a thin thickness is a tunneling oxide film.

As shown in FIG. 5B, a first polysilicon layer is deposited on the entire surface, and then, on the predetermined regions of the first and second gate oxide films 12a and 12b of the selection transistor region A and the cell transistor region B, respectively. The first polysilicon layer is selectively patterned (photolithography process + etching process). Accordingly, the selection gate line 13a is formed in the selection transistor region A, and the floating gate pattern 13b is formed in the cell transistor region B. Next, an insulating film 14 is formed over the first and second gate oxide films 12a and 12b including the selection gate line 13a and the floating gate pattern 13b. In this case, the insulating layer 14 is an insulating layer having an oxide nitride oxide (ONO) structure.

At this time, although not shown in the drawing, the floating gate pattern 13b is patterned in a horizontal direction and separated into a rectangular shape.

As shown in FIG. 5C, a second polysilicon layer 15 is deposited on the entire insulating film 14.

As shown in FIG. 5D, after applying the first photosensitive film PR1 on the second polysilicon layer 15, the first photosensitive film PR1 is selectively patterned by an exposure and development process. In this case, the patterned and removed portion is over the selection transistor region A and the cell transistor region B adjacent to the selection transistor region A. FIG. Afterwards, the second polysilicon layer 15 is selectively removed using the patterned first photoresist film PR1 as a mask, leaving only the insulating film 14 in the cell transistor region B.

In this case, when the second polysilicon layer 15 is left only on the region where the control gate line is to be formed to form the control gate line, the floating gate pattern 13b under the control gate line is etched and the selection gate line 13a may also be formed. Since it is etched and removed, only the second polysilicon layer 15 on the selection transistor region A is removed first.

Subsequently, as shown in FIG. 5E, the first photosensitive film PR1 is removed, and then a second photosensitive film PR2 is coated on the second polysilicon layer 15 including the insulating film 14. And patterning the second photoresist film PR2 to remain on the entire surface of the selection transistor region A in the developing process, and in the cell transistor region B, the second polysilicon layer 15 on the floating gate pattern 13b. The patterning is performed to have a predetermined distance on the image. The control gate line 15a is formed by selectively removing the second polysilicon layer 15 and the floating gate pattern 13b by an etching process using the patterned second photoresist layer PR2 as a mask.

In this case, when the first polysilicon layer forming the second polysilicon layer 15 and the floating gate pattern 13b is etched, a second photoresist layer (A) is formed at an interface between the selection transistor region A and the cell transistor region B. The semiconductor substrate 10, which is not masked with PR2, is also etched to form the trench 16.

The reason for this is due to the etching selectivity and the etching rate. In general, the oxide and nitride layers and the polysilicon layer have different etching selectivity, but the oxide and nitride layers are etched to some extent under the conditions of etching the polysilicon layer. do. In the same etching conditions, the etching rate of the nitride film is faster than that of the polysilicon layer and the oxide film is faster than the nitride film.

For this reason, when the second polysilicon layer 15 and the floating gate pattern 13b are etched, the insulating film 14 having the ONO structure and the second gate oxide film 12b having a thin thickness are also etched, and the semiconductor substrate 10 is also etched. It is also etched to form unnecessary trenches 16.

As shown in FIG. 5F, the selection gate line 13a and the control gate line are removed by an ion implantation process using the selection gate line 13a and the control gate line 15a as a mask. (15a) An impurity region 17 is formed in the semiconductor substrate 10 at both lower sides. Next, a first interlayer insulating film 18 is deposited on the entire surface of the semiconductor substrate 10 including the selection gate line 13a and the control gate line 15a, and a bit line contact region is defined to define the first line of the bit line contact region. The bit line contact hole 19 is formed by selectively patterning the first interlayer insulating film 18, the insulating film 14, and the first gate oxide film 12a (photolithography process + etching process). Next, the bit line 20 is formed on the entire surface of the first interlayer insulating layer 18 including the bit line contact hole 19. Subsequently, the bit line 20 is patterned with a predetermined width.

As shown in FIG. 5G, a second interlayer insulating film 21 is deposited on the first interlayer insulating film 18 including the bit line 20.

In addition, a signal applying region of the selection gate line 13a may be defined to one side of the bit line 10 (see FIG. 1) to selectively select the first and second interlayer insulating layers 18 and 21 on the selection gate line 13a. To form a select gate contact hole 22. The common source contact region 23 is formed in the N + diffusion region of the cell transistor region B.

The conventional nonvolatile memory device and its manufacturing method as described above have the following problems.

Since unnecessary trenches are formed in the semiconductor substrate between the selection transistor region and the cell transistor region, impurity regions are irregularly formed, thereby reducing the reliability of the device.

The present invention has been made to solve the above problems, and in particular, to provide a non-volatile memory device suitable for preventing damage to the impurity diffusion region between the selection transistor and the cell transistor and to reduce the resistance of the selection transistor and a manufacturing method thereof. Its purpose is to.

Still another object is to provide a nonvolatile memory device suitable for reducing cell size due to the reduction in the space between the selection transistor and the cell transistor, and a method of manufacturing the same.

1 is a layout of a conventional nonvolatile memory device

2 is a structural diagram taken along the line I-I of FIG.

3 is a structural diagram of the II-II line of FIG.

4 is a structural diagram on line III-III of FIG.

5A to 5G are cross-sectional views of a process along the line IV-IV of FIG.

6 is a layout diagram of a nonvolatile memory device according to the first embodiment of the present invention.

7 is a structural diagram along the line I-I of FIG.

FIG. 8 is a structural diagram of the II-II line of FIG. 6

9A to 9D are process cross-sectional views taken along line II of FIG. 6.

10A to 10C are cross-sectional views of the process taken along line II-II of FIG. 6.

11 is a layout diagram of a nonvolatile memory device according to the second embodiment of the present invention.

12 is a structural diagram on line III-III of FIG.

FIG. 13 is a structural diagram taken along line IV-IV of FIG.

FIG. 14 is a structural view taken along the line VV of FIG.

15A to 15C are process cross-sectional views on the line III-III of FIG.

16A to 16B are cross-sectional views of the process on the line 11V-V.

Explanation of symbols for main parts of the drawings

31: semiconductor substrate 32: P well

33: field oxide film 34a: first gate oxide film

34b: second gate oxide film 35: first polysilicon layer

35a: selection gate line 35b: floating gate

36: insulating film 37: second polysilicon layer

37a: control gate line 38a: source region

38b: drain region 39: first interlayer insulating film

40: first planar protective film 41: first contact hole

42: tungsten plug 43: metal pattern

44: second interlayer insulating film 45: second planar protective film

46: metal line

According to an embodiment of the present invention, a nonvolatile memory device includes a semiconductor substrate defined by a selection transistor region and a cell transistor region, a first selection gate line formed in a line shape in one direction in the selection transistor region, and a cell transistor region. A floating gate formed in a predetermined pattern, an insulating layer formed on the first selection gate line at a predetermined interval, and stacked on the first selection gate line in the same direction as the first selection gate line; An insulating layer and a control gate line to be formed, an impurity region formed in one region of the semiconductor substrate on both sides of the control gate line and the first selection gate line, and a first contact hole having a first contact hole on the first selection gate line and the impurity region A planar protective layer, a contact plug formed in the first contact hole, and the contact A conductive layer pattern contacting the lug, a second flat protective layer having a second contact hole in the conductive layer pattern above the first selection gate line, a wiring layer formed in one direction on the second contact hole and the second flat protective layer Characterized in that configured to include.

In the method of manufacturing a nonvolatile memory device having the above structure, forming a gate insulating film on a semiconductor substrate including a selection transistor region and a cell transistor region, and forming a first semiconductor layer on the gate insulating layer, the selection transistor Patterning the first semiconductor layer so that the region is linear and the cell transistor region is connected to each other at a predetermined interval, and depositing an insulating film and a second semiconductor layer on the entire surface of the semiconductor substrate, wherein the selection transistor region is one direction A first selection gate line having a line shape and a second selection gate line patterned to have a predetermined distance, and being stacked, wherein the cell transistor region is formed in a pattern in a predetermined shape and in one direction on the top including the floating gate The first control gate line is formed to be laminated to form a Etching the first and second semiconductor layers and the insulating layer at the same time, forming an impurity region in one region of the semiconductor substrate on both sides of the first selection gate line and the control gate line, and the first selection gate line and the control Forming a first planar passivation layer having a first contact hole in an impurity region on one side of the gate line, forming a contact plug in the first contact hole, and forming a conductive layer pattern on the contact plug and the first planar passivation layer Forming a second planar passivation layer having a second contact hole in the contact plug formed on the first selection gate line, and forming a conductive line having one direction on the second contact hole and the second planar passivation layer Characterized by forming.

The present invention having the above characteristics will be explained by dividing into first and second embodiments.

The nonvolatile memory device according to the first embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 6 is a layout diagram of a nonvolatile memory device according to the first exemplary embodiment of the present invention, FIG. 7 is a structural diagram of an I-I line of FIG. 6, and FIG. 8 is a structural diagram of a II-II line of FIG. 6.

In the nonvolatile memory device according to the first embodiment of the present invention, in forming the selection transistor and the cell transistor, the selection transistor is configured such that the first and second polysilicon layers are stacked like the cell transistor, and the first polysilicon layer is stacked on the first transistor. Configure to apply voltage. At this time, in order to prevent the resistance of the second polysilicon layer formed on the selection gate line from increasing, the second polysilicon layer is separated at a predetermined interval. The wiring is formed to contact the select gate line formed of the first polysilicon layer under the isolated region of the second polysilicon layer.

More specifically, the nonvolatile memory device according to the first exemplary embodiment of the present invention may have a field oxide film (") in a field region of an N-type semiconductor substrate 31 having an active region and a field region defined therein as shown in FIGS. 33) There is a P well 32 having a predetermined depth in the semiconductor substrate 31.

In the semiconductor substrate 31, a selection transistor region and a cell transistor region are defined.

The select transistor region includes a select gate line 35a having one direction, and a first gate oxide layer 34a is disposed below the select gate line 35a. There is a second polysilicon layer 37 stacked on the selection gate line 35a and isolated at a predetermined interval. An insulating layer 36 is disposed under the second polysilicon layer 37. In this case, the insulating layer 36 has an oxide oxide (ONO) structure.

In the cell transistor region, the floating gate 35b is patterned in a rectangular shape in a predetermined region, and the second gate oxide layer 34b is disposed below the floating gate 35b. In this case, the second gate oxide film 34b is thicker than the first gate oxide film 34a. There is a control gate line 37a having the same direction as the selection gate line 35a on the top including the floating gate 35b. In addition, an insulating film 36 is disposed under the control gate line 37a, and the insulating film 36 may have an ONO structure.

A plurality of source regions 38a and drain regions 38b having the same direction as the selection gate lines 35a are formed in the active regions of the semiconductor substrate 31 on both sides of the control gate line 37a and the selection gate line 35a. have.

The first interlayer insulating film 39 and the first insulating hole 41 having an isolated portion of the second polysilicon layer 37 and a first contact hole 41 in the drain region 38b of the selection gate line 35a and the cell transistor region. 1 planar protective film 40 is laminated. In this case, the first interlayer insulating film 39 is formed to surround the side surface of the second polysilicon layer 37 in the first contact hole 41.

There is a tungsten plug 42 selectively formed in the first contact hole 41.

There is a tungsten plug 42 formed in an isolated region of the second polysilicon layer 37 and a metal pattern 43 patterned in a square shape on the first flat protective layer 40 adjacent thereto.

In addition, the metal pattern is formed in a line shape in contact with the tungsten plug 42 formed in the drain region 38b and has a direction orthogonal to the control gate line 37a on the top of the floating gate 35b and the control gate line 37a. There is 43. The tungsten plug 42 formed in the drain region 38b is used as a bit line.

The source region 38a of the cell transistor extends to one side of the semiconductor substrate 31 along the cell transistors, and the metal commonly connects the cell transistors through a common source contact region of the extended source region 38a. There is a contact 43. In this case, the metal contact 43 connected to the common source contact region has a line shape having one direction orthogonal to the control gate line 37a.

The second interlayer insulating layer 44 and the second planar passivation layer 45 having the second contact hole are stacked on the metal pattern 43 formed on the selection gate line 35a.

A metal line 46 is formed on the second planar passivation layer 45 to be in contact with the metal pattern 43 through the second contact hole and to have the same direction as the selection gate line 35a.

Next, a method of manufacturing a nonvolatile memory device according to the first embodiment of the present invention will be described with reference to the accompanying drawings.

9A to 9D are process cross-sectional views on the line II of FIG. 6, and FIGS. 10A to 10C are process cross-sectional views on the line II-II of FIG. 6.

In the method of manufacturing a nonvolatile memory device according to the first embodiment of the present invention, as shown in FIGS. 9A and 10A, a P well (P well) is formed to have a predetermined depth in an N-type semiconductor substrate 31 in which an active region and a field region are defined. 32). Subsequently, a field oxide layer 33 is formed in the field region by a LOCOS (LOCal Oxidation of Silicon) process. The semiconductor substrate 31 is divided into a selection transistor region and a cell transistor region (not shown).

Thereafter, a threshold voltage regulation ion is implanted into the surface of the P well 32 in which the selection transistor region and the cell transistor region are to be formed. After the oxide film is deposited on the selected transistor region and the cell transistor region, the oxide film of the cell transistor region is removed to a predetermined thickness. Accordingly, the thickness of the first gate oxide film 34a of the selection transistor region is greater than the thickness of the second gate oxide film 34b of the cell transistor region.

Next, an undoped first polysilicon layer 35 is deposited on the entire surface including the first and second gate oxide films 34a and 34b. Thereafter, impurity ions are implanted into the undoped first polysilicon layer 35 to dope the first polysilicon layer 35.

Subsequently, as shown in FIGS. 9B and 10A, the first polysilicon layer 35 is patterned so that the selection transistor region and the cell transistor region are connected, and the selection transistor region is patterned so as to be longitudinally connected, and the cell is formed. The transistor region is subsequently patterned to have a predetermined interval to form a floating gate pattern in a rectangular shape. In addition, an insulating layer 36 having an oxide Nitride Oxide (ONO) structure is deposited on the entire surface, and a doped second polysilicon layer 37 is deposited on the entire surface of the resultant. Thereafter, anisotropic etching is performed simultaneously so that the selection transistor region and the first and second polysilicon layers 35 and 37 of the cell transistor region are stacked. Accordingly, the selection gate line 35a formed of the linear polysilicon layer 35 is formed in the selection transistor region, and the second polysilicon layer 37 separated from each other is formed on the selection gate line 35a at regular intervals. . In addition, a patterned floating gate 35b is formed in the cell transistor region at a predetermined interval in a quadrangular shape, and a control gate line parallel to the upper portion including the floating gate 35b in the same direction as the selection gate line 35a. 37a) is formed.

Next, impurity ions are implanted into the surfaces of the P well 32 on both sides of the selection gate line 35a and the control gate line 37a to form the source region 38a and the drain region 38b. At this time, the source region 38a and the drain region 38b are formed in plural to have one direction in the surface of the P well 32 on both sides of the selection gate line 35a and the control gate line 37a. The source region 38a extends between the cell transistors and is formed on one side of the semiconductor substrate 31.

In addition, the source region 38a and the drain region 38b inject low concentration impurity ions into the surface of the P well 32 on both sides of the selection gate line 35a and the control gate line 37a, and the selection gate line 35a and the drain region 38b. After forming sidewall spacers (not shown) on both sides of the floating gate 35b and the control gate line 37a, impurities are formed in the P well 32 on both sides of the selection gate line 35a and the control gate line 37a. It can be formed by implanting ions.

A first interlayer insulating film 39 and a first planar protective film 40 are sequentially deposited on the entire surface of the resultant product. Thereafter, a first contact hole is formed such that an upper portion of the selection gate line 35a of the isolated portion of the second polysilicon layer 37, the drain region 38b, and one side of the extended source region 38a are exposed. To form 41. As a result, a drain contact region is formed in the drain region 38b, and a common source contact region is formed in the source region 38a (see Fig. 6).

Next, as shown in FIGS. 9C and 10B, after forming the tungsten plug 42 in the first contact hole 41, the first metal layer is deposited on the entire surface including the tungsten plug 42. The first metal layer is formed by aluminum sputter deposition. Thereafter, the first metal layer is selectively etched to form a metal pattern 43. In this case, the metal pattern 43 is formed to have a rectangular pattern on the tungsten plug 42 formed on the isolated region of the second polysilicon layer 37 and on the first flat protective film 40 adjacent thereto. In addition, a common source is formed on the control gate line 37a stacked with the floating gate 35b to be connected to the tungsten plug 42 formed in the drain region 38b so as to be perpendicular to the control gate line 37a. It is formed to have a direction orthogonal to the control gate line 37a so as to be connected to the tungsten plug 42 formed in the contact region.

Thereafter, a second interlayer insulating film 44 is deposited on the entire surface.

Next, as shown in FIGS. 9D and 10C, a second planar protective film 45 is deposited on the second interlayer insulating film 44. The second interlayer insulating layer 44 and the second planarization protective layer 45 are anisotropically etched to form a second contact hole in the metal pattern 43 formed on the isolated upper portion of the second polysilicon layer 37. The second metal layer is deposited on the second contact hole and the second planarization protective layer 45.

Thereafter, the second metal layer is anisotropically etched to contact the metal pattern 43 through the second contact hole and form the same direction as the selection gate line 35a to form the metal line 46.

Next, a nonvolatile memory device according to a second embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 11 is a layout diagram of a nonvolatile memory device according to the second exemplary embodiment of the present invention, FIG. 12 is a structural diagram of line III-III of FIG. 11, FIG. 13 is a structural diagram of line IV-IV of FIG. 11, and FIG. 14 Is a structural diagram along the line V-V in FIG.

In the nonvolatile memory device according to the second embodiment of the present invention, in forming a selection transistor and a cell transistor, the selection transistor is formed by stacking first and second polysilicon layers like the cell transistor, and is formed on the selection gate line. In order to prevent the resistance of the second polysilicon layer from increasing, the second polysilicon layer is isolated to have a predetermined interval. In addition, in order to reduce the resistance of the select gate line formed of the first polysilicon layer, the tungsten plug was connected to the second polysilicon layer having low resistance without forming another wiring.

In more detail, as shown in FIGS. 11, 12, 13, and 14, the nonvolatile memory device according to the second exemplary embodiment of the present invention may include a field oxide film (FIG) in a field region of a semiconductor substrate 31 in which an active region and a field region are defined. 33) There is a P well 32 having a predetermined depth in the semiconductor substrate 31.

In the semiconductor substrate 31, a selection transistor region and a cell transistor region are defined.

The selection transistor region has a selection gate line 35a having one direction, and a first gate oxide layer 34a is disposed below the selection gate line 35a. There is a second polysilicon layer 37 stacked on the selection gate line 35a and isolated at a predetermined interval. An insulating layer 36 is disposed under the second polysilicon layer 37. In this case, the insulating layer 36 has an oxide oxide (ONO) structure.

In the cell transistor region, the floating gate 35b is patterned in a rectangular shape in a predetermined region, and the second gate oxide layer 34b is disposed below the floating gate 35b. In this case, the second gate oxide film 34b is thicker than the first gate oxide film 34a. There is a control gate line 37a having the same direction as the selection gate line 35a on the top including the floating gate 35b. An insulating layer 36 is disposed under the control gate line 37a. At this time, the insulating film 36 has an ONO structure.

A plurality of source regions 38a and drain regions 38b having the same direction as the selection gate line 35a are formed in the active regions of the semiconductor substrate 31 on both sides of the control gate line 37a and the selection gate line 35a. have.

The first interlayer insulating film 39 and the first insulating hole 41 having an isolated portion of the second polysilicon layer 37 and a first contact hole 41 in the drain region 38b of the selection gate line 35a and the cell transistor region. 1 planar protective film 40 is laminated. In this case, the first contact hole 41 is formed such that the side surface of the second polysilicon layer 37 is exposed.

There is a tungsten plug 42 selectively formed in the first contact hole 41.

And a direction orthogonal to the control gate line 37a to be in contact with the tungsten plug 42 formed in the drain region 38b and to be in contact with the tungsten plug 42 on the floating gate 35b and the control gate line 37a. And a metal pattern 43 is formed. The tungsten plug 42 formed in the drain region 38b is used as a bit line.

The source region 38a of the cell transistor extends from one side of the semiconductor substrate 31, and there is a metal contact 43 which connects the cell transistors in common through the common source contact region of the extended source region 38a. . In this case, the metal contact 43 connected to the common source contact region forms a line orthogonal to the control gate line 37a and is formed in a line shape.

The selection gate line 35a is formed of the first polysilicon layer 35 formed by ion implantation, and the resistance at this time is approximately 1000Ω. The second polysilicon layer 37 deposited in the doped state has a resistance of about 6Ω or 7Ω.

Therefore, since the selection gate line 35a and the second polysilicon layer 37 are connected through the tungsten plug 42 on the selection gate line 35a, the resistance of the selection gate line 35a may be reduced.

Next, a method of manufacturing a nonvolatile memory device according to a second embodiment of the present invention will be described with reference to the accompanying drawings.

15A to 15C are process cross-sectional views on the line III-III of FIG. 11, and FIGS. 16A to 16B are the process cross-sectional views on the line V-V of FIG.

In the method of manufacturing a nonvolatile memory device according to the second embodiment of the present invention, as shown in FIGS. 15A and 16A, a P well (eg, a P well) is formed to have a predetermined depth in an N-type semiconductor substrate 31 in which an active region and a field region are defined. 32). Subsequently, a field oxide layer 33 is formed in the field region by a LOCOS (LOCal Oxidation of Silicon) process. The active region is divided into a selection transistor region and a cell transistor region (not shown).

Thereafter, a threshold voltage regulating ion is implanted into the surface of the P well 32 in which the selection transistor region and the cell transistor region are to be formed. After the oxide film is deposited on the select transistor region and the cell transistor region, the oxide film of the cell transistor region is removed by a predetermined thickness. Accordingly, the thickness of the first gate oxide film 34a of the selection transistor region is thicker than the thickness of the second gate oxide film 34b of the cell transistor region.

Next, an undoped first polysilicon layer 35 is deposited on the entire surface including the first and second gate oxide films 34a and 34b. Thereafter, impurity ions are implanted into the undoped first polysilicon layer 35 to dope the first polysilicon layer 35.

Next, as shown in FIGS. 15B and 16A, the first polysilicon layer 35 is patterned to connect the selection transistor region and the cell transistor region. In this case, the selection transistor region is patterned to be long in the vertical direction, and the cell transistor region is patterned so that the region of the floating gate to be patterned later is formed in a square shape. In addition, an insulating layer 36 having an oxide Nitride Oxide (ONO) structure is deposited on the entire surface, and a doped second polysilicon layer 37 is deposited on the entire surface of the resultant.

Thereafter, anisotropic etching is performed simultaneously so that the selection transistor region and the first and second polysilicon layers 35 and 37 of the cell transistor region are stacked.

Accordingly, the selection gate line 35a formed of the linear first polysilicon layer 35 is formed in the selection transistor region, and the second polysilicon layer 37 is formed on the selection gate line 35a by a predetermined interval. do. A patterned floating gate 35b is formed in the cell transistor region at predetermined intervals, and the control gate line 37a is parallel to the same direction as the selection gate line 35a on the upper portion including the floating gate 35b. Is formed.

Next, impurity ions are implanted into the surfaces of the P well 32 on both sides of the selection gate line 35a and the control gate line 37a to form the source region 38a and the drain region 38b. At this time, the source region 38a and the drain region 38b are formed in plural to have one direction in the surface of the P well 32 on both sides of the selection gate line 35a and the control gate line 37a. The source region 38a is formed on one side of the semiconductor substrate 31 by the phase extending between the cent transistors.

In addition, the source region 38a and the drain region 38b inject low concentration impurity ions into the surface of the P well 32 on both sides of the selection gate line 35a and the control gate line 27a, and the selection gate line 35a and the drain region 38b. After forming sidewall spacers (not shown) on both sides of the floating gate 35b and the control gate line 37a, impurities are formed in the P well 32 on both sides of the selection gate line 35a and the control gate line 37a. It can also be formed by implanting ions.

A first interlayer insulating film 39 and a first planar protective film 40 are sequentially deposited on the entire surface of the resultant product. Thereafter, the first contact hole 41 is formed to expose sidewalls of the selection gate line 35a and the second polysilicon layer 37 of the isolated portion of the second polysilicon layer 37. The first contact hole 41 is also formed in the source region 38a which extends from the drain region 38b. In this case, the first contact hole 41 may be formed so that the edge of the isolated portion of the second polysilicon layer 37 is exposed. That is, the diameter of the first contact hole 41 in the first planarization protective film 40 may be longer than the diameter of the first contact hole 41 in the second polysilicon layer 37. As a result, a drain contact region is formed in the drain region 38b, and a common source contact region is formed in the source region 38a (see FIG. 11).

Next, as illustrated in FIGS. 15C and 16B, a tungsten plug 42 is selectively formed in the first contact hole 41. Thereafter, a first metal layer is deposited on the entire surface including the tungsten plug 42. The first metal layer is formed by aluminum sputter deposition. Thereafter, the first metal layer is anisotropically etched to form a metal pattern 43. At this time, the metal pattern 43 is orthogonal to the control gate line 37a on the control gate line 37a stacked with the floating gate 35b to be connected to the tungsten plug 42 formed in the drain region 38b. It is formed to have. In addition, referring to FIG. 11, the metal pattern 43 is formed to have a line structure in one direction contacted to the common source contact region to commonly connect the source region 38a of the cell transistor region.

The nonvolatile memory device of the present invention as described above and a manufacturing method thereof have the following effects.

First, since the selection transistor is formed by stacking the first and second polysilicon layers like the cell transistor, unnecessary trenches are formed between the selection transistor and the cell transistor, thereby preventing impurity regions therebetween.

Second, since the second polysilicon layers of the selection transistors formed by stacking the first and second polysilicon layers are separated by a predetermined interval, the resistance of the second polysilicon layer on the selection gate line may be reduced.

Third, since the selection gate line of the selection transistor and the second polysilicon layer having a small resistance are used through the tungsten plug, it is possible to prevent the resistance of the selection gate line from increasing.

Claims (17)

A semiconductor substrate defined by a selection transistor region and a cell transistor region, A first selection gate line formed in a line shape in one direction in the selection transistor region and a floating gate formed in a predetermined pattern in the cell transistor region, An insulating film and a control gate line stacked on the first selection gate line at a predetermined interval and stacked on the first selection gate line in the same direction as the first selection gate line. , An impurity region formed in one region of the semiconductor substrate on both sides of the control gate line and the first selection gate line; A first planar passivation layer having a first contact hole on the first select gate line and the impurity region; A contact plug formed in the first contact hole, A conductive layer pattern in contact with the contact plug, A second planar passivation layer having a second contact hole in the conductive layer pattern on the first select gate line; And a wiring layer formed in one direction on the second contact hole and the second planarization protective layer. The nonvolatile memory device of claim 1, wherein a gate insulating layer is provided under the first selection gate line and under the floating gate. The nonvolatile memory device of claim 2, wherein the gate insulating layer under the first selection gate line is thicker than the gate insulating layer under the floating gate. The nonvolatile memory device of claim 1, wherein the insulating layer has an oxide nitride oxide (ONO) structure. The nonvolatile memory device of claim 1, wherein the second selection gate line is configured to electrically float with the first selection gate line by the insulating layer. The nonvolatile memory device of claim 1, wherein an interlayer insulating layer is further formed between the second selection gate line and the first planar passivation layer to surround one side of the first contact hole. The nonvolatile memory device of claim 1, wherein the first contact hole is formed in an upper region of the first selection gate line in which the second selection gate line is isolated. A semiconductor substrate defined by a selection transistor region and a cell transistor region, A gate insulating film and a floating gate stacked on the selection transistor region in a line shape in one direction, a gate insulating film and a floating gate stacked on the cell transistor region in a predetermined pattern; An insulating film and a control gate line stacked in the same direction as the first selection gate line on the first selection gate line, the insulating film being stacked on the first selection gate line at a predetermined interval, and the second selection gate line and the floating gate; An impurity region formed in one region of the semiconductor substrate on both sides of the control gate line and the first selection gate line; A planar passivation layer having contact holes in the first select gate line and the impurity region to expose side surfaces of the second select gate line; A contact plug formed in the contact hole to connect the second selection gate line and the first selection gate line; And a contact layer formed in the impurity region and a wiring layer formed in one direction on the planar passivation layer. Forming a gate insulating film on the semiconductor substrate including the selection transistor region and the cell transistor region, and forming a first semiconductor layer on the gate insulating film; Patterning the first semiconductor layer so that the selection transistor region is in a line shape and the cell transistor region is connected to each other at a predetermined interval; Depositing an insulating film and a second semiconductor layer on the entire surface of the semiconductor substrate; The selection transistor region is formed by stacking a line-type first selection gate line having one direction and a second selection gate line patterned to have a predetermined interval, and the cell transistor region is formed with a pattern having a predetermined shape and the floating gate and the floating. Simultaneously etching the first and second semiconductor layers and the insulating layer such that a line-type control gate line having one direction is stacked on the upper portion including the gate; Forming an impurity region in one region of the semiconductor substrate on both sides of the first selection gate line and the control gate line; Forming a first planar passivation layer having a first contact hole in the impurity region on one side of the first selection gate line and the control gate line; Forming a contact plug in the first contact hole; Forming a conductive layer pattern on the contact plug and the first flat protective layer; Forming a second planar passivation layer having a second contact hole in the contact plug formed on the first select gate line; And forming a conductive line in one direction on the second contact hole and the second planar passivation layer. 10. The method of claim 9, wherein the gate insulating layer under the first select gate line is formed thicker than the gate insulating layer under the cell transistor region. 10. The method of claim 9, wherein the first semiconductor layer is formed by depositing an undoped polysilicon layer followed by ion implantation. 10. The method of claim 9, wherein the insulating film is formed to have an oxide oxide (ONO) structure. 10. The method of claim 9, wherein the second semiconductor layer is formed by depositing a doped polysilicon layer. 10. The method of claim 9, further comprising forming an interlayer insulating film on the second select gate line before forming the first contact hole so that side surfaces of the first contact hole are surrounded by the interlayer insulating film. A method of manufacturing a nonvolatile memory device, characterized in that. 10. The method of claim 9, wherein the contact plug is made of tungsten. Forming a gate insulating film on the semiconductor substrate including the selection transistor region and the cell transistor region, and forming a first semiconductor layer on the gate insulating film; Patterning the first semiconductor layer so that the selection transistor region is in a line shape, and the cell transistor region is connected to each other at a predetermined interval; Depositing an insulating film and a second semiconductor layer on the entire surface of the semiconductor substrate; The selection transistor region is formed by stacking a line-type first selection gate line having one direction and a patterned second selection gate line having a predetermined interval, and the cell transistor region is formed with a pattern having a predetermined shape. Simultaneously etching the first and second semiconductor layers and the insulating layer such that a line-type control gate line having one direction is stacked on the upper portion including the gate; Forming an impurity region in one region of the semiconductor substrate on both sides of the first selection gate line and the control gate line; Forming a planar passivation layer having a contact hole in the first select gate line such that both the impurity region on one side of the control gate line and both sides of the second select gate line separated from each other are exposed; Forming a contact plug in the contact hole such that the first selection gate line and the second selection gate line are connected to each other; And forming a conductive line in one direction on the contact hole of the impurity region and the planar passivation layer. 17. The method of claim 16, wherein the second semiconductor layer is formed by depositing a doped polysilicon layer.