JPS63152165A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To clamp a voltage applied to a cell, and prevent a capacitor of the cell from being destroyed, by providing an active layer surrounded by an field insulating film of a different region from a memory cell with an avalanche diode for clamping a voltage. CONSTITUTION:On the periphery of a P-type Si substrate 1, a thick field SiO2 film 2 is formed, and on the region surrounded by this film, a continuous thin SiO2 film 3 and 3A are stuck. On the film 3, a plate 4 of one side electrode composed of a polycrystalline Si film constituting a capacitor C is arranged, and on the film 3A, a word line W of polycrystalline Si is arranged. Under the plate 4, an N<+> type region 5 which serves as the other electrode and a P<+> type region 6 situated under the region 5 are formed, which constitute a condenser with large capacity. By applying the word line W to a gate electrode, an N<+> type source region 7 and a drain region 8 are formed on both sides of the condenser to constitute an access transistor. Under a part of the film 3a, an N<+> type region 9 and a P<+> type region 10 are formed to constitute an avalanche diode D.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly relates to a technique that is effective when applied to prevent fluctuations in the clamp voltage of a clamp diode using avalanche breakdown. It is something.

[Conventional technology]

For example, dynamic RAM (Random, Acce
In the ss Me-ory), the capacitor constituting the memory cell is composed of an MO5 capacitor and a pn junction capacitor formed by adding a second conductivity type semiconductor region under the first conductivity type semiconductor region which is one electrode of the MO5 capacitor. so-called) 1i-C
There is a known technology that reduces the soft error rate and increases the storage capacity by increasing the storage capacity (for example, the patent application
0-86393 etc.).

[Problem that the invention seeks to solve]

The present inventor studied a dynamic RAM having a capacitor of this Hi-C structure.

In other words, in a +Hi-C4iI capacitor, there is an n-type semiconductor region and a p-type semiconductor region, for example, in the semiconductor substrate below the plate constituting the capacitor electrode.
By providing a type 4 semiconductor region, the storage capacity is increased.

However, according to the study results of one of the present inventors.

When performing accelerated testing after manufacturing dynamic RAM,
Power supply voltage V. . and substrate bias VBg to a value much higher than the value during normal operation (e.g. ■. = +5V, VBg = -3V) (e.g. V.C = +7V, Vg, = -4,2
v), an excessive reverse bias is applied to the diode formed by these semiconductor regions, resulting in junction breakdown.

An object of the present invention is to provide a technique for keeping (clamping) the voltage applied to a memory cell below a certain voltage.

Another object of the present invention is to provide a technique that can prevent fluctuations in clamp voltage.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

Outline of typical inventions disclosed in this application is as follows.

That is, an avalanche diode for voltage clamping is formed by providing, for example, an n' type semiconductor region and, for example, a p' type semiconductor region in an active region surrounded by a field insulating film in a region different from the memory cell.

[For production]

According to the above-described means, the voltage applied to the memory cell can be clamped to the breakdown voltage BVJ of the diode, thereby preventing the capacitor of the memory cell from being destroyed.

〔Example〕

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the present invention will be described below based on one embodiment with reference to the drawings.

Dynamic RA according to one embodiment as shown in FIG.
In M, a field insulating film 2 such as a SiO2 film is provided on a semiconductor substrate 1 such as a p-type silicon (Si) substrate, and isolation between elements is thereby performed. On the surface of the active region surrounded by the field insulating film 2, insulating films 3 and 3A, such as 5102 films, are provided. On this insulating film 3, a plate 4 made of, for example, a first layer of polycrystalline silicon film constitutes one electrode of a capacitor C made of, for example, a polycrystalline silicon film.
is provided. On the other hand, on the insulating film 3A.

A word line W is formed. The word line W is made of, for example, a second layer of polycrystalline silicon film. For example, a voltage Vc c /2, which is half the power supply voltage, is applied to the plate 4 . A capacitor C is constructed by sandwiching the insulating film 3 between the semiconductor substrate 1 and the plate 4. That is, in the semiconductor substrate 1 below the plate 4, a semiconductor region 5 of, for example, an N4 type, which constitutes the other electrode of the capacitor C, is provided, and below this semiconductor region 5, a semiconductor region of, for example, a P'' type is provided. 6 is provided.The capacitor C has increased storage capacitance due to the junction capacitance between these semiconductor regions 5 and 6.
) It has a li-C structure. Further, the semiconductor substrate l
For example, n is self-aligned with respect to the word line W.
A type semiconductor region 7.8 is provided. A data line (not shown) is connected to the area 7 . The word line W
as the gate electrode.

The semiconductor regions 7 and 8 are used as a source region and a drain region, and an access transistor (memory cell selection MI
S FE, T) T is configured. And the fourth
As shown in the figure, the access transistor T and the capacitor C constitute a known 1MO3FET type (one transistor, one capacitor type) memory cell.

On the other hand, in the active region surrounded by the field insulating film 2 in the peripheral region of the chip, for example, an n-type semiconductor region 9 is provided, and below the semiconductor region ffi, 9, for example, a p-type semiconductor is provided. A region 10 is provided.

As will be described later, semiconductor regions 9 and 10 are formed by the same manufacturing process as semiconductor regions 5 and 6, respectively.

These semiconductor regions 9 and 10 constitute an avalanche diode D for voltage clamping having an IV characteristic as shown in FIG.

With this diode D, as shown in FIG.

The voltage applied to the memory cell is clamped to the breakdown voltage B V r of the diode D. Specifically, the diode D connects to the external terminal pvc of the dynamic RAM chip.
c and the board. External terminal Pvcc is a terminal for supplying power supply voltage Vcc to the chip. That is, semiconductor region 9 is supplied with power supply voltage VCC.

On the other hand, the semi-quartet region 10 has substantially the same potential as the potential applied to the semiconductor region 6, and in this embodiment, the same potential vlffo as the substrate. The voltage of the external terminal Pvcc is supplied as an operating voltage to each internal circuit block of the dynamic RAM.

In this embodiment, the breakdown voltage BVy is, for example, about 11
It is considered to be V.

For example, when performing an acceleration test after manufacturing a dynamic RAM, a high power supply voltage of about 8V is used. C to external terminal Pvc
When applied to c, a high substrate bias voltage VeB of about -4.5 V, for example, is generated by a voltage generation circuit (not shown) built into the chip and supplied to the substrate. deer,
However, in this embodiment, the diode D clamps the difference between the operating voltages of the substrate and the internal circuit to about 11V. Specifically, the potential of the terminal Pvcc is about 7V, while the potential of the substrate is about -4V.

As a result, even if a high-level full write is performed on any memory cell in an accelerated test (a write in which the power supply voltage appears almost unchanged in the semiconductor region 5 due to boosting of the word line W, etc.), the semiconductor region 5.6 Since the voltage applied to the configured diodes is always clamped to BVy, junction breakdown can be prevented.

As shown in FIG. 3, a protection circuit is connected to the external terminal PAD to which address signals and the like are applied in order to prevent the MISFETs T2 and T3 from being destroyed. The protection circuit may be composed of various known circuits, but the one in this embodiment is composed of a resistor R and an N-channel MISFET Tl connected in a diode configuration. Furthermore, in one embodiment,
A diode D' having the same structure as diode D is added to the protection circuit. Thereby, the function of the protection circuit can be further improved.

In this embodiment, the semiconductor region 10 of the diode D (and D') is provided so as not to be in contact with the field insulating film 2, for example, by d=0.5 μm from the field insulating film 2.
They are located a fair distance apart. This is due to the following reasons. When the semiconductor region 10 is formed so as to be in contact with the field insulating film, according to the study results of the present inventor, when a reverse bias is applied to the voltage clamping diode and avalanche breakdown occurs, it occurs near the field insulating film. As a result of carriers being injected into the field insulating film and accumulated, the breakdown voltage BVJ, that is, the clamp voltage of the diodes D and D' fluctuates.

As a result of extensive studies, the inventors of the present invention have found that carriers are injected into the field insulating film as described above because of field extinction R.
It was discovered that this is due to the existence of an electric field directed toward the field insulating film near the film. Based on this discovery, the semiconductor region 10 is provided so as not to be in contact with the field insulating film.

As a result, as shown in FIG. 1, there is no electric field directed toward the field insulating film 2 in the vicinity of the field insulating film 2, so that carriers generated by avalanche breakdown in the diode D are transferred to the field insulating film 2. can be prevented from being injected. Therefore, it is possible to prevent fluctuations in BVy, that is, the clamp voltage, due to accumulation of carriers in the field insulating film 2.

Next, an example of a method for manufacturing the dynamic RAM according to this embodiment configured as described above will be described.

As shown in FIG. 1, first, the surface of a semiconductor substrate 1 is selectively thermally oxidized to form a field insulating film 2, and then the surface of the active region surrounded by this field insulating film 2 is thermally oxidized to form an insulating film. form 3. Next, a p-type impurity such as boron is ion-implanted into the semiconductor substrate 1 using a mask having a predetermined shape to form a semiconductor region 6.10. Regions 6 and 10 are selectively introduced into the substrate using a field insulating layer 2 and a mask (not shown) consisting of, for example, a photoresist layer. Similarly, an n-type impurity such as arsenic is selectively ion-implanted into the semiconductor region 5.9.
form. Next, a polycrystalline silicon film, for example, is formed on the entire surface, and this polycrystalline silicon film is doped with an impurity such as phosphorus to lower the resistance, and then this polycrystalline silicon film is patterned into a predetermined shape by etching. to form the plate 4. Next, the surface of the plate 4 is thermally oxidized, and a new insulating film (SiO2 film) 3 is formed on the surface of the substrate 1.
A is formed as a gate oxide film. Next, word lines W are formed in the same manner as the plate 4.

Next, using this word line W as a mask, an n-type impurity such as arsenic is ion-implanted into the semiconductor substrate 1, thereby forming a semiconductor region 7.8 in a self-aligned manner with respect to this word line W. After that, an interlayer insulating film, wiring, etc. (not shown) are formed, and the desired dynamic RAM is created.
complete.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the gist of the invention. It is.

The material and structure of the gate electrode, the structure of the transistor T, etc. can be changed to various known ones.

In addition to the planar type shown in FIG. 1, the memory cell may be of a known stacked capacitor type or a type that utilizes grooves (pores) formed in the substrate.

In addition to dynamic RAM, static RAM
In M, etc., an information storage node (in an SRAM, a pair of input/output nodes of a memory cell flip-flop circuit) has an impurity concentration lower than that of a semiconductor region of the first conductivity type and a substrate (or well region) formed therebelow. The present invention is effective when the semiconductor region is connected to a PN junction formed of a semiconductor region of a high conductivity type.

The semiconductor regions 9 and 1 or 10 may be formed independently by a manufacturing process different from that of the semiconductor region 5.6. In this case as well, it is preferable that the region 10 is not formed using the field insulating film as a mask, but is formed apart from the field insulating film. In this case 1, for example, by making the impurity concentration of region 10 higher than that of region 6, the breakdown voltage of diode D can be made smaller than that of the PN junction of capacitor C. Therefore, the reliability of the memory can be increased and the yield can be improved.

For example, the present invention can be applied to various semiconductor integrated circuit devices having clamp diodes.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical inventions will be briefly explained.

It is as follows.

That is, it is possible to prevent destruction of the memory cell and prevent fluctuations in the clamp voltage.

[Brief explanation of the drawing]

FIG. 1 shows a dynamic RAM according to an embodiment of the present invention.
2 is a graph showing the IV characteristics of a clamp diode using avalanche breakdown, FIG. 3 is a diagram showing a voltage clamp circuit, and FIG. 4 is a circuit diagram showing a memory cell. be. In the figure, 1... semiconductor substrate, 2... field insulating film,
3... Insulating film, 4... Plate, 5-10... Semiconductor region, W... Word line, T... Access transistor, C'cap'<'t'.
knee\.

Claims (1)

[Claims] 1. A diode comprising a first semiconductor region of a first conductivity type provided in a semiconductor substrate and a second semiconductor region of a second conductivity type provided below the first semiconductor region; A third semiconductor region formed in the same process as the first semiconductor region and connected to the information storage node of the memory cell, and a third semiconductor region formed in the same process as the second semiconductor region provided below the third semiconductor region. A semiconductor integrated circuit device comprising a fourth semiconductor region. 2. The semiconductor integrated circuit device according to claim 1, wherein the second semiconductor region is not in contact with a field insulating film. 3. Claim 2, wherein the first and third semiconductor regions are n^+ type semiconductor regions, and the second and fourth semiconductor regions are p^+ type semiconductor regions. The semiconductor integrated circuit device described in Section 1. 4. Claim 2, wherein the third semiconductor region is one electrode of a capacitor of a memory cell.
The semiconductor integrated circuit device described in Section 1. 5. a semiconductor substrate, an insulating film formed on a part of the semiconductor substrate, a first semiconductor region of a first conductivity type formed in the semiconductor substrate and defined by the insulating film, and a first semiconductor region in the semiconductor substrate; a second semiconductor region of a second conductivity type formed below the semiconductor region and separated from the insulating film, and utilizing a breakdown voltage in a reverse direction of a diode constituted by the first and second semiconductor regions. Features of semiconductor integrated circuit devices.