JPH04335570A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device such as a dynamic RAM or the like which can discharge the stored charge of an input/output part cell region by installing the following: a static-electricity protective circuit which is formed in a second well region of a first conductivity; and a well-charge discharge part which discharges the stored charge of the second well region. CONSTITUTION:For example, a first N-type diffusion layer N<+>1 coupled to a power-supply voltage VCC for a circuit is used as its collector and a second N-type diffusion layer N<+>2 coupled to the ground potential VSS of a circuit is used as its emitter inside an input/output part P-well region IOPW in which an input/output part, a static-electricity protective circuit and the like are formed. A well-charge discharge part WQS which includes the following is installed: a lateral bipolar transistor using a P-well region as its base; or a diode which uses a P-well region as its anode and which uses a third N-type diffusion layer N<+>3 coupled to the ground potential VSS of a circuit as its cathode. Thereby, it is possible to realize a dynamic RAM which does not deteriorate a characteristic and which does not increase a chip area.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a semiconductor device.
For example, the present invention relates to a technique that is particularly effective when used in a dynamic RAM (random access memory), etc., which includes bonding pads coupled to external terminals and electrostatic protection circuits provided corresponding to these bonding pads.

0002

2. Description of the Related Art There is a semiconductor device such as a dynamic RAM having a plurality of bonding pads on a semiconductor substrate. These dynamic RAMs and the like include a plurality of electrostatic protection circuits provided corresponding to each bonding pad.

Dynamic RA with electrostatic protection circuit
M is described, for example, in Japanese Patent Application No. 1-65838.

0004

[Problems to be Solved by the Invention] Prior to the present invention, the inventors of the present application attempted to install an input/output section including an input circuit and an output circuit such as a dynamic RAM, and a corresponding electrostatic protection circuit by covering most of the surface of a semiconductor substrate. By forming the well region in a well region that is electrically isolated from the memory array section, which is located in the same area, the memory array section is protected from disturbances generated through external terminals, that is, input/output sections, and its operating margin is improved. I thought about doing it. At this time, dynamic RAM and the like have a so-called triple well structure, and a P-well region where an input/output section is formed and a P-type semiconductor substrate where a memory array section is formed are electrically separated. An N-well region is provided for this purpose. As a result, an input/output section is formed at P
By supplying substrate potentials of different absolute values to the P-type semiconductor substrate on which the well region and the memory array portion are formed, it becomes possible to further optimize the characteristics of each.

However, the inventors of the present application have discovered that the dynamic RAM having the triple well structure has the following problems. That is, relatively high voltage noise such as spike noise is applied to the input/output section of a dynamic RAM or the like via an external terminal. In conventional dynamic RAMs, charges associated with these high voltage noises are discharged through the PN junction section or lateral bipolar transistor of an electrostatic protection circuit formed in a common semiconductor substrate region that is electrically integrated with the memory array section. and is released to the circuit's supply voltage or ground potential supply point. In addition, when high voltage noise exceeds the charge absorption capacity of the PN junction section or lateral bipolar transistor, some of the charge flows into the semiconductor substrate, but after being stored in a relatively large substrate capacitance, it is stored in the memory array section or directly surrounding the semiconductor substrate. Appropriate PN of the circuit
It is discharged to the power supply voltage or ground potential of the circuit through the junction part. However, in dynamic RAMs with a triple-well structure in which the input/output section and electrostatic protection circuit are placed in a P-well region that is electrically separated from the semiconductor substrate, charges flowing from the electrostatic protection circuit into the P-well region are removed. There is not enough storage capacity available and no path for these charges to be released. Additionally, in order to deal with this, it is possible to increase the size of the lateral bipolar transistor in the electrostatic protection circuit to maximize its charge discharging ability, but this would increase the capacitance of the input/output section, making it difficult to meet the standards. At the same time, the required layout area of the electrostatic protection circuit increases, and the chip area of dynamic RAM and the like increases.

A first object of the present invention is to accumulate an input/output section well region that is electrically isolated from a semiconductor substrate on which a memory array section and the like are formed, and on which an input/output section, an electrostatic protection circuit, etc. are formed. An object of the present invention is to provide a semiconductor device such as a dynamic RAM that can emit charges. A second object of the present invention is to realize a dynamic RAM or the like having a triple well structure without degrading its characteristics or increasing the chip area. A third object of the present invention is to promote the triple well structure of dynamic RAM and the like and to improve its operating characteristics.

[0007]

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows. That is, in the input/output part P-well region where the input/output part, electrostatic protection circuit, etc. are formed, for example, a first N-type diffusion layer connected to the power supply voltage of the circuit is connected to the ground potential of the circuit with its collector as the first N-type diffusion layer. A lateral bipolar transistor having the second N-type diffusion layer as its emitter and the P-well region as its base, or a third N-type transistor having the P-well region as its anode and coupled to the ground potential of the circuit.
A well charge emitting portion including a diode having the type diffusion layer as its cathode is provided.

[0008]

[Operation] According to the above means, the charge flowing from the electrostatic protection circuit into the P-well region due to high voltage noise input from the external terminal is transferred to the power supply voltage or ground potential of the circuit through the lateral bipolar transistor or diode. It can be released to As a result, a dynamic RAM or the like having a triple well structure can be realized without deteriorating its characteristics or increasing the chip area. As a result, it is possible to promote the triple well structure of dynamic RAM, etc., and improve its operating characteristics.

[0009]

[Embodiment] FIG. 1 shows a board layout diagram of an embodiment of a dynamic RAM to which the present invention is applied, and FIGS. 2 and 3 show input/output sections included in the dynamic RAM of FIG. A cross-sectional structure diagram and a layout diagram of one embodiment of the P-well region IOPW are shown. Further, FIGS. 4 and 5 respectively show a layout diagram and a cross-sectional structural diagram of an embodiment of the electrostatic protection circuit ESD formed in the input/output part P well region IOPW of FIG. 2, and FIG. Its equivalent circuit diagram is shown. Further, FIG. 7 shows a layout diagram of an embodiment of the well charge discharge part WQS formed in the input/output part P well region IOPW of FIG. 2, and FIG. 8 shows an equivalent circuit diagram thereof. There is. Based on these figures, an overview of the configuration and operation of the dynamic RAM of this embodiment as well as its characteristics will be described. Note that the following explanation will focus on the input/output section P well region IOPW, which is the subject of the present invention, and will omit explanation regarding the specific configuration and operation of the memory array section and its direct peripheral circuits.

In FIG. 1, the dynamic RAM of this embodiment has a pair of memory array parts ARY1 arranged occupying most of a P type (first conductivity type) semiconductor substrate PSUB made of single crystal silicon as a base material. and ARY2. These memory array sections are basically constructed of one-element type dynamic cells arranged in a lattice pattern, and have a complementary type M
Each includes a direct peripheral circuit such as an address decoder whose basic structure is an OSFET (metal oxide semiconductor field effect transistor; in this specification, MOSFET is a general term for insulated gate field effect transistor).

In the center of the P-type semiconductor substrate PSUB sandwiched between the memory array parts ARY1 and ARY2, there is a
An input/output part P well region IOPW is formed, and its left side (
In this specification, a substrate potential generation circuit VBBG1 for the memory array portion is formed in the upper, lower, left, and right sides of the semiconductor substrate surface (represented by the positional relationship in each layout diagram or cross-sectional structural diagram). Among these, the substrate potential generation circuit VBBG1 forms a substrate potential VBB1 of a predetermined negative potential based on a power supply voltage VCC such as +5V supplied from the outside, and generates a substrate potential VBB1 of a predetermined negative potential, that is, a P-type It is supplied to the semiconductor substrate PSUB. This improves the information retention characteristics of the dynamic cells that make up each memory array.
Erroneous inversion of stored data due to α rays is suppressed.

Next, the input/output section P well region IOPW is
It includes a plurality of bonding pads PAD arranged in a straight line, a plurality of input circuits IC and output circuits OC, and an electrostatic protection circuit ESD provided corresponding to these bonding pads. In this embodiment, the input/output part P well region IOPW is an N-type (second conductivity type) well region NWELL (first well region) formed in a P-type semiconductor substrate PSUB, as shown in FIG. A P-type (first conductivity type) well region PWELL (second well region) formed therein is used as a base. A circuit power supply voltage VCC (first power supply voltage) is supplied to the N well region NWELL. Thereby, the input/output section P well region IOPW is electrically isolated from the P-type semiconductor substrate PSUB in which the memory array sections ARY1 and ARY2 are formed.

Here, as shown in FIG. 4, each of the electrostatic protection circuits ESD provided in the input/output P well region IOPW has a relatively long and narrow N
Contains type diffusion layer N+4. The diffusion layer N+4 is coupled to the aluminum wiring layer AL1 formed in the upper layer via a plurality of contacts, and is further connected to the aluminum wiring layer AL1.
1 to the corresponding bonding pad PAD. The diffusion layer N+4 is further formed by an aluminum wiring layer A.
Through L2, a diffused resistor R consisting of an N-type diffused layer N+7
G is coupled to one terminal of G. The other terminal of the diffused resistor RG is coupled to the N-type diffused layer N+8, ie, the source of the MOSFET QD, via the aluminum wiring layer AL3, and further coupled to the input terminal of the corresponding input circuit IC. The polysilicon layer serving as the source and gate of the MOSFET QD is coupled to the ground potential VSS (second power supply voltage) of the circuit via an aluminum wiring layer (not shown). As a result, the MOSFETQD shown in FIGS. 5 and 6
As shown in FIG. 2, it is in the form of a diode and acts as a clamp MOSFET between the corresponding input node, that is, the bonding pad PAD, and the ground potential of the circuit. As a result, the abnormally positive high voltage applied to the bonding pad PAD is clamped by the breakdown voltage between the source and drain of the MOSFET QD, and its level is limited.

The electrostatic protection circuit ESD further includes an N-type diffusion layer N+ 5 formed in close proximity to and opposite to the diffusion layer N+ 4 and surrounding the upper half of the diffusion layer N+ 4;
4 and another N type diffusion layer N+ 6 formed adjacently to and surrounding the lower half thereof. Of these, the diffusion layer N+ 5 is coupled to the power supply voltage VCC of the circuit via a plurality of contacts (not shown) and an aluminum wiring layer formed in the upper layer, and the diffusion layer N+ 6 is connected to a plurality of contacts (not shown) and the upper layer. It is coupled to the ground potential VSS of the circuit through an aluminum wiring layer formed in the circuit. As a result, the diffusion layer N+ 5 forms an NPN type lateral bipolar transistor T1 together with the diffusion layer N+ 4, as shown in FIGS.
+6 forms another lateral bipolar transistor T2 together with the diffusion layer N+4. As a result, the relatively large spike noise input to the bonding pad PAD is transferred to the circuit power supply voltage VC through the current path by the lateral bipolar transistors T1 and T2.
C or the ground potential VSS, thereby suppressing potential fluctuations in the input/output section P well region IOPW. Note that when the magnitude of the spike noise input to the bonding pad PAD exceeds the charge absorption capacity of the lateral bipolar transistors T1 and T2, a part of the charge accompanying the spike noise is transferred to P, which becomes the base of the input/output P well region IOPW. flows into the well area.

In this embodiment, the input/output section P well region IOPW further includes the input/output section and electrostatic protection circuit E.
It includes a substrate potential generation circuit VBBG2 for the input/output section P well region arranged on the left side of SD, and a well charge discharge section WQS arranged on the left side thereof. Among these, the substrate potential generation circuit VBBG2 forms a predetermined substrate potential VBB2 based on the circuit power supply voltage VCC, and
It is supplied to the P well region which becomes the base of PW. As described above, the input/output section P well region IOPW is connected to the N well region NWELL coupled to the power supply voltage VCC of the circuit.
It is electrically isolated from the P-type semiconductor substrate PSUB that serves as the base of the memory array parts ARY1 and ARY2. Therefore, the substrate potential VBB2 supplied to the input/output section P well region IOPW can have a different absolute value from the substrate potential VBB1 supplied from the substrate potential generating circuit VBBG1 to the P-type semiconductor substrate PSUB.

As is well known, the input/output section P well region IO
PW, that is, the substrate potential VBB2 supplied to the input/output section of the dynamic RAM is assumed to be a negative potential with a relatively large absolute value, considering the influence of negative spike noise input from the external terminal on the operation of the internal circuit. It is desirable that Also, the substrate potential VBB1 supplied to the P-type semiconductor substrate SUB, that is, the memory array parts ARY1 and ARY2.
In order to suppress leakage current, improve the information retention characteristics of memory cells, and reduce the width of the MOSFET depletion layer to suppress the trap probability of minor carriers caused by α rays, the absolute value of N that makes up the cell
It is desirable to reduce the potential gradient between the type diffusion layer and the P-type semiconductor substrate. As a result of these, dynamic RA
In order to improve the overall characteristics of M, the substrate potential V
It is desirable that the absolute values of BB1 and VBB2 are not the same, and as in this embodiment, the P-type semiconductor substrate PSUB to which the substrate potential VBB1 is supplied and the input/output part P well region IOPW to which the substrate potential VBB2 is supplied are electrically connected. It is a necessary condition that they be separated.

Next, as shown in FIG. 3, the well charge discharge part WQS of the input/output part P well region IOPW is connected to the N type diffusion layer N+1 (first diffusion layer) coupled to the power supply voltage VCC of the circuit. ), and an N-type diffusion layer N+ formed opposite to this diffusion layer N+1 and coupled to the ground potential VSS of the circuit.
2 (second diffusion layer). These diffusion layers have a so-called comb-like shape, and the extension distance of the opposing portions is relatively long. This results in diffusion layers N+1 and N
As shown in FIGS. 7 and 8, +2 has its collector coupled to the circuit ground potential VCC, its emitter coupled to the circuit ground potential VSS, and is connected to the P well region PWELL of the input/output section P well region IOPW. A lateral bipolar transistor T3 having a base thereof is constructed.

As mentioned above, the bonding pad PAD
When a large spike noise that exceeds the charge absorption capacity of the lateral bipolar transistors T1 and T2 constituting the electrostatic protection circuit ESD is input, a part of the accompanying charge is transferred to the P well region of the input/output section P well region IOPW. It flows in and accumulates. When the charge flowing into the P-well region is a positive charge and the potential of the P-well region rises and exceeds its base-emitter voltage, the lateral bipolar transistor T3 is turned on, thereby discharging the accumulated charge in the P-well region into the circuit. It is released to power supply voltage VCC or ground potential VSS. In addition, if the charge flowing into the P-well region is a negative charge and the potential of the P-well region decreases and exceeds a predetermined voltage, the lateral bipolar transistor T
3 enters an avalanche breakdown state, whereby the charges accumulated in the P-well region are released to the circuit power supply voltage VCC or ground potential VSS. Further, if an abnormally high voltage is applied between the power supply voltage VCC and the ground potential VSS of the circuit, the lateral bipolar transistor T3 similarly enters a breakdown state, and has the function of limiting the potential difference. In addition, as shown in FIG. 3, the lateral bipolar transistor T3 has a relatively large size because the diffusion layers N+1 and N+2 have a comb-like shape and the extension distance of the opposing portions is relatively long. It is said to have charge absorption ability. As a result, the electrostatic withstand voltage characteristics of dynamic RAM can be improved without increasing the capacity of the input/output section, and dynamic RAM
It is possible to promote triple well structure such as M and improve its operating characteristics.

The input/output section P well region IOPW further includes another N type diffusion layer N+3 (third diffusion layer) coupled to the circuit ground potential VSS. As shown in FIGS. 7 and 8, the diffusion layer N+ 3
constitutes a PN junction, that is, a diode D1, with P well region PWELL as a cathode and P well region PWELL as an anode. As described above, the substrate potential VBB2, which is a predetermined negative potential, is supplied to the anode of the diode D1, ie, the P-well region PWELL. Therefore, the diode D1 is normally in a cut-off state, and when the potential of the P-well region PWELL becomes higher than its forward voltage with respect to the circuit ground potential VSS, the positive voltage accumulated in the input/output section P-well region IOPW is It has the function of discharging the charge to the ground potential VSS of the circuit. Similarly, when the potential of the P well region PWELL becomes lower than the breakdown voltage of the circuit ground potential VSS, the input/output portion P well region IO
It has the function of releasing the negative charge accumulated in PW to the ground potential VSS of the circuit. As a result, the electrostatic breakdown voltage characteristics of the dynamic RAM are further improved.

As shown in the above embodiment, the present invention can be applied to a dynamic RAM or the like having a plurality of bonding pads coupled to external terminals and electrostatic protection circuits provided corresponding to these bonding pads. By applying it to a semiconductor device, the following effects can be obtained. That is, (1) In the input/output part P-well region where the input/output part and the electrostatic protection circuit etc. are formed, for example, the first N-type diffusion layer coupled to the power supply voltage of the circuit is used as its collector to ground the circuit. A lateral bipolar transistor having a second N-type diffusion layer coupled to the potential as its emitter and a P-well region as its base, or a third N-type diffusion layer having the P-well region as its anode and coupled to the circuit ground potential. By providing a well charge discharge section including a diode with the layer as its cathode, the charge flowing from the electrostatic protection circuit into the P well region and accumulated due to high voltage noise input from an external terminal is removed from the lateral bipolar layer. The effect is that it can be discharged to the power supply voltage or ground potential of the circuit via the transistor or diode. (2) Item (1) above has the effect of releasing positive or negative charges accumulated in the electrically isolated input/output P-well region etc. due to spike noise etc. input from external terminals. can get. (3) Items (1) and (2) above provide the effect that a dynamic RAM with a triple well structure can be realized without deteriorating its characteristics or increasing the chip area. (4) Items (1) to (3) above have the effect of promoting the triple well structure of dynamic RAMs and the like and improving their operating characteristics.

[0021] Above, the invention made by the present inventor has been specifically explained based on examples, but this invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. It goes without saying that there is. For example, in FIG. 1, the input/output part P well region IOPW is
For example, it can be divided into a plurality of parts and formed on the upper and lower parts of the P-type semiconductor substrate PSUB, and the arrangement position thereof can be arbitrarily set according to the arrangement position of the bonding pad and the input/output section. In addition, dynamic RA
M can include a plurality of substrate potential generation circuits VBBG1, and various embodiments may be considered for the specific substrate arrangement. In FIG. 3, FIG. 7, and FIG. 8, the N-type diffusion layers N+ 1 and N+ 2 constituting the lateral bipolar transistor T3 can take any shape as long as the extension distance of the opposing portions is long. can. Further, the input/output part P well region IOPW may include only one of the lateral bipolar transistor T3 and the diode D1, or may include a plurality of each of the lateral bipolar transistors T3 and the diode D1. good. Input/output section P well area I
The OPW can include a plurality of substrate potential generation circuits VBBG2, and its specific layout can take various embodiments. In FIGS. 4 to 6, the specific configuration of the electrostatic protection circuit ESD is not limited by these embodiments. Furthermore, the polarity and absolute value of the power supply voltage supplied to the dynamic RAM are arbitrary.

In the above explanation, the invention made by the present inventor was mainly applied to a dynamic RAM, which is the field of application that formed the background of the invention.
The present invention is not limited thereto, and can be applied to various memory integrated circuits such as static RAM, gate array integrated circuits, etc., for example. The present invention can be widely applied to semiconductor devices having at least a bonding pad coupled to an external terminal and an electrostatic protection circuit provided corresponding to the bonding pad.

[0023]

Effects of the Invention: In the input/output part P-well region where the input/output part and the electrostatic protection circuit etc. are formed, for example, the first N-type diffusion layer connected to the power supply voltage of the circuit is used as its collector to ground the circuit. A lateral bipolar transistor having a second N-type diffusion layer coupled to the potential as its emitter and a P-well region as its base, or a third N-type diffusion layer having the P-well region as its anode and coupled to the circuit ground potential. By providing a well charge discharge section including a diode with the layer as its cathode, the charge that flows from the electrostatic protection circuit into the P well region due to high voltage noise input from an external terminal and is accumulated is transferred to the lateral bipolar transistor. Alternatively, it can be discharged to the circuit power supply voltage or ground potential via a diode. As a result, a dynamic RAM or the like having a triple well structure can be realized without deteriorating its characteristics or increasing the chip area. As a result, it is possible to promote the triple well structure of dynamic RAM and the like, and further improve the operating characteristics thereof.

[Brief explanation of the drawing]

FIG. 1 is a board layout diagram showing an embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a cross-sectional structural diagram showing an example of an input/output P-well region included in the dynamic RAM of FIG. 1;

FIG. 3 is a layout diagram showing one embodiment of the input/output section P well region of FIG. 2;

FIG. 4 is a layout diagram showing an example of an electrostatic protection circuit formed in the input/output P well region of FIGS. 2 and 3;

FIG. 5 is a cross-sectional structural diagram showing an example of the electrostatic protection circuit of FIG. 4;

6 is an equivalent circuit diagram of the electrostatic protection circuit of FIG. 4. FIG.

7 is a cross-sectional structural diagram showing an example of a well charge emitting section formed in the input/output section P well region of FIGS. 2 and 3; FIG.

FIG. 8 is an equivalent circuit diagram of the well charge discharge section in FIG. 7;

[Explanation of symbols]

PSUB...P-type semiconductor substrate, ARY1~ARY2・
...Memory array section, IOPW...Input/output section P well region, VBBG1-VBBG2...Substrate potential generation circuit, NWELL...N well region, WQS...Well charge discharge section, PAD...Bonding Pad, IC・
...Input circuit, OC...Output circuit, ESD...Electrostatic protection circuit. N+ 1 to N+ 8...N type diffusion layer, T
1 to T3...Lateral bipolar transistor, D1
... Diode, RG... Diffused resistance, QD... Clamp MOSFET, AL1 to AL3... Aluminum wiring layer.

Claims (5)

[Claims] 1. An electrostatic protection circuit formed in a second well region of a first conductivity type formed in a first well region of a second conductivity type formed in a semiconductor substrate of a first conductivity type; A semiconductor device comprising: a well charge discharge section that discharges the charges accumulated in the second well region. 2. The well charge emitting section has the second well region as its base, the first diffusion layer coupled to the first power supply voltage as its collector, and the well charge discharge region coupled to the second power supply voltage. A second diffusion layer formed opposite to the first diffusion layer.
2. The semiconductor device according to claim 1, further comprising a lateral bipolar transistor having a diffusion layer of as an emitter. 3. The well charge emitting section includes a diode having the second well region as its anode and the third diffusion layer coupled to the first power supply voltage as its cathode. 2. The semiconductor device according to claim 1. 4. The semiconductor device is a dynamic type RA.
A bonding pad and an input circuit and/or an output circuit are further formed in the second well region, and a memory array and its immediate surroundings are formed outside the second well region of the semiconductor substrate. 4. A semiconductor device according to claim 1, wherein a circuit is formed therein. 5. A first substrate potential is supplied to the semiconductor substrate, and a second substrate potential whose absolute value is different from the first substrate potential is supplied to the second well region. 5. The semiconductor device according to claim 1, 2, 3, or 4.