JPS6149456A - Mos type semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent a change into a positive value of substrate voltage by forming a MOSFET for clamping substrate voltage in which a drain and a gate are connected to a substrate and a source is connected to a ground. CONSTITUTION:A bonding pad 3 is connected to a die frame for a package with which a chip 1 for a MOS dynamic RAM is die-bonded, and substrate voltage is applied to a substrate for the chip 1. When a memory cell is formed generally by using a process of double layer poly Si, a memory cell plate is constituted by first poly Si, but a gate oxide film in first poly Si is thinned extremely. A grounding wiring 4 and an output 5 from a substrate-voltage generating circuit are wired so as to make a round on the outer circumference of the chip 1. Accordingly, when a first poly Si gate FET in which a drain and a gate are connected to the wiring 5 in a transistor region 8 for clamping substrate voltage and a source is connected to the wiring 4 is formed, a MOSFET for clamping substrate voltage having extremely low threshold voltage can be constituted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a MOS type semiconductor integrated circuit provided with a substrate voltage clamp circuit.

[Prior art]

In current MOS type semiconductor integrated circuits, especially MOS dynamic RAM, it is difficult to unify the power supply, and it has become common to generate the substrate voltage by a substrate voltage generation circuit provided on the chip. .

Figure 1 shows a MOS with a built-in conventional substrate voltage generation circuit.
Relationship between substrate voltage and power supply voltage in semiconductor integrated circuits!
show.

In Fig. 1, the substrate voltage is VB, and the power supply voltage '1
Vcc, the relationship between the two is clear from Figure 15.
When the power supply voltage VCC is relatively low, the substrate voltage vRB becomes deeply negative in proportion to the power supply voltage VCC Ic, but as the power supply voltage VCC increases, it becomes shallower, and when it becomes very high, K becomes a positive voltage. There is also.

The reason for this is that when the power supply voltage Vcc increases and the current consumption increases, the hole current in the substrate due to impact ionization increases, and the charging current from the substrate voltage generation circuit cannot compensate for this current. This situation will not occur if the semiconductor integrated circuit is used at a power supply voltage within the guaranteed operation range.
If a high voltage is applied to the semiconductor integrated circuit due to some reason such as handling error, the pn junction will be biased in the forward direction and the substrate voltage will rise, potentially causing permanent damage to the semiconductor integrated circuit.

Figures 2 (a) and (b) show the power supply voltage V at the time of power-on of a semiconductor integrated circuit with a built-in substrate voltage generation circuit when a relatively large capacitance is formed between the power supply line and the substrate.
The waveforms of cc and substrate voltage vBB are shown. FIG. 2(a) shows the relationship between power supply voltage Vcc and time, and FIG. 2(b) shows the relationship between t'! Substrate voltage v! It also shows the relationship between lIl and time. It takes a certain amount of time for the substrate voltage generation circuit to generate a sufficient voltage after power is turned on. Therefore,
If the power supply voltage VCC rises sharply in the evening, Fig. 2(a),
(b) As shown in the diagram, there is a period in which the substrate voltage IIB becomes positive due to capacitive coupling between the power supply line and the substrate. If this substrate voltage vIIB rises significantly, it may cause permanent destruction of the Kkl semiconductor integrated circuit, and even if destruction VC does not occur, there is a drawback that an extremely large inrush power supply current will flow. .

[Summary of the invention]

This invention was made to improve the above-mentioned drawbacks.
It is a MOS type semiconductor integrated circuit with a built-in substrate voltage generation circuit, the input and gate are connected to the substrate, and the source is connected to the ground.
) By providing a transistor, a highly reliable MOS type semiconductor integrated circuit is provided which can prevent the substrate voltage from becoming positive. This invention will be explained below with reference to the drawings.

[Embodiments of the invention]

FIG. 4 shows an embodiment of the invention, and FIG. 3 shows an equivalent circuit Z of the invention.

In FIG. 3, when the voltage of the semiconductor substrate becomes positive and exceeds the threshold voltage of the substrate voltage clamping MOS transistor T (this threshold voltage is referred to as YVra), the substrate voltage clamping MOS transistor T becomes conductive. state, the board is discharged and the rise in board voltage is suppressed. Therefore, it is more effective for this invention to set the threshold voltage VT11YO of the transistor T (MOS for substrate voltage clamping) to as low a value as possible within the range of 0 volts or more and less than the built-in potential of the pn junction. The channel width of the substrate voltage clamping MOS transistor T is made thicker in order to quickly discharge the voltage.

FIG. 4 shows a MOS dynamic RAMK having a one-transistor/one-capacitor type memory structure, which is a practical example of this invention. In Fig. 4, 1 is a MOS dynamic RA
M chip, 2 is the bonding band of the ground terminal,
3 is a bonding pad of the output terminal of the substrate voltage generation circuit, and this bonding pad 3t is connected to the die frame (not shown) of the package in which the chip 1 is attached to the tie pad 3H, and a substrate voltage is applied to the substrate of the chip 1. .

Reference numeral 4 designates a ground wire that goes around the outer periphery of the chip 1, and 5 designates an output wire that goes around the outer periphery of the chip 1 for the output of the substrate voltage generation circuit. 6 is a memory cell 7 lay region, T is a memory peripheral circuit region, and 8 is a substrate voltage clamping transistor region forming a substrate voltage clamping transistor.

1 transistor/1 capacitor type memory cells are generally manufactured using a multilayer polysilicon process 2. For example, in the case of AJJ using a two-layer polysilicon process, the memory cell plate is made of polysilicon, and the transfer gate of the memory cell and the gate of the peripheral circuit transistor are made of the second polysilicon. However, the gate oxide film of the first polysilicon is extremely thin in order to increase the storage capacity 2 of the memory cell. Therefore, if the first polysilicon is used as the gate to form a transistor, the substrate voltage clamping MOS transistor T can be formed without requiring any special ion implantation.
A transistor with a low threshold voltage VTII can be obtained. For example, when the gate oxide film of the first polysilicon is 160 to 200A and the gate oxide film of the second polysilicon is 350 to 400A, the second
Threshold voltage VTH of polysilicon gate transistor
If IJ″-O, SV is about the same, the channel length is about 3 μm.
The threshold voltage vTH of the first polysilicon gate transistor is approximately 0.1 to 0.2V. Furthermore, for various reasons, the ground wiring 4 and the wiring 5 for the output of the substrate voltage generation circuit 9 are wired so as to go around the outer periphery of the chip 1.
In the substrate voltage clamping transistor region 8 shown in the shaded area in the figure, the drain and gate are connected to the output arrangement fj5Vc of the substrate voltage generation circuit, and the source is connected to the ground wiring 4. By providing a gate transistor Z, it is possible to create a substrate voltage clamping MOS (MOS) transistor with an extremely low threshold voltage vTH and an extremely large channel width without adding a special process and also increasing the chip area. It is possible to form a forest without any problems.

〔Effect of the invention〕

To explain the above, this invention has a MOSO8 type conductor integrated circuit board with a built-in substrate voltage generation circuit, the drain and gate are connected to the output of the substrate voltage generation circuit, and the source is connected to the ground. MOS for voltage clap)
Since it is a 74M O8 type half integrated circuit equipped with a transistor, it has the advantage of preventing the substrate voltage from becoming positive and providing a highly reliable MOS type semiconductor integrated circuit.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the relationship between the substrate voltage and power supply voltage in an rsMOS type semiconductor integrated circuit with a built-in conventional substrate voltage generation circuit, and Figure 2 is a diagram showing the power supply voltage when the power is turned on for the type half-integrated circuit shown in Figure 1. Figure 2 (a) is a diagram showing the waveform and substrate voltage waveform 2.
is a voltage waveform diagram that represents the relationship between power supply voltage and time, and the same figure (
FIG. 3 is an equivalent circuit diagram for explaining the present invention, and FIG. 4 is a configuration diagram showing a second embodiment of the present invention. In the figure, 1 is a chip, 2 is a bonding band of a ground terminal, 3 is a bonding band of an output terminal of a substrate voltage generation circuit, 4 is a ground wiring, 5 is an output wiring of the substrate voltage generation circuit, 6 is a memory cell array area, 7 is a peripheral circuit area, 8 is a transistor area for clamping the substrate voltage, and 2 is a MOS transistor area for clamping the substrate voltage. Note that the same reference numerals in the drawings indicate the same parts, and L indicates corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 2 Figure 3 Figure 4 1 l j

Claims (3)

[Claims] (1) A substrate voltage generation circuit is built into the substrate of a MOS semiconductor integrated circuit, and a substrate voltage clamping MOS transistor is provided, the drain and gate of which are connected to the output of the substrate voltage generation circuit, and the source of which is connected to ground. A MOS type semiconductor integrated circuit characterized by the following. (2) The threshold voltage of the substrate voltage clamping MOS transistor is 0 volts or more and less than or equal to the built-in potential of the pn junction.
1) MOS type semiconductor integrated circuit as described in item 1). (3) A MOS type semiconductor integrated circuit is a MOS dynamic RAM with a one-transistor/one-capacitor type memory cell structure using a multilayer polysilicon process, and the memory cell plate and the gate of the MOS transistor for substrate voltage clamping are in the same layer. MO according to claim 1, characterized in that the MO is made of polysilicon of
S-type semiconductor integrated circuit.