JPH11340339A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device whose malfunction is hardly generated when an undershoot is superposed on an input signal. SOLUTION: A node N1 to which an input signal is given is connected to the drain of an N-channel transistor 74a whose gate and source are coupled to a ground potential. The source part of the N-channel transistor 74a is formed on the sidewall of a trench part 86. Consequently, since an open angle α at which electrons are injected into a P-type silicon substrate 120 from the node N1 is restricted by an n<+> region 88 as the source part of the N-channel transistor 74a, the amount of the electrons which are injected can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having an element for preventing an undershoot of an input signal.

[0002]

2. Description of the Related Art At present, microcomputers are used in various electric products such as personal computers and workstations.
Various semiconductor devices including a memory and a gate array are mounted.

Many of these semiconductor devices are MOS (Metal Oxide Silicon) suitable for high integration and low power consumption.
) It is composed of transistors.

[0004] In recent years, a memory having a large capacity has been developed.
DRAM (Dynamic Random Access Memory) used as one of the main memories of personal computers and workstations as one that includes an S transistor
y) there.

FIG. 134 shows an input protection circuit disclosed in Japanese Patent Application Laid-Open No. 61-232658.

Referring to FIG. 134, this input protection circuit includes a terminal EN for receiving various signals input from the outside.
, A resistor 502 connected between a node Ni connected to the terminal EN and a node Nj, and a P-channel transistor 508 connected to the gate of the node Nj and having a source and a channel forming region at the internal power supply potential Vcc. When,
The node Nj is connected to the gate and the source is at the ground potential Vss.
And an N-channel transistor 510 whose drain is connected to the drain of P-channel transistor 508 with the potential of the channel formation region at substrate potential VBB. N-channel transistor 510 has a drain connected to an output node IOUT for transmitting an input signal to an internal circuit of the semiconductor device.
Becomes

The input protection circuit further includes a p ⁺ -n ^- junction diode 504 having an anode connected to node Nj and a cathode connected to internal power supply potential Vcc, and an anode connected to ground potential Vss and a cathode connected to node Nj. And a connected p ⁺ -n ⁺ junction diode 506.

A signal input to the input terminal EN from the outside passes through a resistor 502 and an N-channel transistor 510 and a P-channel transistor 508 which are input inverters.
Is transmitted to each gate. When the signal transmitted to the node Nj is higher than the internal power supply potential Vcc or lower than the ground potential Vss, the junction diode 50
4, 506 functions as a clamp circuit. The threshold values of the junction diodes 504 and 506 are set to V504 and V50, respectively.
6, when an input voltage equal to or more than (Vcc + V504) is applied, the junction diode 504 operates and the node Nj
Is prevented from exceeding (Vcc + V504).

When an input potential equal to or lower than V506 is applied, the junction diode 506 operates to prevent the node Nj from lowering to V506 or lower.

As described above, this input protection circuit protects the internal circuit. FIG. 135 is a cross-sectional view for illustrating a cross-sectional structure of resistor 502 shown in FIG.

Referring to FIG. 135, a resistor 502 is an n ⁺ diffusion resistance and is formed in a P well 514 formed on a P-type silicon substrate 512. The resistor 502 is covered on both sides with an isolation oxide film 516.

FIG. 136 shows an example of an input waveform of a signal input from the outside to the semiconductor device. Referring to FIG. 136, it is assumed that input high level VIH of this input signal is internal power supply potential Vcc, and input low level VIL is 0V. An undershoot of 0 V or less is observed in the portion A immediately after the input level falls from the high level to the low level, and the internal power supply potential Vcc or more in the portion B immediately after the waveform 514 rises from the low level to the high level. Overshoot is on waveform 514.

The substrate potential VBB = -1.5 V is applied to the P-type silicon substrate on which the input protection circuit shown in FIG. 134 is formed.
Is applied. For example, if the semiconductor device is a DRAM, if the undershoot is -1.
When the voltage becomes 5 V or less, it is considered that the data held in the memory cells formed on the same substrate is adversely affected.

FIG. 137 is a cross sectional view showing a part of the input protection circuit and a cross section of the memory cell portion. When an undershoot of -1.5 V or less is applied to the resistor 502, which is an n ⁺ diffusion resistor, a forward voltage is applied to the PN junction at the boundary between the resistor 502 and the P well 514, and electrons 519 are transferred to the P well 514. Injected inside. The injected electrons are in P well 5
It migrates as a minority carrier in the 14 and P-type silicon substrate 512 until recombination occurs.

[0015] In Figure 137, n ⁺ regions of the n ⁺ region and a memory cell of the input protection circuit is formed without being completely separated. The injected electrons convert electric energy into kinetic energy and travel straight through the silicon substrate to some extent.

After that, it interacts with silicon atoms and impurity atoms to be scattered and further diffused. At this time, if a large amount of electrons are absorbed in the n ⁺ region 520 of the memory cell holding H (high) data formed on the P well 514 which is not separated from the P-type silicon substrate, the memory cell data Becomes L (low), causing data destruction.

If the lifetime of the injected electrons is long, the electrons migrate a long distance. Therefore, in order to prevent data destruction, it is necessary to increase the distance between the input protection circuit and the memory cell. If this distance is increased, there is a problem that the chip area increases.

If the chip area increases, there arises a problem that the manufacturing cost increases. Next, an electron injection aperture angle which is important in considering the distance between the memory cell and the n ⁺ diffusion region where electron injection occurs will be described.

FIG. 138 is a plan view of a transistor having a conventional structure. Referring to FIG. 138, this transistor has N
A channel transistor which is surrounded by the element isolation region 532 and includes a gate electrode 534, an n ⁺ region 538 serving as a drain, and an n ⁺ region 536 serving as a source.

FIG. 139 is a sectional view showing a section taken along line XX 'in FIG. 138. Referring to FIG. 139, this transistor is formed in a P well 543 formed on a P-type silicon substrate 542, has an n ⁺ region 538 serving as a drain in a portion sandwiched between gate electrodes 534, and has a gate electrode An n ⁺ region 536 serving as a source is formed in a region outside 534. An oxide film for element isolation 544 is formed outside the n ⁺ region 536. n ⁺ region 53
8 is connected to a node Cin to which an undershoot causing injection of electrons is applied.

Here, d _n is the junction depth of the n ⁺ region. d _L is the depth of the insulating film into which the insulating film 544 for element isolation has penetrated into the silicon substrate. L is the input signal input n
The distance from the ⁺ region 538 to the element isolation insulating film 544. L _L is the element isolation insulating film 544 insulating film depth d _L
It is the distance to enter. α is an opening angle at which electrons are injected in the XX ′ section (hereinafter, referred to as an electron injection opening angle).

FIG. 140 is a sectional view showing a section taken along line YY 'in FIG. 138. Referring to FIG. 140, an n ⁺ region 538 to which an input signal is applied is formed in a P well 543 on a P type silicon substrate 542, and an insulating film 544 for element isolation is formed on both sides thereof. I have. Here, y _L is the joining length in the YY ′ section. β is the electron injection aperture angle in the y direction.

From the above, the electron injection aperture angles α and β are represented by the following equations. ^{α = π / 2-tan -1} ((d L -d n) / (L + L L)) ... (1) β = π / 2-tan -1 ((d L -d n) / (y L + L L )) (2) In order for the electrons injected into the n ⁺ region 538 in FIG. 138 to migrate more widely than the transistor region (element region),
In the x direction, electrons need to be injected at an opening angle α or less.

In the y direction, electrons need to be injected at an opening angle β or less. The reason for this is that since there are usually many recombination centers at the interface between the element isolation insulating film and the silicon substrate, the electrons that are problematic are electrons that escape without colliding with the element isolation insulating film.

[0025]

SUMMARY OF THE INVENTION In a DRAM,
Further cost reduction and higher performance are required. One of the performance enhancements is to increase the speed.

The operating frequency of microprocessors has been improving year by year, and high-speed DRAMs have been demanded. These DR
AM must correspond to a noisy input waveform with undershoot and overshoot.

In particular, a DRAM having a P-type substrate twin well structure
As described above, as described above, there is a problem that electrons due to undershoot are injected from the n ⁺ diffusion layer formed on the substrate of the input protection circuit and memory cell data is destroyed.

Also, in a semiconductor device in which an analog circuit and a digital circuit are mixed, for example, there is a problem that the analog output section of a DA (digital-analog) conversion circuit is distorted.

A first object of the present invention is to provide an undershoot countermeasure element for improving resistance to undershoot causing memory data destruction and analog output distortion, and a semiconductor device provided with this undershoot countermeasure element. .

It is a second object of the present invention to provide an undershoot preventing element in which electron injection into the substrate due to undershoot does not easily occur and a semiconductor device provided with the undershoot preventing element.

[0031]

A semiconductor memory device according to claim 1 is a semiconductor device formed on a main surface of a semiconductor substrate of a first conductivity type, wherein a ground potential applied from outside the semiconductor device is provided. Terminal receiving the input signal, an input terminal receiving an input signal input from outside the semiconductor device, an internal node electrically coupled to the input terminal, and an internal circuit performing a predetermined operation in response to a signal on the internal node. And undershoot countermeasure means for setting the potential of the internal node to the first potential or more at the time of undershoot input in which the potential of the input terminal is equal to or lower than the first potential lower than the ground potential. Formed on the internal node and the first
And a switching element coupled to form a path that can conduct between the switching element and the switching element, which is provided adjacent to the switching element and inhibits migration of electrons injected from the switching element into the semiconductor substrate when an undershoot is input. And a trench portion to be formed.

According to a second aspect of the present invention, in addition to the configuration of the semiconductor device of the first aspect, the switching element is formed on the main surface, and is provided between the internal node and the first constant potential. A MOS transistor of a second conductivity type coupled to form a path capable of conducting to the first node, the MOS transistor having a first impurity region of a second conductivity type connected to an internal node, and a first constant potential. A second impurity region of a second conductivity type to be coupled, and a gate electrode located on a main surface interposed between the first impurity region and the second impurity region; Are deeper than the junction depth of the first impurity region and are in contact with the second impurity region.

According to a third aspect of the present invention, in the configuration of the semiconductor device according to the second aspect, the gate of the MOS transistor is coupled to the ground potential, the first conductivity type is P-type, The two conductivity types are N-type.

According to a fourth aspect of the present invention, in the configuration of the semiconductor device according to the second aspect, the first constant potential is a ground potential.

According to a fifth aspect of the present invention, in addition to the configuration of the semiconductor device of the second aspect, the semiconductor memory device further includes a power supply terminal receiving an externally applied power supply potential. This is a potential corresponding to the power supply potential.

According to a sixth aspect of the present invention, in addition to the configuration of the semiconductor device of the second aspect, in addition to the configuration of the semiconductor device of the second aspect, a power supply terminal receiving an externally applied power supply potential and boosting the power supply potential to an internal boosted potential are provided. And the first constant potential is an internal boosted potential.

According to a seventh aspect of the present invention, in the configuration of the semiconductor device according to the second aspect, the second impurity region surrounds the gate electrode and the first impurity region on the main surface, and has a trench portion. Opening surrounds the second impurity region on the main surface.

In a semiconductor memory device according to an eighth aspect, in addition to the structure of the semiconductor device according to the second aspect, the second impurity region includes a third impurity region formed on a side wall of the trench portion. .

According to a ninth aspect of the present invention, in the configuration of the semiconductor device according to the second aspect, the trench has an angle of 90 degrees between a side wall in contact with the second impurity region and a main surface of the semiconductor substrate. °, and the bottom is wider than the opening.

According to a tenth aspect of the present invention, in addition to the configuration of the semiconductor device of the first aspect, the switching element is formed on the main surface and is of the second conductivity type connected to the internal node. A first impurity region formed on the main surface between the opening of the trench portion and the first impurity region, in contact with the first impurity region, and a junction of the first impurity region; An element isolation portion formed deeper than the depth, and a second impurity region of a second conductivity type formed at least on a sidewall of the trench portion deeper than the bottom of the element isolation portion and coupled to a first constant potential; The junction depth of the second impurity region is smaller than the distance between the trench portion and the first impurity region on the main surface.

In a semiconductor memory device according to an eleventh aspect, in the configuration of the semiconductor device according to the tenth aspect, the first conductivity type is a P-type and the second conductivity type is an N-type.

According to a twelfth aspect of the present invention, in the semiconductor memory device according to the tenth aspect, the first constant potential is a ground potential.

According to a thirteenth aspect of the present invention, in addition to the configuration of the semiconductor device of the tenth aspect, the semiconductor memory device further includes a power supply terminal receiving a power supply potential applied from the outside, and the first constant potential is This is a potential corresponding to the power supply potential.

According to a fourteenth aspect of the present invention, in addition to the configuration of the semiconductor device of the tenth aspect, a power supply terminal receiving an externally applied power supply potential, and a power supply potential boosted to an internal boosted potential are provided. And the first constant potential is an internal boosted potential.

According to a fifteenth aspect of the present invention, in the configuration of the semiconductor device according to the tenth aspect, the element isolation portion surrounds the first impurity region on the main surface,
The opening of the trench surrounds the element isolation portion on the main surface.

In a semiconductor memory device according to a sixteenth aspect of the present invention, in the configuration of the semiconductor device according to the tenth aspect, the angle between the side wall and the main surface of the semiconductor substrate is 90 °.
The bottom is wider than the opening.

According to a seventeenth aspect of the present invention, in addition to the configuration of the semiconductor device of the first aspect, the switching element is formed on the main surface, and is provided between the internal node and the first constant potential. A MOS transistor of the second conductivity type coupled to form a path that can conduct to the MOS transistor, and an element isolation portion formed between the opening of the trench portion and the MOS transistor on the main surface. A first impurity region of a second conductivity type having a shallower junction depth than the bottom of the element isolation portion and connected to an internal node; and a second impurity region of a second conductivity type coupled to a first constant potential. A region, and a gate electrode located on a main surface interposed between the first impurity region and the second impurity region, and the second impurity region is in contact with the element isolation portion on the main surface.

In the semiconductor memory device according to the eighteenth aspect, in the configuration of the semiconductor device according to the seventeenth aspect, the gate of the MOS transistor is coupled to the ground potential, the first conductivity type is P-type, The two conductivity types are N-type.

According to a nineteenth aspect of the present invention, in the semiconductor memory device according to the seventeenth aspect, the first constant potential is a ground potential.

According to a twentieth aspect of the present invention, in addition to the configuration of the semiconductor device according to the seventeenth aspect, the semiconductor memory device further includes a power supply terminal receiving an externally applied power supply potential. This is a potential corresponding to the power supply potential.

According to a twenty-first aspect of the present invention, in addition to the configuration of the semiconductor device of the seventeenth aspect, a power supply terminal receiving an externally applied power supply potential, and a power supply potential boosted to an internal boosted potential are provided. And the first constant potential is an internal boosted potential.

In a semiconductor memory device according to a twenty-second aspect, in the configuration of the semiconductor device according to the seventeenth aspect, the element isolation portion surrounds the MOS transistor on the main surface, and the opening of the trench portion is formed on the main surface. Surrounds the element isolation portion.

According to a twenty-third aspect of the present invention, in addition to the configuration of the semiconductor device of the seventeenth aspect, the switching element is formed on a side wall of the trench portion and coupled to the second constant potential. 3 impurity regions.

According to a twenty-fourth aspect of the present invention, in the semiconductor memory device according to the second aspect, the trench is formed such that an angle formed between the side wall and the main surface of the semiconductor substrate is less than 90 °. And the bottom is wider than the opening.

A semiconductor memory device according to a twenty-fifth aspect further includes a resistor connected between an input terminal and an internal node, in addition to the configuration of the semiconductor device according to the first aspect.

According to a twenty-sixth aspect of the present invention, in addition to the configuration of the semiconductor device of the first aspect, the semiconductor memory device is connected to an internal node, and the potential of the input terminal is equal to or higher than a second potential higher than the ground potential. A positive surge countermeasure for reducing the potential of the internal node to a level equal to or lower than the second potential.

A semiconductor memory device according to a twenty-seventh aspect is a semiconductor device formed on a semiconductor substrate, comprising: a ground terminal receiving a ground potential applied from outside the semiconductor device;
An input terminal for receiving an input signal input from outside the semiconductor device, a first internal node connected to the input terminal, a signal received on the first internal node and transmitted to a second internal node, An undershoot countermeasure for setting the potential of the second internal node to be equal to or higher than the first potential when the potential becomes equal to or lower than the first potential lower than the ground potential; and a predetermined means for receiving a signal on the second internal node. An internal circuit formed on the semiconductor substrate for performing an operation; the undershoot countermeasure means includes a resistor connected between the first internal node and the second internal node; MO of the first conductivity type coupled to form a path capable of conducting with a constant potential
An MOS transistor, wherein the MOS transistor is formed in a semiconductor layer electrically separated by a semiconductor substrate and an insulating layer, and connected to a second internal node.
And a second impurity region of a first conductivity type formed in the semiconductor layer and coupled to a constant potential, and a first impurity region and a second impurity region formed in the semiconductor layer and forming a channel. A channel formation region of the second conductivity type sandwiched between the impurity regions; and a gate electrode provided adjacent to the channel formation region.

In a semiconductor memory device according to a twenty-eighth aspect, in the configuration of the semiconductor device according to the twenty-seventh aspect, the gate electrode is connected to the second internal node, and the first conductivity type is P
And the second conductivity type is an N-type, and the constant potential is a ground potential.

According to a twenty-ninth aspect of the present invention, in the configuration of the semiconductor device according to the twenty-eighth aspect, the channel formation region of the MOS transistor is floated.

A semiconductor memory device according to a thirtieth aspect of the present invention further includes, in addition to the configuration of the semiconductor device according to the twenty-eighth aspect, a power supply terminal receiving an externally applied power supply potential.
In the OS transistor, a channel formation region is set to a potential corresponding to a power supply potential.

In a semiconductor memory device according to a thirty-first aspect, in the configuration of the semiconductor device according to the twenty-seventh aspect, the gate electrode is coupled to a ground potential, the first conductivity type is N-type, and the second conductivity type is The type is a P type, and the constant potential is a ground potential.

In a semiconductor memory device according to a thirty-second aspect, in the configuration of the semiconductor device according to the thirty-first aspect, the channel formation region of the MOS transistor is floated.

In a semiconductor memory device according to a thirty-third aspect, in the configuration of the semiconductor device according to the thirty-first aspect, the channel formation region of the MOS transistor is set to the ground potential.

In a semiconductor memory device according to a thirty-fourth aspect, in the configuration of the semiconductor device according to the twenty-seventh aspect, the gate electrode is coupled to a ground potential, the first conductivity type is N-type, and the second conductivity type is N-type. The type is a P type, and the constant potential is a potential corresponding to a power supply potential.

According to a semiconductor memory device described in claim 35, in the configuration of the semiconductor device described in claim 34, the channel formation region of the MOS transistor is floated.

In a semiconductor memory device according to a thirty-sixth aspect, in the configuration of the semiconductor device according to the thirty-fourth aspect, in the MOS transistor, a channel formation region is set to a ground potential.

A semiconductor memory device according to a thirty-seventh aspect has the configuration of the semiconductor device according to the twenty-seventh aspect, further comprising a second potential connected to the first internal node, wherein the potential of the input terminal is higher than the ground potential. And positive surge suppression means for reducing the potential of the first internal node to the second potential or lower when the condition becomes

A semiconductor memory device according to a thirty-eighth aspect has the configuration of the semiconductor device according to the thirty-seventh aspect, further comprising a second potential connected to the second internal node, wherein the potential of the input terminal is higher than the ground potential. And a positive surge countermeasure for reducing the potential of the second internal node to the second potential or less when the condition becomes

[0069]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

[First Embodiment] FIG. 1 is a schematic block diagram showing a configuration of a semiconductor device 1 according to a first embodiment of the present invention. This overall configuration is a representative example that can be applied to all the embodiments described below.

Referring to FIG. 1, semiconductor device 1 has control signal input terminals 2 to 6 and address signal input terminal group 8
, A data signal input / output terminal group 16, a ground terminal 18, and a power supply terminal 20.

The semiconductor device 1 has input buffers 10 to 14, a clock generation circuit 22, a row and column address buffer 24, a row decoder 26, a column decoder 28, a memory mat 32, and a data input buffer. 40
And a data output buffer 42. The memory mat 32 includes a memory cell array 34 and a sense amplifier + input / output control circuit 38.

Clock generation circuit 22 has an external row address strobe signal Ext. Ext. Provided externally through control signal input terminals 2 and 4 and input buffers 10 and 12. /
RAS and external column address strobe signal Ext. / CA
A control clock corresponding to a predetermined operation mode based on S is generated to control the operation of the entire semiconductor device.

The row and column address buffer 24 includes externally applied address signals A0 to Ai (i is a natural number)
Is applied to a row decoder 26 and a column decoder 28.

The memory cells in the memory cell array 34 specified by the row decoder 26 and the column decoder 28
Data is exchanged with the outside through the data signal input / output terminal group 16 via the sense amplifier + input / output control circuit 38 and the data input buffer 40 or the data output buffer 42. The power supply circuit 50 has an external power supply potential Ext. Receiving Vcc and ground potential Vss, it supplies various internal power supply potentials necessary for the operation of the semiconductor device.

That is, the power supply circuit 50 supplies the external power supply potential Ext. Vcc and ground potential Vss, boosted power supply circuit 58 for generating internal boosted potential Vpp, and substrate potential Vpp.
VBB generating circuit 56 for generating BB, and internal power supply potential V
cc generating step-down power supply circuit 54 and internal power supply potential Vc
c, and generates a precharge potential VBL.

The present invention relates to an input buffer for receiving a signal from the outside, and has been described with reference to the block diagram of a semiconductor memory device as an example in FIG. It is not limited to.

FIG. 2 is a block diagram for describing a configuration of input buffer 10 in FIG.

The input buffer 10 is provided to a terminal 62 for receiving a signal from the outside, an undershoot countermeasure element 64 for receiving the signal input to the terminal 62 to absorb the undershoot and to output the undershoot to the node N1, and to the node N1. And an inverter 68 receiving and inverting the signal to output an output signal IOUT to the internal block.

Although an inverter has been described here, another type of input buffer such as a reference voltage comparison type input buffer may be used.

The input buffer 10 further includes a node N1
And a positive surge countermeasure element 66 for absorbing a positive surge of the signal applied to the power supply.

FIG. 3 shows the structure of the positive surge suppression element 6 in FIG.
FIG. 6 is a circuit diagram showing an example of the sixth embodiment. Positive surge suppression element 66
Includes a junction diode 70 having an anode connected to node N1 and a cathode connected to internal power supply potential Vcc. The positive surge suppression element 66 is not limited to the junction diode as shown in FIG. 3, and may have any configuration as long as it has a similar function.

FIG. 4 is a circuit diagram showing a configuration of undershoot preventing element 64 in FIG.

Referring to FIG. 4, undershoot countermeasure element 64 includes a resistor 72 connected between input node EN and node N1, and a source (N channel in a normal use state when undershoot does not enter). Of the two sources and drains of the transistor,
The drain (drain) and the gate are coupled to the ground potential and the drain (during normal use when no undershoot occurs, N
The source / drain with the higher potential of the two sources / drains in the channel transistor is connected to the node N1
Connected to the substrate portion and the substrate potential VBB is coupled to the substrate portion.
And a channel transistor 74.

When a negative potential undershoot is input to the drain of the N-channel transistor 74, the source / drain portion connected to the node N1 becomes a source and the N-channel transistor operates. However, in this specification, the terms “source” and “drain” will be used in relation to normal operation for simplicity. The same applies to the P-channel transistor.

The resistor 72 is formed by a polysilicon resistor or p⁺
Diffusion resistance may be used. That is, n⁺region
Any resistor that does not have a resistor may be used. Where p
⁺When a diffused resistor is used, the power supply voltage
-Considering the bar shoot, p ⁺N where diffusion resistance is formed
The well potential must be raised to the internal power supply potential Vcc or higher.
It is necessary.

The drain of N-channel transistor 74 connected to node N1 is an n ⁺ region to which an input signal is applied first, and is formed on a P substrate.

FIG. 5 is a plan view of an N-channel transistor 74a showing a structure of a first example of the N-channel transistor 74 in FIG.

Referring to FIG. 5, an N-channel transistor 74a includes a LOCOS (local oxidation of silicon)
The element is isolated from other elements on the semiconductor substrate by a normal element isolation region 82 such as a shallow trench. Gate electrode 84
Is n ⁺ region 90 sandwiched corresponding to the node N1 of FIG.

An n ⁺ region 88 is formed outside gate electrode 84, and a trench portion 86 is formed adjacent to a side of n ⁺ region 88 opposite to a side of gate electrode 84 in contact.

The trench 86 is usually formed deeper than the bottom of the element isolation region 82. FIG. 6 is a cross-sectional view of FIG.
It is sectional drawing which shows the structure of the cross section of A '.

Referring to FIG. 6, in the semiconductor device according to the first embodiment, a P well 122 is formed on a P type silicon substrate 120, and an N channel transistor 74a is formed thereon. An n ⁺ region 90 corresponding to node N1 in FIG. 4 is formed in a region sandwiched between gate electrodes 84, and an n ⁺ region 88 serving as a source of N-channel transistor 74a is formed outside gate electrode 84. . n ⁺ region 8
8 and gate electrode 84 are coupled to ground potential.

[0093] The outside of the N-channel transistor 74a is formed trench portion, along the n ⁺ region 88 n ⁺
A mold polysilicon 104 is deposited on the sidewalls of the trench. An insulating film 102 is formed on the polysilicon 104.

Transistor 74a is normally connected to node N1
Is non-conducting when the potential is positive. Then, the non-conductive state is maintained until the potential of the node N1 exceeds the reverse breakdown voltage of the PN junction at the boundary between the n ⁺ region 90 and the P well 122.

The reverse breakdown voltage is usually 8 V or more and 5 V
There is no problem with the operation of related devices. In addition, since a power supply potential suitable for device design rules is used, there is no problem even if the reverse breakdown voltage is not considered in the normally used voltage range of each device.

Next, steps for forming the structure shown in FIG. 6 will be described. 7 to 13 are cross-sectional views showing each step of forming the structure of FIG.

The following description is for the case where a trench isolation structure is provided. First, referring to FIG. 7, the silicon oxide film (SiO ₂₎ of 300Å thickness of about by CVD 1
After depositing (or forming by thermal oxidation) 34 and forming an underlying oxide film, a resist is applied and a resist mask 132 is formed by a lithography process. Then, the silicon substrate is etched by anisotropic etching to form element isolation trench portions.

Referring to FIG. 8, a new resist is applied (here, resist mask 132 may be removed once and a new resist mask may be formed). Then, a resist mask 136 is formed by a lithography process. An undershoot preventing element trench 135 is formed by anisotropic etching.

Referring to FIG. 9, after removing resist mask 136, a silicon oxide film 140 is formed on the entire surface to a thickness of about 1000 ° by a CVD method. A resist mask 138 is formed in a portion where the silicon oxide film 140 remains.

Thereafter, silicon oxide film 140 is partially removed by hydrofluoric acid (HF) treatment.

Next, the process proceeds to an LDD transistor forming step. Referring to FIG. 10, an n ⁺ polysilicon (or polycide) film for gate electrode 84 is formed, and sidewalls 142 are further formed. In this side wall forming step, the protruding portion of the silicon oxide film 140 on the bottom surface of the trench portion disappears (however, it may be left).

Referring to FIG. 11, n⁺Forming an area
The on-injection will be described. Injection angle θ = about 5 ° to 10 °
At an acceleration voltage of 50 keV and a dose of 10¹³-10¹⁴/
cm ^TwoArsenic (As) is implanted under the conditions of⁺Region 90,
88 is the source / drain region of the N-channel transistor
And formed on the side and bottom of the trench (oblique ion
Injection).

Referring to FIG. 12, the transistor portion is
Silicon oxide film 1 having a thickness of about 1000 ° by VD method
48, with the side walls and bottom of the trench exposed
And n ⁺The polysilicon film 104 is formed by CVD
It is formed with a thickness of about Å.

Thereafter, a resist mask 152 is formed in the trench portion and in the transistor region sandwiched between the trench portions.

Then, a part of the n ⁺ polysilicon film 104 is removed by hydrofluoric acid (HF, HNO ₃ ) treatment.

Referring to FIG. 13, resist mask 154 is provided.
Is formed, and a part of the n ⁺ polysilicon film 104 is removed by anisotropic etching.

Further, the resist mask 154 is removed, a silicon oxide film is deposited, and the trench is filled.

Thereafter, an undershoot countermeasure element is connected to a predetermined node by an interlayer insulating film forming step, a contact hole step, and a metal wiring step.

Although the above description has been made with reference to the transistor having the LDD structure, a single drain transistor may be used.
Other MIS (metal-insulator-semiconductor
) A transistor having a structure may be used.

The above is the description of n-channel transistor n⁺Seo
Source / drain formation process and undershoot prevention element
N of the trench part⁺Explanation on the method of forming the region at the same time
However, the performance of other N-channel transistors is
If there is a change in sex, use a normal N-channel transistor
Of source / drain and undershoot countermeasure element ⁺
It is preferable that the region forming step be a separate step.

In this case, the normal N-channel transistor region is covered with a resist mask, and the transistor of the undershoot countermeasure element and the n ⁺ region of the trench portion are formed in the oblique ion implantation step.

After that, a resist mask is formed, and an opening is formed only in a normal N-channel transistor portion.
An n ⁺ region for a drain is formed.

In this way, the undershoot countermeasure element and the normal N-channel transistor can be formed independently under optimum conditions.

The above has described the process of manufacturing an undershoot countermeasure element having a trench isolation structure.
It is also possible to form a trench with an isolation structure.

FIGS. 14 to 15 are cross-sectional views showing steps of forming a trench portion in the LOCOS isolation structure.

Referring to FIG. 14, a silicon nitride film (Si
₃ N ₄₎ 162 as a mask after forming field oxide film 164 by wet oxidation, a resist mask 166 for the trench opening of undershoot protection device.

Referring to FIG. 15, field oxide film 164 and the silicon substrate are etched by anisotropic etching to form a trench portion. After that, FIGS.
Since the process is the same as that of No. 3, the description will not be repeated.

As described above, the undershoot prevention element is set to L
It can be formed using an OCOS separation structure.

Referring again to FIGS. 4 and 6, the threshold value of transistor 74a is set to, for example, 1V. When a potential of -1 V or less is applied to the node N1, the transistor 74a
There becomes conductive, the ground potential V from the outside of the n ⁺ region 88
Electrons escape to ss.

Normally, a substrate potential VBB is applied to a P-type silicon substrate.
Is applied. For example, VBB is set to -1.5V.

Here, undershoot of -1.5 V or less
Is applied to the node N1 with a pulse width tp,
During the period tp when the transistor 74a is conductive, the node N1
N ⁺At the PN junction at the boundary between the region 90 and the P well 122
When a forward voltage is applied, electrons flow through the P-well 122 and the P-type
It will be implanted into the silicon substrate 120.

Here, the electron injection aperture angle at which electrons are injected from n ⁺ region 90 toward P well 122 and P type silicon substrate 120 will be considered. _{DT in} FIG. 6 is the trench depth. d _n is the junction depth. L is node N
1 is the distance from the end of the n ⁺ region 90 to the trench sidewall. At this time, the electron injection aperture angle α in the AA ′ direction is represented by the following equation.

Α = π / 2−tan ⁻¹ (d _T / (L−d _n )) (3) The injected electrons are those having an aperture angle α or less in the x direction of FIG. Since it can be captured on the side wall, the undershoot resistance is improved.

However, n ⁺ region 88 is formed in trench portion 86
Of the semiconductor substrate from the main surface of the semiconductor substrate to the bottom of the trench portion 86, the depth of the semiconductor substrate does not exceed the depth indicated by the broken line in the n ⁺ region 88 of FIG. The presence of the trench sidewall has the effect of narrowing the electron injection aperture angle.

At the time when electrons are injected, a channel is formed in the N-channel transistor 74a. As a potential having a large absolute value is applied to the node N1 in the negative direction, the electric field between the n ⁺ region 90 and the trench side wall n ⁺ region 88 increases, and a considerable number of electrons are directed to the side wall. The undershoot resistance is improved.

However, in the y direction, the electron injection aperture angle β is the same as that of the conventional example shown in FIG. 140, but the injection amount is reduced by the amount of the electric field on the side wall. improves.

Further, since the resistance 72 makes it difficult for the current to flow, it functions to alleviate the negative pulse of a sudden undershoot.

That is, N-channel transistor 74a
There is an action of extending the time from the conduction state of the PN junction to the forward direction of the PN junction and an action of decreasing the absolute value of the potential of the negative pulse.

Therefore, the resistance to undershoot is improved by providing resistor 72 in front of node N1.

Further, since the resistor 72 is provided, it is not necessary to increase the area of the node N1 in consideration of the heat generated by the current. 6 if the area of the node N1 can be reduced.
(Distance from the end of the n ⁺ region of the node N1 to the side wall of the trench) can be reduced, so that the electron injection aperture angle can be reduced. Therefore, the undershoot resistance is improved as compared with the case where the resistor 72 is not provided.

[Second Embodiment] In a semiconductor device of a second embodiment, the structure of an N-channel transistor in an undershoot countermeasure element is a structure shown by an N-channel transistor 74b described below. By further reducing the electron injection aperture angle in the x direction as compared with the first embodiment,
Undershoot resistance can be improved.

FIG. 16 is a plan view of an N-channel transistor 74b in the semiconductor device of the second embodiment.

The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the structure of the N-channel transistor 74 of the undershoot countermeasure element shown in FIG. 4 is the structure shown by the N-channel transistor 74b.

Referring to FIG. 16, an N-channel transistor 74b is isolated from other elements on a semiconductor substrate in a normal element isolation region 82 such as a LOCOS or a shallow trench. N ⁺ region 90 interposed between gate electrodes 84 corresponds to node N1.

An n ⁺ region 172 is provided outside gate electrode 84.
Is formed, and trench portion 94 is formed adjacent to the side of n ⁺ region 172 opposite to the side in contact with gate electrode 84.

The trench portion 94 is usually formed deeper than the bottom of the element isolation region 82. FIG. 17 is a sectional view showing an AA 'section in FIG.

Referring to FIG. 17, a semiconductor device according to the second embodiment has a P-well 122
Is formed, and trench portion 94 is formed outside N-channel transistor 74b. The trench 94 has an inversely tapered side wall.

N channel transistor 74b has n ⁺ region 9 corresponding to node N1 interposed between gate electrodes 84.
0 is formed, and an n ⁺ region 172 serving as the source of the N-channel transistor 74b is formed outside the gate electrode 84 along the side wall of the reverse tapered trench portion 94. n in line with the n ⁺ region 172 ⁺ polysilicon 17
4 is deposited on the trench side wall, and an insulating film 176 is formed thereon.
Has been deposited.

FIGS. 18 to 24 are sectional views showing steps of forming the structure shown in FIG. Hereinafter, a description will be given of forming the structure of FIG. 17 with a trench isolation structure.

Referring to FIG. 18, 300
After depositing (or forming by thermal oxidation) a silicon oxide film having a thickness of about Å and forming an underlying oxide film 134,
A resist is applied and a resist mask 136 is formed by a lithography process.

In order to form a reverse tapered shape, anisotropic etching is performed by setting the implantation angle of the etching ions to θ ′ (for example, 20 °).

In order to make the implantation angle of the etching ions θ ′, the wafer is tilted by θ ′ and set in the anisotropic etching apparatus, and the wafer fixing table is rotated. With this method, the implantation angle of the etching ions can be set to θ ′.

Referring to FIG. 19, a resist mask 1 covering side walls and bottom surfaces of the element forming portion and the trench portion with resist.
82 is formed.

After that, the silicon substrate is etched by anisotropic etching to form an element isolation trench portion, and then the resist mask 182 is removed.

Referring to FIG. 20, a silicon oxide film 184 is formed on the entire surface to a thickness of about 1000 ° by the CVD method. After that, a resist mask 186 is formed in a portion where the silicon oxide film 184 remains, and a part of the silicon oxide film is removed by hydrofluoric acid (HF) treatment.

Next, the process proceeds to an LDD transistor forming step.
Referring to FIG. 21, an n ⁺ polysilicon (or polycide) film of gate electrode 84 is formed, and sidewalls 142 are further formed.

Referring to FIG. 22, ion implantation for forming an n ⁺ region is next performed. Injection angle from 5 ° to reverse taper angle γ
At an angle θ of about 10 °, arsenic (As) is implanted under the conditions of an acceleration voltage of 50 keV, a dose of 10 ¹³ to 10 ¹⁴ / cm ² , and a source / drain region of an N-channel transistor and one side of a trench and a bottom. The n ⁺ regions 110 and 172 are formed in portions (openings of silicon oxide film) (oblique ion implantation).

Referring to FIG. 23, a region where transistor 74b is to be formed is covered with a silicon oxide film 188 having a thickness of about 1000 ° by a CVD method, and n ⁺ Polysilicon film 1
74 is formed to a thickness of about 2000 ° by the CVD method.

Thereafter, a resist mask 1 is formed in a trench portion where a transistor is to be formed and in a region sandwiched between the trench portions.
90 are formed.

Next, a part of the n ⁺ polysilicon film 174 is removed by hydrofluoric acid (HF, HNO ₃ ) treatment.

Referring to FIG. 24, a resist mask 192 is formed.
Is formed, and a part of n ⁺ polysilicon film 174 is further removed by anisotropic etching. Then, the resist mask 192 is removed, a silicon oxide film is deposited, and the trench is filled.

Thereafter, an undershoot countermeasure element is connected to a predetermined node by an interlayer insulating film forming step, a contact hole step, and a metal wiring step.

Although the above description has been made with reference to the transistor having the LDD structure, a single drain transistor may be used.
In addition, other MIS (metal-insulator-semiconducto
r) A transistor having a structure may be used.

The above is the description of n-channel transistor n⁺Seo
Source / drain formation process and undershoot prevention element
N of the trench part⁺Explanation on the method of forming the region at the same time
However, the performance of other N-channel transistors is
If there is a change in sex, use a normal N-channel transistor
Of source / drain and undershoot countermeasure element ⁺
It is preferable that the region forming step be a separate step.

In this case, the normal N-channel transistor region is covered with a resist mask, and the transistor of the undershoot countermeasure element and the n ⁺ region of the trench portion are formed in the oblique ion implantation step.

Thereafter, a resist mask is formed, and an opening is formed only in a normal N-channel transistor portion.
An n ⁺ region for a drain is formed.

By doing so, the undershoot countermeasure element and the normal N-channel transistor can be formed independently under optimum conditions.

Referring to FIG. 17 again, the case of the second embodiment
Consider the electron injection aperture angle in this case. In FIG.
L_AThe reverse tapered side wall of the trench portion 94 is
The bite distance into the lower part of transistor 74b
You. d_TIs the trench depth, d _nIs the junction depth, L is the node
N of N1⁺At the distance from the end of region 90 to the trench sidewalls
is there.

At this time, the electron injection aperture angle α in the x direction is represented by the following equation. ^{α = π / 2-tan -1} (d T / (L-L A -d n)) ... (4) The semiconductor device of the second embodiment, as compared to the semiconductor device of the first embodiment, the input signal N ⁺ region 90 applied first
, The electron injection aperture angle in the x-direction toward the P-type silicon substrate 120 can be reduced, so that the undershoot resistance is further improved.

[Embodiment 3] The semiconductor device of the embodiment 3 is different from the semiconductor devices of the embodiments 1 and 2 in that
It has a structure in which the electron injection aperture angle in the y direction in the n ⁺ region to which a signal is applied first is reduced.

In the semiconductor device of the third embodiment, the structure of the N-channel transistor in the undershoot countermeasure element is the structure shown by N-channel transistor 74c described below.

FIG. 25 is a plan view of an N-channel transistor 74c in the semiconductor device of the third embodiment.

The semiconductor device of the third embodiment differs from the semiconductor device of the first embodiment in that the structure of the N-channel transistor 74 of the undershoot countermeasure element shown in FIG. 4 is the structure shown by the N-channel transistor 74c.

Referring to FIG. 25, N-channel transistor
The element 74c is usually formed on the semiconductor substrate in the element isolation region 210.
It is separated from other elements. Surrounded by the gate electrode 206
N ⁺The area 202 corresponds to the node N1 in FIG.
You.

[0165] The gate electrode 206 has a ring shape, its outer periphery 3 n ⁺ region 204 in line with the direction are formed adjacently along the outer peripheral three directions of the n ⁺ region 204 trench portion 208 are formed.

[0166] There are n ⁺ regions outside three directions of the n ⁺ region 202 corresponding to the node N1, since the trench sidewalls is also outside the three directions, it is possible to reduce the y-direction electron injection aperture angle in the direction of the trench sidewalls.

FIG. 26 is a sectional view showing the structure of the section taken along line AA 'of FIG. Since this structure can be formed in a step similar to that described in the first embodiment, description thereof will not be repeated.

Referring to FIG. 26, a semiconductor device according to the third embodiment has a P-well 122
Is formed thereon, and the N-channel transistor 7 of FIG.
4c is formed. An n ⁺ region 202 corresponding to node N1 in FIG. 4 is formed in a region sandwiched between gate electrodes 206, and an n ⁺ region 204 that is a source of N-channel transistor 74c is formed outside gate electrode 206. . N ⁺ region 204 and gate electrode 206 are coupled to ground potential.

A trench 208 is formed outside N-channel transistor 74c, and n ⁺ type polysilicon 104 is deposited on the side wall of the trench along the n ⁺ region 204. An insulating film 102 is formed on the polysilicon 104.
Is formed.

The electron injection aperture angle α in this case is equal to that in the first embodiment, and is expressed by the following equation (3).

As described above, the semiconductor device of the third embodiment has a trench side wall on one side in the y direction as compared with the semiconductor device of the first embodiment, so that the electron injection aperture angle in the y direction can be reduced. Undershoot resistance is further improved.

[First Modification of Third Embodiment] FIG. 27 is a plan view showing a planar structure of an N-channel transistor 74d according to a first modification of the third embodiment.

The semiconductor device according to the first modification of the third embodiment has the following structure.
4 has a planar structure surrounding three sides of N-channel transistor 74 in FIG.
The semiconductor device of the third embodiment is different from the semiconductor device of the third embodiment in that an N-channel transistor 74d having a reverse tapered shape as shown in FIG.

[0174] With reference to FIG. 27, N-channel transistor 74d in the first modification of the third embodiment, in the N-channel transistor 74c of the third embodiment shown in FIG. 25, n ⁺ region 204, the trench 208 Instead, each has an n ⁺ region 212 and a trench portion 214.

FIG. 28 is a sectional view showing the structure of the section taken along line AA 'of FIG. Since this structure can be formed by a process similar to that described in Embodiment 2, description thereof will not be repeated.

Referring to FIG. 28, in the semiconductor device according to the first modification of the third embodiment, a P well 122 is formed on a P type silicon substrate 120, and an N channel transistor 74d is formed.
Is formed outside the trench. The side wall of the trench 214 has an inverted tapered shape.

The gate of the N-channel transistor 74d is
N corresponding to the node N1 sandwiched between the⁺region
202 is formed, and a reverse text is formed outside the gate electrode 206.
N-channel transistor along the sidewall of the tapered trench
N which is the source of the star 74d ⁺The area 212 is formed
I have. n⁺N along the region 212⁺Type polysilicon 1
74 is deposited on the side wall of the trench, and an insulating film 17 is
6 have been deposited.

The semiconductor device of the first modification of the third embodiment also has
The electron injection aperture angle α in the x-direction is expressed by equation (4) as in the second embodiment. The semiconductor device according to the first modification of the third embodiment has a structure in which three directions of a transistor are surrounded by a trench region as compared with the semiconductor device according to the second embodiment.
Since the opening angle of the electron injection in the y direction in the direction in which the trench side wall exists can be reduced as in the x direction, the undershoot resistance is further improved.

[Embodiment 4] FIG. 29 shows Embodiment 4 of the present invention.
30 is a plan view of an N-channel transistor 74e in the semiconductor device of FIG.

The semiconductor device of the fourth embodiment differs from the semiconductor device of the first embodiment in that the structure of N-channel transistor 74 in FIG. 4 is the structure shown by N-channel transistor 74e.

Referring to FIG. 29, N channel transistor
The head 74e is surrounded by trench portions 226 in four directions.
And the outside thereof is usually surrounded by an element isolation region 216.
Have been. In the center of FIG.
Is formed, and a region surrounded by the gate electrodes 220 on both sides thereof
Is the drain n of the N-channel transistor 74e. ⁺
A region 218 is formed. Gate electrode 220 and tray
The region sandwiched between the punch portions 226 is an N-channel transistor
N which is the source of 74e⁺An area 224. Normal element
In the portion where the separation area 122 and the gate electrode 220 overlap.
Electrically connects the gate electrode and a wiring layer (not shown)
A contact is provided.

FIG. 30 is a sectional view showing the structure of the section taken along line BB 'of FIG. Embodiment 4 Referring to FIG.
In this semiconductor device, a P-well 122 is formed on a P-type silicon substrate 120, and an N-channel transistor 74e in FIG. 4 is formed thereon. The n ⁺ region 21 corresponding to the node N1 in FIG.
8 are formed, and an n ⁺ region 224 that is the source of the N-channel transistor 74e is formed outside the gate electrode 220. N ⁺ region 224 and gate electrode 220
Is coupled to ground potential.

A trench portion 226 is formed outside N channel transistor 74e, and n ⁺ type polysilicon 104 is deposited on the side wall of the trench portion along n ⁺ region 224. An insulating film 102 is formed on the polysilicon 104.
Is formed.

FIG. 30 shows the electron injection aperture angle when the electron injection aperture angle is determined on the trench side wall far from the n ⁺ region 218 without the electron colliding with the central element isolation region 222. Is shown.

Here, m is the n ⁺ region 218 of the node N1.
From the end of the trench to the farthest trench sidewall. Further, the d _T trench depth, is d _n is a junction depth. At this time, the electron injection aperture angle β in the y direction (BB ′ direction) is represented by the following equation.

Β = π / 2−tan ⁻¹ (d _T / (m−d _n )) (5) In the semiconductor device of the fourth embodiment, one of the electron injection aperture angles in the y direction is given by the following equation (2). From the value of (5) to the value of the expression (5).

FIG. 31 is a sectional view showing a section taken along the line AA 'in FIG. Referring to FIG. 31, in the semiconductor device of the fourth embodiment, P well 122 is formed on P type silicon substrate 120, and trench portion 226 is formed outside N channel transistor 74e. In the N-channel transistor 74e, an n ⁺ region 218 corresponding to the node N1 sandwiched between the gate electrodes 220 is formed, and outside the gate electrode 220 is the source of the N-channel transistor 74e along the side wall of the trench portion 226. An n ⁺ region 224 is formed. n along the n ⁺ region 224
⁺ -Type polysilicon 104 is deposited on the sidewalls of the trench,
An insulating film 102 is deposited thereon.

From FIG. 31, the electron injection aperture angle in the x direction and the electron injection aperture angle in the other direction (to the trench sidewall on the near side) in the embodiment 4 are α, and are expressed by equation (3). .

As described above, in the fourth embodiment, the four directions of the transistor 74e are surrounded by the trench sidewalls, so that the undershoot resistance can be further improved as compared with the third embodiment.

[Fifth Embodiment] In the semiconductor device of the fifth embodiment, the structure of an N-channel transistor in an undershoot countermeasure element is a structure shown by an N-channel transistor 74f described below.

FIG. 32 is a plan view of an N-channel transistor 74f in the semiconductor device of the fifth embodiment.

Referring to FIG. 32, N-channel transistor 74f is surrounded by trench portions 230 in four directions, and is further surrounded by element isolation regions 216. A normal element isolation region 222 is formed in the center of FIG. 32, and an n ⁺ region 218 serving as a drain of the N-channel transistor 74f is formed in a region surrounded by the gate electrodes 220 on both sides thereof. The region sandwiched between the gate electrode 220 and the trench 230 is an N-channel transistor 7
4f is the n ⁺ region 228 that is the source.

FIG. 33 is a cross sectional view showing the BB 'cross section of N-channel transistor 74f in FIG.

Referring to FIG. 33, the semiconductor device of the fifth embodiment has a structure in which a P well 122
Is formed, and trench portion 230 is formed outside N-channel transistor 74f. This trench portion 23
Numeral 0 indicates that the side wall has an inverted tapered shape.

The N-channel transistor 74f has a gate
Corresponding to the node N1 sandwiched between the gate electrodes 220⁺region
218 is formed, and a reverse text is formed outside the gate electrode 220.
N-channel transistor along the sidewall of the tapered trench
N which is the source of the star 74f ⁺The region 228 is formed
I have. n⁺N along the region 228⁺Type polysilicon 1
74 is deposited on the side wall of the trench, and an insulating film 17 is
6 have been deposited.

[0196] In Figure 33, the implanted without the n ⁺ region that electrons collide with the element isolation region 222 of the central portion 218
The case where the electron injection aperture angle is determined on the trench side wall that is farther from the viewer is shown. At this time, the electron injection aperture angle β is expressed by the following equation.

[0197] ^{β = π / 2-tan -1} (d T / (m-L A -d n)) ... (6) In the semiconductor device of the fifth embodiment, while an electron injection aperture angle in the y direction ( 6) will be narrowed down to the value of equation.

FIG. 34 is a sectional view showing an AA 'section in FIG. Referring to FIG. 34, in the semiconductor device of the fifth embodiment, P well 122 is formed on P type silicon substrate 120, and trench portion 230 is formed outside N channel transistor 74f. The trench 230 has an inversely tapered side wall.

The gate of the N-channel transistor 74f is
Corresponding to the node N1 sandwiched between the gate electrodes 220⁺region
218 is formed, and a reverse text is formed outside the gate electrode 220.
N-channel transistor along the sidewall of the tapered trench
N which is the source of the star 74f ⁺The region 228 is formed
I have. n⁺N along the region 228⁺Type polysilicon 1
74 is deposited on the side wall of the trench, and an insulating film 17 is
6 have been deposited.

In this case, the electron injection aperture angle α in the x direction is represented by the following equation (4). In the semiconductor device of the fifth embodiment, the four directions of N-channel transistor 74f are surrounded by trench side walls, and the electron injection aperture angles α and β can be reduced in both the x direction and the y direction. Undershoot resistance can be improved.

[Sixth Embodiment] In the semiconductor device of the sixth embodiment, the structure of the N-channel transistor in the undershoot countermeasure element is the structure shown by an N-channel transistor 74g described below.

FIG. 35 is a plan view of an N-channel transistor 74g in the semiconductor device of the sixth embodiment.

Referring to FIG. 35, the structure of the N-channel transistor 74g in the sixth embodiment is different from that of the fourth embodiment in that a normal element isolation region 238 further includes a trench portion 242. 7
4e.

The central element isolation region 238 may be completely replaced with a trench.

FIG. 36 is a sectional view showing a section taken along line BB 'in FIG. Referring to FIG. 36, in the semiconductor device of the sixth embodiment, P well 122 is formed on P type silicon substrate 120, and trench portion 244 is formed outside N channel transistor 74g.

An N ⁺ region 234 corresponding to node N 1 sandwiched between gate electrodes 236 is formed in N channel transistor 74 g, and N channel transistor 7 is formed outside gate electrode 236 along the side wall of trench portion 244.
An n ⁺ region 240 as a 4 g source is formed.
An n ⁺ type polysilicon 104 is deposited on the trench side wall along the n ⁺ region 240, and is deposited on the insulating film 102 thereon.

The n ⁺ region 234 has the element isolation region 2 at the center.
38, a trench portion 242 is formed at the center of the element isolation region 238.

In this case, the electron injection aperture angle in the y direction (BB ′ direction) is beyond the central trench 242 because electrons injected into the n ⁺ region 234 are blocked by the central trench 242. It is not determined by the n ⁺ region 240 on the trench sidewall portion on the far side. In this case, the electron injection aperture angle is the wider one of the aperture angles determined by the n ⁺ region 240 on the trench side wall portion closer to the aperture angle determined by the central trench portion 242.

Here, by adjusting the size of n ⁺ region 234 and the size of element isolation region 238, the opening angle can be easily determined by n ⁺ region 240 on the side wall of the trench that is closer. . In that case, y
The electron injection aperture angle in the direction is expressed by the same equation (3) as the electron injection aperture angle in the x direction.

FIG. 37 is a sectional view showing an AA 'section of FIG. Referring to FIG. 37, the semiconductor device of the sixth embodiment has a structure in which a P well 122
Is formed, and trench portion 244 is formed outside N-channel transistor 74g.

N ⁺ region 234 corresponding to node N 1 sandwiched between gate electrodes 236 is formed in N channel transistor 74 g, and N channel transistor 7 is formed outside gate electrode 236 along the side wall of trench portion 244.
An n ⁺ region 240 as a 4 g source is formed.
An n ⁺ type polysilicon 104 is deposited on the trench side wall along the n ⁺ region 240, and an insulating film 102 is deposited thereon.

As shown in FIG. 37, the electron injection aperture angle in the x direction is expressed by equation (3). As described above, the electron injection aperture angle in the y direction is the same as the electron injection aperture angle in the x direction. Therefore, it is expressed by equation (3).

In the semiconductor device of the sixth embodiment, the electron injection aperture angle in the y direction of the N-channel transistor 74g of the undershoot prevention element portion can be made smaller than that of the fourth embodiment. Further, undershoot resistance can be improved.

[First Modification of Sixth Embodiment] FIG. 38 is a plan view of an N-channel transistor 74h in a semiconductor device of a first modification of the sixth embodiment.

Referring to FIG. 38, an N-channel transistor 74h according to a first modification of the sixth embodiment has trench portions 246 and 246 instead of trench portions 242 and 244, respectively.
The difference from the N-channel transistor 74g of the sixth embodiment shown in FIG. The other parts are shown in FIG.
Are the same as in the case shown by, and the description will not be repeated.

FIG. 39 is a sectional view showing a section taken along line BB 'in FIG. Sixth Embodiment Referring to FIG.
In the semiconductor device of the first modification, the P well 122 is formed on the P-type silicon substrate 120, and the trench 250 is formed outside the N-channel transistor 74h.
The trench 250 has an inversely tapered side wall.

In N channel transistor 74h, n ⁺ region 234 corresponding to node N1 sandwiched between gate electrodes 236 is formed, and outside gate electrode 236, along the side wall of reverse tapered trench portion 250. An n ⁺ region 248 that is a source of the N-channel transistor 74h is formed.

An n ⁺ type polysilicon 174 is deposited on the trench side wall along the n ⁺ region 248, and an insulating film 176 is deposited thereon. The n ⁺ region 234 has a central portion divided by an element isolation region, and a trench portion 246 is further formed at the central portion. The trench 246 also has an inversely tapered side wall.

FIG. 40 is a sectional view showing an AA 'section in FIG. Referring to FIG. 40, in the semiconductor device of the first modification of the sixth embodiment, P well 122 is formed on P type silicon substrate 120, and trench portion 250 is formed outside N channel transistor 74h. . The trench 250 has an inversely tapered side wall.

In N-channel transistor 74h, n ⁺ region 234 corresponding to node N1 sandwiched between gate electrodes 236 is formed, and outside gate electrode 236, along the side wall of inversely tapered trench portion 250. An n ⁺ region 248 that is a source of the N-channel transistor 74h is formed. An n ⁺ type polysilicon 174 is deposited on the trench side wall along the n ⁺ region 248, and an insulating film 176 is deposited thereon.

At this time, the electron injection aperture angle is represented by α in equation (4) in both the x and y directions. The semiconductor device of the sixth embodiment can further reduce the undershoot resistance since the y-direction electron injection aperture angle in the N-channel transistor 74h of the undershoot prevention element portion can be further reduced as compared with the semiconductor device of the fifth embodiment. .

[Embodiment 7] FIG. 41 shows Embodiment 7 of the present invention.
FIG. 6 is a circuit diagram showing an undershoot countermeasure element in the semiconductor device of FIG.

The semiconductor device of the seventh embodiment differs from the semiconductor device of the first embodiment in having an undershoot preventing element shown in FIG. 41 instead of the undershoot preventing element shown in FIG.

This undershoot preventing element includes a resistor 72 connected between input node EN and node N1,
An N-channel transistor 252 having a source connected to node N1, a gate coupled to ground potential, a drain coupled to internal power supply potential Vcc, and a substrate portion coupled to substrate potential VBB. The resistor 72 may be a polysilicon resistor or a p ⁺ diffusion resistor. That is, any resistor may be used as long as it does not have an n ⁺ region on a P-type silicon substrate. However, when a p ⁺ diffusion resistor is used, considering that a waveform with an overshoot higher than the internal power supply potential Vcc is applied, the potential of the N well where the p ⁺ diffusion resistance is formed is set to be higher than the internal power supply potential Vcc. It needs to be raised.

The input signal is applied to the node N1 first.
N formed on a P-type silicon substrate ⁺Area.

In the seventh embodiment, N-channel transistor 252 is an N-channel transistor 252 described below.
It has the structure shown by a.

FIG. 42 shows an N-channel transistor 252.
It is a top view of a. 42 has the same structure as that of FIG. 5 in the first embodiment, and therefore description thereof will not be repeated.

FIG. 43 is a sectional view showing a section taken along AA 'in FIG. In n-channel transistor 252a shown in FIG. 43, n ⁺ region 88 has internal power supply potential Vcc.
Is different from that in the first embodiment in that depletion layer 256 is present. Other parts are the same as those in the first embodiment shown in FIG. 6, and therefore description thereof will not be repeated.

The thickness of depletion layer 256 extending from n ⁺ region 88 toward P well 122 is represented by W.

At this time, the electron injection aperture angle α in the x direction (AA ′ direction) is represented by the following equation. α = π / 2−tan ⁻¹ ((d _T + W) / (L−d _n −W)) (7) As described above, the case where the depletion layer 256 is expanded is the same as that of the first embodiment. In comparison with this, the electron injection aperture angle can be made smaller, so that the undershoot resistance is improved.

At the time when electrons are injected, a channel is formed in N-channel transistor 252a. However, compared to the case where ground potential is coupled to n ⁺ region 88 on the side wall of the trench, n ⁺ region The electric field existing between 90 and n ⁺ region 88 on the side wall of the trench is further increased. As described in the first embodiment, when a negative voltage exceeding the threshold value of N-channel transistor 252a is applied to node N1, transistor 252a is turned on, and electrons flow from node N1 to internal power supply potential Vcc. . The electric field at this time is larger than when the ground potential is coupled to n ⁺ region 88, and electrons flow immediately to the trench side wall, so that the PN between node N1 and the P well is reduced. It works so that joining is hard to be performed in the forward direction.

In this state, when a potential having a large absolute value is applied to the node N1 in the negative direction, the electric field further increases accordingly. Therefore, even if there are injected electrons, the majority of the injected electrons are absorbed by n ⁺ region 88 on the side wall of the trench, so that the undershoot resistance is improved.

Although the electron injection aperture angle β in the y direction is the same as that of the conventional example, the probability that electrons injected in the y direction also go to the side wall increases because the electric field to the side wall is further increased. Therefore, the undershoot resistance is improved.

Further, since the resistance 72 makes it difficult for the current to flow, it functions to alleviate a sudden undershoot negative pulse.

That is, N-channel transistor 252
There is an operation of extending the time from the conduction state a to the forward direction of the PN junction and an operation of reducing the absolute value of the potential of the negative pulse.

Therefore, the resistance to undershoot is improved by providing resistor 72 in front of node N1.

[Modification 1 of Embodiment 7] FIG.
It is a top view of channel transistor 252b.

44 is different from the transistor shown in the plan view of FIG. 42 in the seventh embodiment in that n ⁺ region 88 is replaced with n ⁺ region 172, and trench portion 94 is replaced with trench portion 86. Have. Since the other configuration is the same as that of FIG. 42, description thereof will not be repeated.

FIG. 45 is a sectional view showing a section taken along line AA 'in FIG. Referring to FIG. 45, a semiconductor device according to a first modification of the seventh embodiment has a P-type silicon
Above, a P-well 122 is formed, and a trench portion 94 is formed outside the N-channel transistor 252b. The trench 94 has an inversely tapered side wall.

In N-channel transistor 252b, an n ⁺ region 90 corresponding to node N1 sandwiched between gate electrodes 84 is formed, and outside gate electrode 84, along the side wall of reverse tapered trench portion 94. An n ⁺ region 172, which is the source of N channel transistor 252b, is formed. An n ⁺ type polysilicon 174 is deposited on the trench side wall along the n ⁺ region 172, and the insulating film 1 is formed thereon.
76 have been deposited.

Internal power supply potential Vcc is coupled to n ⁺ region 172. Therefore, depletion layer 258 extends from n ⁺ region 172 into P well 122. The thickness of this depletion layer is W.

At this time, the electron injection aperture angle α in the x direction (AA ′ direction) is represented by the following equation. ^{α = π / 2-tan -1} ((d T + W) / (L-L A -d n -W)) ... (8) as described above, and a depletion layer 258 spreads, and the trench sidewall portion Has an inversely tapered shape, so that the electron injection aperture angle can be further reduced as compared with the case of the seventh embodiment, and the undershoot resistance is improved.

[Eighth Embodiment] In the semiconductor device of the eighth embodiment, y is further increased than in the case of the semiconductor device of the seventh embodiment.
In this example, the structure of the N-channel transistor 252 in FIG. 41 is changed to an N-channel transistor 252c in order to reduce the directional electron injection aperture angle.

FIG. 46 is a plan view of an N-channel transistor 252c according to the eighth embodiment.

Since the plan view of FIG. 46 has the same structure as that of FIG. 25 in the third embodiment, description thereof will not be repeated.

FIG. 47 is a sectional view showing a section taken along AA 'in FIG. Referring to FIG. 47, in the semiconductor device of the eighth embodiment, P well 122 is formed on P type silicon substrate 120, and N channel transistor 252c is formed thereon. An n ⁺ region 202 corresponding to the node N1 is formed in a region sandwiched between the gate electrodes 206, and an n ⁺ region 204 that is a source of the N-channel transistor 252c is formed outside the gate electrode 206. N ⁺ region 204 is coupled to internal power supply potential Vcc. Gate electrode 206 is coupled to ground potential.

Outside N-channel transistor 252c
Is formed with a trench 208, and n ⁺Along area 204
So n⁺Type polysilicon 104 is on the side wall of the trench.
Deposited on An insulating film 10 is formed on the polysilicon 104.
2 are formed.

In this structure, n at which electrons are injected first
N ⁺ region 2 in the trench sidewall portion in three directions of ⁺ region 202
Since there is the hole 04, the electron injection opening angle in the y direction with the trench side wall can be further reduced as compared with the case of the seventh embodiment, and the undershoot resistance is further improved.

[Modification 1 of Embodiment 8] Embodiment 8
The semiconductor device of the first modification is an example in which the side wall of the trench portion of the eighth embodiment has an inverted tapered shape.

FIG. 48 is a plan view showing a planar structure of an N-channel transistor 252d according to a first modification of the eighth embodiment.

Referring to FIG. 48, an N-channel transistor 252d according to the first modification of the eighth embodiment has a structure similar to that of FIG.
In the N channel transistor 252c according to the eighth embodiment, the n ⁺ region 204 and the trench 208
Instead of n ⁺ region 212 and trench portion 214, respectively.
Having.

FIG. 49 is a sectional view showing the structure of the section taken along line AA 'of FIG. Embodiment 8 Referring to FIG.
In the semiconductor device of Modification 1, the P-well 122 is formed on the P-type silicon substrate 120, and the trench 214 is formed outside the N-channel transistor 252d. The side wall of the trench 214 has an inverted tapered shape.

The transistor 252d has a gate electrode 2
The n ⁺ region 202 corresponding to the node N1 sandwiched between the gate electrode 06 and the N channel transistor 25 is formed outside the gate electrode 206 along the side wall of the reverse tapered trench portion.
An n ⁺ region 212 as a 2d source is formed.
An n ⁺ type polysilicon 174 is deposited on the trench side wall along the n ⁺ region 212, and an insulating film 176 is deposited thereon.

N ⁺ region 212 is coupled to internal power supply potential Vcc, and gate electrode 206 is coupled to ground potential.

As described above, the semiconductor device of the first modification of the eighth embodiment differs from the semiconductor device of the eighth embodiment in that the trench portion surrounding the n ⁺ region of node N1 into which electrons are injected is provided. Has a reverse tapered shape, the electron injection aperture angle can be further reduced as compared with the case of the semiconductor device of the eighth embodiment, so that the undershoot resistance is further improved.

[Ninth Embodiment] In the semiconductor device of the ninth embodiment, the value of y is further increased than in the case of the semiconductor device of the eighth embodiment.
In this example, the structure of the N-channel transistor 252 in FIG. 41 is changed to an N-channel transistor 252e in order to reduce the directional electron injection aperture angle.

FIG. 50 is a plan view of an N-channel transistor 252e in the semiconductor device of the ninth embodiment.

Since the plan view of FIG. 50 has a structure similar to that of FIG. 29 in the fourth embodiment, description thereof will not be repeated.

FIG. 51 is a sectional view showing the structure of the section taken along line BB 'of FIG. Ninth Embodiment Referring to FIG.
In the semiconductor device, a P-well 122 is formed on a P-type silicon substrate 120, and an N-channel transistor 2
52e are formed. An n ⁺ region 218 corresponding to the node N1 is formed in a region sandwiched between the gate electrodes 220, and an n ⁺ region 224 serving as a source of the N-channel transistor 252e is formed outside the gate electrode 220. N ⁺ region 224 is coupled to internal power supply potential Vcc. Gate electrode 220 is coupled to ground potential.

Outside N-channel transistor 252e
Is formed with a trench portion 226, and n ⁺Along area 224
So n⁺Type polysilicon 104 is on the side wall of the trench.
Deposited on An insulating film 10 is formed on the polysilicon 104.
2 are deposited.

A reverse bias is applied to the PN junction at the boundary between the n ⁺ region 224 and the P well 122, and the depletion layer 264 extends in the P well with the thickness W.

At this time, the electron injection aperture angle β is as follows. β = π / 2−tan ⁻¹ ((d _T + W) / (m−d _n −W)) (9) FIG. 52 is a cross-sectional view showing a cross section taken along the line AA ′ in FIG.

Referring to FIG. 52, in the semiconductor device of the ninth embodiment, a P well 122
Is formed, and an N-channel transistor 252e is formed thereon.
Are formed. An n ⁺ region 218 corresponding to node N 1 is formed in a region sandwiched between gate electrodes 220, and N channel transistor 25 is formed outside gate electrode 220.
An n ⁺ region 224 serving as a source of 2e is formed.
N ⁺ region 224 is coupled to internal power supply potential Vcc. Gate electrode 220 is coupled to ground potential.

Outside N-channel transistor 252e
Is formed with a trench portion 226, and n ⁺Along area 224
So n⁺Type polysilicon 104 is on the side wall of the trench.
Deposited on An insulating film 10 is formed on the polysilicon 104.
2 are formed.

In the semiconductor device of the ninth embodiment, the structure can be such that four sides of the n ⁺ region into which electrons are injected first are surrounded by the trench side walls, so that the undershoot resistance is higher than that of the semiconductor device of the eighth embodiment. It can be further improved.

[Modification 1 of Ninth Embodiment] FIG. 53 is a plan view showing a plane of an N-channel transistor 252f in a semiconductor device of a modification 1 of the ninth embodiment.

[0267] With reference to FIG. 53, in the case of the semiconductor device of the first modification of the ninth embodiment, in FIG. 50 of Embodiment 9, the n ⁺ region 224, in place of the trench portion 226, respectively n ⁺ region 228 and a trench 230.

FIG. 54 is a sectional view showing a section taken along line BB 'in FIG. Referring to FIG. 54, a semiconductor device according to a first modification of the ninth embodiment has a P-type silicon substrate 120.
Above, a trench portion 230 is formed outside the N-channel transistor 252f. The trench 230 has an inversely tapered side wall.

In N-channel transistor 252f, n ⁺ region 218 corresponding to node N1 sandwiched between gate electrodes 220 is formed, and N ⁺ region is formed outside gate electrode 220 along the side wall of the reverse tapered trench portion. An n ⁺ region 228 that is a source of the channel transistor 252f is formed. An n ⁺ type polysilicon 174 is deposited on the trench side wall along the n ⁺ region 228, and an insulating film 176 is deposited thereon.

N ⁺ region 228 is coupled to internal power supply potential Vcc, and gate electrode 220 is coupled to the ground potential.

Since a reverse bias is applied to the PN junction at the boundary between the n ⁺ region 228 and the P well 122, the depletion layer extends toward the P well with the width of W.

At this time, the electron injection aperture angle β in the y direction is represented by the following equation. ^{β = π / 2-tan -1} ((d T + W) / (m-L A -d n -W)) ... (10) FIG. 55 is a cross-section showing the structure of a cross section of A-A 'in FIG. 53 FIG.

Referring to FIG. 55, in the semiconductor device of the first modification of the ninth embodiment, a P well 122 is formed on a P type silicon substrate 120, and an N channel transistor 252 is formed.
A trench 230 is formed outside f. The trench 230 has an inversely tapered side wall.

The transistor 252f has a gate electrode 2
An n ⁺ region 218 corresponding to the node N1 sandwiched between the gate electrodes 30 is formed, and an N channel transistor 25 is formed outside the gate electrode 230 along the side wall of the reverse tapered trench portion.
An n ⁺ region 228 that is a source of 2f is formed.
An n ⁺ type polysilicon 174 is deposited on the trench side wall along the n ⁺ region 228, and an insulating film 176 is deposited thereon.

N ⁺ region 228 is coupled to internal power supply potential Vcc, and gate electrode 230 is coupled to ground potential.

In the first modification of the ninth embodiment, since the structure is formed so as to surround the four directions with the trench side walls, the undershoot resistance can be further improved as compared with the first modification of the eighth embodiment.

[Tenth Embodiment] In the semiconductor device of the tenth embodiment, the structure of the N-channel transistor in the undershoot countermeasure element is the structure shown by N-channel transistor 252g described below.

FIG. 56 is a plan view of an N-channel transistor 252g in the semiconductor device of the tenth embodiment.

Since the plan view of FIG. 56 has the same structure as the plan view of FIG. 35 in the sixth embodiment, description thereof will not be repeated.

FIG. 57 is a sectional view showing a section taken along line BB 'in FIG. Referring to FIG. 57, the semiconductor device of the tenth embodiment has a P-type silicon substrate
Well 122 is formed, and N-channel transistor 25 is formed.
A trench 244 is formed outside 2g.

An N ⁺ region 234 corresponding to node N 1 sandwiched between gate electrodes 236 is formed in N channel transistor 252 g, and N channel transistor 252 g is formed outside gate electrode 236 along the side wall of trench portion 244. N ⁺ region 240 is formed. n in line with the n ⁺ region 240 ⁺ polysilicon 10
4 is deposited on the side wall of the trench, and an insulating film 102 is
Are formed.

N ⁺ region 240 is coupled to internal power supply potential Vcc, and gate electrode 236 is coupled to ground potential.

Since a reverse bias is applied to the PN junction at the boundary between n ⁺ region 240 and P well 122, depletion layer 268 is formed toward the inside of P well 122.

The n ⁺ region 234 is divided at the center by an element isolation region 238, and a trench 242 is formed at the center of the element isolation region 238. The central element isolation region 238 may be completely replaced with the central trench 242.

In the semiconductor device of the tenth embodiment, the normal element isolation region 22 at the center in FIG.
In this structure, injected electrons are prevented from moving to the side where the opening angle is widened beyond P2 to the P well and the P-type silicon substrate.

In the tenth embodiment, since the opening angle of the electron injection in the y direction (BB ′ direction) is blocked by the central trench portion, the trench side wall portion closer to n ⁺ region 234 into which electrons are injected is closer. Is determined by the larger of the opening angle with the n ⁺ region 240 and the opening angle with the central trench portion.

Here, it is easy to adjust the size of n ⁺ region 234 and the size of element isolation region 238 so that the opening angle is determined by n ⁺ region 240 on the closer trench side wall portion. it can. The electron injection aperture angle in the y direction at this time is expressed by the same formula as the electron injection aperture angle in the x direction.

FIG. 58 is a cross section taken along line AA 'of FIG.
FIG. Referring to FIG. 58, in the tenth embodiment,
The semiconductor device has a P-well on a P-type silicon substrate 120.
122 are formed on which the N-channel transistor 2 is formed.
52 g are formed. Sandwiched between the gate electrodes 236
In the area, n corresponding to the node N1 ⁺Region 234 is formed
And an N-channel transistor outside the gate electrode 236.
N which is the source of⁺Area 240 is formed
I have. n⁺Region 240 is coupled to internal power supply potential Vcc.
ing. Gate electrode 236 is coupled to ground potential.
You.

Outside N-channel transistor 252g
Is formed with a trench portion 244, and n ⁺Along area 244
So n⁺Type polysilicon 104 is on the side wall of the trench.
Deposited on An insulating film 10 is formed on the polysilicon 104.
2 are formed.

In the tenth embodiment, the electron injection aperture angles in the x and y directions are represented by α shown in equation (7).

In the semiconductor device of the tenth embodiment, the electron injection aperture angle in the y direction can be made smaller than that of the semiconductor device of the ninth embodiment, so that the undershoot resistance can be further improved.

[First Modification of Tenth Embodiment] FIG. 59 is a plan view showing a planar structure of an N-channel transistor 252h according to a first modification of the tenth embodiment.

Referring to FIG. 59, the structure of the N-channel transistor 252h in the first modification of the tenth embodiment is different from the structure of the trench portion 242,
6 and 250, and has an n ⁺ region 248 instead of the n ⁺ region 240, which is different from the semiconductor device of the tenth embodiment.

FIG. 60 is a cross sectional view showing a cross sectional structure taken along line BB 'of FIG. Referring to FIG. 60, in the semiconductor device of the first modification of the tenth embodiment, a P well 122 is formed on a P type silicon substrate 120, and an N channel transistor 252h is formed thereon. Trench portion 250 is provided outside N-channel transistor 252h.
Are formed. The trench 250 has an inversely tapered side wall.

In N-channel transistor 252h, n ⁺ region 234 corresponding to node N1 sandwiched between gate electrodes 236 is formed, and outside gate electrode 236, along the side wall of inverted tapered trench portion 250. An n ⁺ region 248, which is the source of N channel transistor 252h, is formed. An n ⁺ type polysilicon 174 is deposited on the trench side wall along the n ⁺ region 248, and an insulating film 176 is deposited thereon. The n ⁺ region 234 has a central portion divided by an element isolation region, and a trench portion 246 is further formed at the central portion. This trench portion 24
6 also has an inversely tapered side wall.

N ⁺ region 248 is coupled to internal power supply potential Vcc, and gate electrode 236 is coupled to ground potential. Therefore, a reverse bias is applied to the PN junction at the boundary between n ⁺ region 248 and P well 122, so that depletion layer 270 expands into the P well.

As described above, trench portions 250 and 246
Has an inversely tapered side wall, the semiconductor device of the first modification of the tenth embodiment has a further smaller electron injection aperture angle in the y direction than the semiconductor device of the tenth embodiment.

FIG. 61 is a cross sectional view showing a cross sectional structure taken along AA 'in FIG. Referring to FIG. 61, in the semiconductor device of the first modification of the tenth embodiment, P well 122 is formed on P type silicon substrate 120, and trench portion 250 is formed outside N channel transistor 252h. . The trench 250 has an inversely tapered side wall.

An N ⁺ region 234 corresponding to node N 1 sandwiched between gate electrodes 236 is formed in N channel transistor 252 h, and N ⁺ region is formed outside gate electrode 236 along the sidewall of inverted tapered trench 250. An n ⁺ region 248 that is a source of the channel transistor 252h is formed. An n ⁺ type polysilicon 174 is deposited on the trench side wall along the n ⁺ region 248, and an insulating film 176 is deposited thereon.

At this time, the electron injection aperture angle in the x and y directions is represented by α shown in equation (8).

[Eleventh Embodiment] FIG. 62 shows an undershoot preventing element 6 in a semiconductor device of an eleventh embodiment.
It is a circuit diagram of 4b.

The undershoot preventing element 64b is the undershoot preventing element 6 shown in FIG.
4A in that an N-channel transistor 284 is provided instead of the N-channel transistor 252.

The difference between N-channel transistor 252 and N-channel transistor 284 is that the potential of the drain has changed from internal power supply potential Vcc to internal boosted potential Vpp. The other portions have the same configuration as that of FIG. 41, and therefore description thereof will not be repeated.

In the semiconductor device of the eleventh embodiment, the internal boosted potential Vpp is coupled to the drain of N-channel transistor 284 in undershoot countermeasure element 64b, and the potential of the P-well where N-channel transistor 284 is formed is equal to the substrate potential. The potential is VBB. Therefore,
The depletion layer at the PN junction at the boundary between the drain of the N-channel transistor 284 and the P well has a drain of Vcc
, The electron injection aperture angle can be further reduced.

Therefore, the potential of the drain of the transistor having the planar structure and the sectional structure shown in the seventh to tenth embodiments is changed from internal power supply potential Vcc to internal boosted potential Vpp.
By changing to, the undershoot resistance is further increased.

[0306] above, in the form 11 in the form 1 implementation of embodiments have been described in the example where there is a part in the n ⁺ region of the trench sidewalls and trench bottom, only the trench sidewall n ⁺
Even in the case where there is a region or the case where there is an n ⁺ region only halfway through the side wall, the same effect can be obtained because the electron injection aperture angle can be reduced.

[Twelfth Embodiment] FIG. 63 is a circuit diagram of an undershoot countermeasure element used in a semiconductor device of a twelfth embodiment.

The undershoot countermeasure element includes a resistor 28 connected between input node Vin and node NP1.
6, a P-channel transistor 28 whose gate and source are connected to node NP1, whose drain is coupled to ground potential, and whose N-well potential of the substrate portion is set to internal power supply potential Vcc.
8 is included. The node NP1 is used as an output terminal of the undershoot countermeasure element, as shown in FIG.
Are connected to the input of an inverter 68 included in

The resistor 286 is preferably not a diffused resistor formed on a substrate but a polysilicon resistor or the like.

The threshold value of P channel transistor 288 is set to, for example, -1V. When a potential of -1 V or less is applied to node NP1, P-channel transistor 288 is turned on, and the potential applied to node NP1 drops to the side of ground potential Vss coupled to the drain of P-channel transistor 288.

Even if a negative potential having a larger absolute value is applied to node NP1, P-channel transistor 28
8 is conductive, the potential of node NP1 is at ground potential V
It is kept near ss.

At this time, even when the input waveform changes from the positive potential to the negative potential quickly, the PN junction at the source of the P-channel transistor 288 remains between the application of the negative potential and the conduction of the P-channel transistor 288. Since this potential difference is in the opposite direction, electrons are not injected into the substrate with respect to the undershoot up to the reverse breakdown voltage of the PN junction.

Therefore, it is possible to make the undershoot very strong. Conversely, if a positive potential is applied to node NP1, if this positive potential is lower than internal power supply potential Vcc, P-channel transistor 288 is off, and PN of the source of P-channel transistor 288 is turned off.
Joining also does not go forward.

Further, internal power supply potential Vc is applied to node NP1.
When a positive potential equal to or higher than c is applied, the PN junction at the source of the P-channel transistor 288 becomes forward, and holes are injected into the N well where the P-channel transistor 288 is formed. However, since the current is suppressed by the resistor 286, a large current does not flow into the node NP1 even if an overshoot having a peak potential equal to or higher than the internal power supply potential Vcc is slightly present in the input signal. Therefore,
There is no problem because the P-channel transistor 288 is not destroyed.

In order to reduce the current density at this time, it is possible to cope with this by increasing the transistor width of the P-channel transistor 288.

As described above, in the twelfth embodiment, the P-channel transistor 288 and the resistor 286 constitute an undershoot countermeasure element. Therefore, in the normal use range where the reverse breakdown voltage of the PN junction is not exceeded, Are not injected with electrons. Therefore, an operation failure when an undershoot is applied to an input signal to the semiconductor device hardly occurs, which is very effective in stabilizing the operation of the semiconductor device.

[Thirteenth Embodiment] FIG. 64 is a circuit diagram of an undershoot countermeasure element in a semiconductor device according to a thirteenth embodiment.

Referring to FIG. 64, undershoot countermeasure element 64c has a resistor 72 connected between input node EN and node N1, a source and a gate connected to ground potential, and a drain connected to node N1. N-channel transistor 7 having substrate portion coupled to substrate potential VBB
And a parasitic npn bipolar transistor (BJT) 73 having an emitter connected to node N1, a base connected to substrate potential VBB, and a collector connected to ground potential.

This resistor 72 is formed by a polysilicon resistor or p ⁺
Diffusion resistance may be used. That is, any resistor may be used as long as it does not have an n ⁺ region on the P substrate. Where p
^{In the} case of using a ⁺ diffusion resistor, it is necessary to raise the potential of the N well where the p ⁺ diffusion resistance is formed to an internal power supply potential Vcc or more in consideration of an overshoot above the internal power supply potential Vcc.

The drain of N-channel transistor 74 connected to node N1 is an n ⁺ region to which an input signal is applied first, and is formed on a P substrate.

FIG. 65 shows an N-channel transistor 7 which is a structural example of the N-channel transistor 74 in FIG.
It is a top view of 4k.

The semiconductor device of the thirteenth embodiment includes an N-channel transistor 74k shown in FIG. 65 as the N-channel transistor 74 in FIG.

Referring to FIG. 65, N-channel transistor 74k is isolated from other elements on the semiconductor substrate by ordinary element isolation regions 82a and 82b such as LOCOS and shallow trenches. The normal element isolation region 82a and the normal element isolation region 82b are separated by the trench 86. The trench portion 86 is formed so as to surround four sides of the N-channel transistor 74k. The trench portion 86 is formed generally deeper than the bottom surfaces of the element isolation regions 82a and 82b.

FIG. 66 is a sectional view showing the structure of the section taken along line AA 'of FIG. FIG. 67 is a cross-sectional view showing a structure of a cross section taken along line BB 'of FIG.

Referring to FIGS. 66 and 67, the thirteenth embodiment
In the semiconductor device described above, a P-well 122 is formed on a P-type silicon substrate 120 and an N-channel transistor 7 is formed thereon.
4k are formed. An n ⁺ region 90 corresponding to node N1 in FIG. 64 is formed, and an n ⁺ region 88a serving as the source of N channel transistor 74k is formed.
^A gate electrode 84 is formed above a region sandwiched between ⁺ regions 88a and 90. N ⁺ region 88a and gate electrode 84 are coupled to ground potential. Parasitic npn bipolar transistor 73 includes n ⁺ region 90, P well 1
22 and n ⁺ region 88b formed on the side wall and bottom surface of trench portion 86. P well 122 corresponds to the base, and n ⁺ region 88b corresponds to the collector.

[0326] On the outside of the N-channel transistor 74k, there is normally the isolation region 82b, is further trench portion 86 is formed outside, n ⁺ -type polysilicon film 1
04 is deposited inside the trench.

Transistor 74k is normally connected to node N
When the potential of 1 is a positive potential, it is in a non-conductive state. Then, the state of the PN junction at the boundary between n ⁺ region 90 and P well 122 is kept in a non-conductive state until the potential of node N1 exceeds the reverse breakdown voltage.

The reverse breakdown voltage is usually 8 V or more and 5 V
There is no problem with the operation of related devices. In addition, since a power supply potential suitable for device design rules is used, there is no problem even if the reverse breakdown voltage is not considered in a voltage range normally used for each device.

Next, steps for forming the structure shown in FIGS. 66 and 67 will be described. 68 to 72 are cross-sectional views showing each step of forming the structure of FIG.

The following description is for the case where a trench isolation structure is provided. Referring first to FIG. 68, a silicon oxide film of 300Å thickness of about by CVD (SiO ₂₎
After depositing (or forming by thermal oxidation) 134 and forming an underlying oxide film, a resist is applied and a resist mask 132 is formed by a lithography process. Then, the silicon substrate is etched by anisotropic etching to form an element isolation trench which is usually an element isolation region.

Referring to FIG. 69, a resist mask 132
Is removed, and a silicon oxide film 102 having a thickness enough to bury the element isolation trench portion is deposited by a CVD method. After that, a resist is applied and a resist mask is formed by a lithography process. Then, an element formation region is exposed by an etching process.

Next, the process proceeds to an LDD transistor forming step. Referring to FIG. 70, an n ⁺ polysilicon (or polycide) film for gate electrode 84 is formed, and side walls 142 are formed. Acceleration voltage 50 keV, at a dose of 10 ¹³ ~10 ¹⁴ / cm ² by injecting arsenic (As), to form an n ⁺ region 90,88a as source and drain regions of the N-channel transistor.

Referring to FIG. 71, the transistor portion is
Silicon oxide film 1 having a thickness of about 1000 ° by VD method
Then, a resist mask 152 for forming a trench portion is formed thereon. The silicon oxide film 148 and the silicon substrate are etched by an anisotropic etching process.

Referring to FIG. 72, a resist mask 152
Is removed, and an n ⁺ polysilicon film 104 having a thickness enough to fill the trench portion 86 is deposited by a CVD method. Thereafter, a resist mask covering the trench portion 86 is formed, and n
⁺ Polysilicon film 104 is made of hydrofluoric nitric acid (HF, HNO ₃ )
Etching is performed in the processing, and the resist mask is removed. Thereafter, n ⁺ region 88b in the trench portion is self-formed in a diffusion step (for example, at 800 ° C. for 30 minutes).

Thereafter, an undershoot countermeasure element is connected to a predetermined node in the interlayer insulating film forming step, the contact hole step, and the metal wiring step.

Although the above description has been made with the transistor having the LDD structure, a single drain transistor may be used.
Further, a transistor having another MIS structure may be used.

Although the entire trench portion 86 has been described as being filled with the n ⁺ polysilicon film 104, the thickness may be sufficient to cover the trench side wall and the bottom surface and connect the n ⁺ polysilicon film in the metal wiring step. . Further, this n ⁺ polysilicon film may be used as a wiring layer.

In the above, the manufacturing process of an undershoot countermeasure element having a trench isolation structure has been described.
It is also possible to form an element isolation trench portion with an isolation structure.

In the case of the LOCOS isolation structure, the steps shown in FIGS. 68 and 69 correspond to the LOCOS separation explained in FIGS. 14 and 15.
The S step is performed, and thereafter, it can be formed using the steps described with reference to FIGS.

Referring again to FIGS. 64 and 66, the threshold voltage of transistor 74k is set to 1 V, for example. When a potential of -1 V or less is applied to node N1, transistor 74k is turned on, and electrons escape from n ⁺ region 88a to ground potential Vss.

Normally, the substrate potential VB is applied to the P-type silicon substrate.
B is applied. For example, VBB is set to -1.5V.

Here, undershoot of -1.5 V or less
Is applied to the node N1 with a pulse width tp,
During the period tp when the transistor 74k is conductive, the node N1
N ⁺At the PN junction at the boundary between the region 90 and the P well 122
When a forward voltage is applied, electrons flow through the P-well 122 and the P-type
It will be implanted into the silicon substrate 120.

Here, the electron is n⁺P-well from region 90
122 and p-type silicon substrate 120
Consider the electron injection aperture angle. D in FIG._TIs training
The depth of the punch. d_nIs the junction depth of the transistor
You. dd is a junction depth formed in the trench portion.
You. L1 is n of the node N1 in the x direction (A-A 'direction).
⁺The distance from the end of the region 90 to the trench sidewall. This
The electron injection aperture angle α in the AA ′ direction at the time of
Is represented.

[0344] ^{α = π / 2-tan -1} ((d T + dd-d n) / (L1-dd)) ... (11) with reference to FIG. 67, the L2 is, y direction of the node N1 n ⁺
The distance from the region 90 to the trench side wall.

The electron injection aperture angle β in the BB ′ direction is expressed by the following equation. ^{β = π / 2-tan -1} ((d T + dd-d n) / (L2-dd)) ... (12) injected electrons with a large injection angle than the opening angle α to the x direction of FIG. 65 It can be captured on the trench side wall.

In the y direction, electrons injected at an injection angle larger than the opening angle β can be captured on the side wall. Therefore, the undershoot resistance is improved.

At the time when electrons are injected, a channel is formed in the N-channel transistor 74k. As the potential having a large absolute value in the negative direction is applied to the node N1, the electric field between the n ⁺ region 90 and the trench side wall n ⁺ region 88 also increases, and a considerable number of electrons travel to the side wall. The undershoot resistance is further improved.

Further, the resistor 72 functions to reduce a sudden undershoot of a negative pulse because it makes it difficult for a current to flow.

That is, the N-channel transistor 74k
There is an operation of increasing the time from the conduction state of the PN junction in the forward direction of the PN junction and an operation of decreasing the absolute value of the potential of the negative pulse.

Therefore, the resistance to undershoot is improved because the resistor 72 is located in front of the node N1.

Further, since the resistor 72 is provided, it is not necessary to increase the area of the node N1 in consideration of heat generated by current. If the area of the node N1 can be reduced, L1 in FIG. 66 (the distance from the end of the n ⁺ region of the node N1 to the trench side wall) can be reduced accordingly, so that the electron injection aperture angle can be reduced. Therefore, the undershoot resistance is improved as compared with the case where the resistor 72 is not provided.

Semiconductor Device of First Embodiment and First Embodiment
The difference from the semiconductor device of No. 3 is that the trench can be formed after the transistor is formed, so that even if the transistor has a single gate, the trench can be surrounded on all four sides without dividing the gate. This allows
The aperture angle can be reduced, and the area of the undershoot prevention element can be reduced.

Also, oblique ion implantation is not required to form the n ⁺ region in the trench portion, and the process for forming the side wall polysilicon can be simplified. Furthermore, since the ground potential can be supplied to the n ⁺ region formed on the side wall of the trench portion, electrons injected from other places can be absorbed, and the undershoot resistance is further improved.

[Modification 1 of the thirteenth embodiment] In the semiconductor device of the modification 1 of the thirteenth embodiment, the structure of the N-channel transistor in the undershoot countermeasure element is represented by an N-channel transistor 74l described below. Becomes The undershoot resistance can be improved by further reducing the electron injection aperture angle in the x direction as compared to the thirteenth embodiment.

FIG. 73 is a plan view of an N-channel transistor 74l in a semiconductor device according to a first modification of the thirteenth embodiment.

Referring to FIG. 73, an N-channel transistor 74l is isolated from other elements on a semiconductor substrate by ordinary element isolation regions 82a and 82b such as LOCOS and shallow trenches.

The normal element isolation region 82a and the normal element isolation region 82b are separated by a trench 94. This trench portion 94 is formed to surround four sides of N-channel transistor 74l. This trench portion 94 is formed to be deeper than the bottom surfaces of the element isolation regions 82a and 82b.

FIG. 74 is a cross sectional view showing the structure of the AA 'cross section of FIG. 73. FIG. 75 is a cross-sectional view showing a structure taken along the line BB 'of FIG. 73.

Referring to FIGS. 74 and 75, the thirteenth embodiment
In the semiconductor device of the first modification, a P-well 122 is formed on a P-type silicon substrate 120, and an N-channel transistor 74l is formed on a main surface of the P-well.

[0360] On the outside of the N-channel transistor 74l, there is normally the isolation region 82b, the trench portion 94 is formed on the further outside, n ⁺ -type polysilicon film 10
4 is deposited inside the trench portion 94. The trench 94 has an inversely tapered side wall.

The manufacturing process is the same as the process described with reference to FIGS. 68 to 72 except that the trench portion has an inverted tapered shape. The step of making the side wall portion reversely tapered is shown in FIG.
Is the same as

In order to form a reverse tapered shape, anisotropic etching is performed by setting the implantation angle of etching ions to θ ′ (for example, 20 °).

In order to make the implantation angle of the etching ions θ ′, the wafer is set to anisotropic etching by tilting the wafer by θ ′,
Rotate the wafer turntable. With this method, the implantation angle of the etching ions can be set to θ ′. Other steps are the same as the steps described in the thirteenth embodiment, and description thereof will not be repeated.

Referring to FIG. 74, the electron injection aperture angle will be considered. In FIG. 74, LA is a biting distance into which the reverse tapered side wall of the trench portion 94 enters the lower portion of the transistor 74l. d _T is the trench depth. d _n is the junction depth of the transistor section. dd
Is the junction depth self-formed in the trench. L1 is the distance from the end of the n ⁺ region 90 of the node N1 to the trench sidewall in the x direction (AA 'direction). At this time, the electron injection aperture angle α in the AA ′ direction is represented by the following equation.

[0365] ^{α = π / 2-tan -1} ((d T + dd-d n) / (L1-LA-dd)) ... (13) with reference to FIG. 75, B-B 'direction of the electron injection opening The angle β is represented by the following equation.

[0366] ^{β = π / 2-tan -1} ((d T + dd-d n) / (L2-LA-dd)) ... (14) The semiconductor device of the first modification of the embodiment 13, embodiment 13, the x direction from the n ⁺ region to which the input signal is first applied to the P-type silicon substrate,
Since the electron injection aperture angle in the direction can be reduced, the undershoot resistance is further improved.

[Fourteenth Embodiment] FIG. 76 is a circuit diagram showing an undershoot countermeasure element in a semiconductor device of a fourteenth embodiment.

The semiconductor device of the fourteenth embodiment differs from the semiconductor device of the thirteenth embodiment in having an undershoot preventing element 64d shown in FIG. 76 instead of the undershoot preventing element shown in FIG.

This undershoot preventing element includes a resistor 72 connected between input node EN and node N1,
An N-channel transistor 75 having a source connected to node N1, a gate connected to ground potential, a drain connected to internal power supply potential Vcc, and a substrate portion connected to substrate potential VBB, an emitter connected to node N1, and a base connected to node N1. A parasitic npn bipolar transistor 73 coupled to substrate potential VBB and having a collector coupled to ground potential.

The resistor 72 is formed by a polysilicon resistor or p ⁺
Diffusion resistance may be used. That is, any resistor may be used as long as it does not have an n ⁺ region on a P-type silicon substrate.
However, considering that a waveform on which an overshoot equal to or higher than the internal power supply potential Vcc is applied is applied, when the p ⁺ diffusion resistance is used, the potential of the N well where the p ⁺ diffusion resistance is formed is set to the internal power supply potential Vcc or more It needs to be raised.

An input signal is applied to node N1 first.
N formed on a P-type silicon substrate ⁺Area.

In the fourteenth embodiment, N-channel transistor 75 is an N-channel transistor 75a described below.
It has a structure shown by.

FIG. 77 shows an N-channel transistor 75a.
FIG. The plan view shown in FIG.
3 in FIG. 65, an N-channel transistor 75a is used instead of the N-channel transistor 74k.
including. Other structures are the same as those in the plan view shown in FIG. 65, and therefore description thereof will not be repeated.

FIG. 78 is a sectional view showing a section taken along line AA 'in FIG. FIG. 79 is a cross-sectional view of FIG.
It is sectional drawing which shows the cross section in B '.

N channel transistor 75a shown in FIGS. 78 and 79 is different from the embodiment shown in the thirteenth embodiment in that n ⁺ region 88a is coupled to internal power supply potential Vcc and depletion layer 256a exists. Other portions are the same as those of N channel transistor 74k shown in FIG. 66, and therefore description will not be repeated.

At this time, the electron injection aperture angles α and β in the x direction (AA ′ direction) and the y direction (BB ′ direction) are expressed by the above-described equations (11) and (12), respectively. It is.

Although the electron injection aperture angle is the same as that of the thirteenth embodiment, the drain of transistor 75a is connected to internal power supply potential Vcc, so that the n ⁺ region 90 is lower than when grounded. And the electric field existing between n ⁺ region 88a of the drain portion is further increased.

In addition, at the time when electrons are injected, a channel is formed in the N-channel transistor 75a. When a potential having a large absolute value is applied to the node N1 in the negative direction, the electric field increases, and the number of electrons traveling to the drain direction or the trench side wall in the drain direction becomes larger than in the thirteenth embodiment. Therefore, many electrons are absorbed in n ⁺ region 88a of the drain portion and n ⁺ region 88b present on the trench side wall in the drain direction, and the undershoot resistance is improved.

Further, the resistor 72 functions to alleviate a sudden undershoot negative pulse because it makes the current hard to flow.

That is, N-channel transistor 75a
There is an operation of extending the time required for the PN junction to reach the forward direction after the conduction state is established, and an operation of decreasing the absolute value of the potential of the negative pulse.

Therefore, since the resistor 72 is located before the node N1, the undershoot resistance is improved.

[Modification 1 of Embodiment 14] In Modification 1 of Embodiment 14, the N-channel transistor 75 has a structure represented by an N-channel transistor 75b described below.

FIG. 80 shows an N-channel transistor 75b.
FIG. The plan view shown in FIG.
77 has an N-channel transistor 75b in place of the N-channel transistor 75a, and has a trench 94 in place of the trench 86.

Since the structure is otherwise the same as that of FIG. 77, description thereof will not be repeated. FIG. 81 is a cross-sectional view showing a cross section taken along AA ′ in FIG. 80.

FIG. 82 is a sectional view showing a section taken along line BB 'in FIG. Referring to FIGS. 81 and 82, in the semiconductor device of the first modification of the fourteenth embodiment, P well 122 is formed on P type silicon substrate 120, and trench portion 94 is formed outside N channel transistor 75b. Have been. The trench 94 has an inversely tapered side wall.

Since the other parts are the same as those of the fourteenth embodiment shown in FIGS. 78 and 79, description thereof will not be repeated.

At this time, the electron injection aperture angles α and β in the x direction (AA ′ direction) and the y direction (BB ′ direction) are expressed by equations (13) and (14), respectively.

The semiconductor device of the first modification of the fourteenth embodiment is different from the semiconductor device of the fourteenth embodiment in that the x direction from the n ⁺ region 90 to which an input signal is first applied to the P-type silicon substrate is smaller. Since the electron injection aperture angle in the y direction can be reduced, the undershoot resistance is further improved.

[Embodiment 15] FIG. 83 shows an undershoot countermeasure element 6 in a semiconductor device of embodiment 15 of the present invention.
It is a circuit diagram which shows 4e.

The semiconductor device of the fifteenth embodiment is different from the semiconductor device of FIG.
The semiconductor device of the thirteenth embodiment differs from the semiconductor device of the thirteenth embodiment in having an undershoot countermeasure element 64e shown in FIG.

An undershoot countermeasure element 64e includes a resistor 72 connected between input node EN and node N1.
An N-channel transistor 74 whose source and gate are connected to ground potential, whose drain is connected to node N1 and whose substrate portion is connected to substrate potential VBB, and whose emitter is connected to node N1 and whose base is connected to substrate potential VBB. And a parasitic npn bipolar transistor 77 having a collector coupled to internal power supply potential Vcc.

This resistor 72 is formed by a polysilicon resistor or p ⁺
Diffusion resistance may be used. That is, any resistor may be used as long as it does not have an n ⁺ region on a P-type silicon substrate.
However, considering that a waveform on which an overshoot equal to or higher than the internal power supply potential Vcc is applied is applied, when the p ⁺ diffusion resistance is used, the potential of the N well where the p ⁺ diffusion resistance is formed is changed to the internal power supply potential Vcc. It is necessary to raise it above.

The input signal is applied to node N1 first.
N formed on a P-type silicon substrate ⁺Area.

In the fifteenth embodiment, N-channel transistor 74 has a structure indicated by N-channel transistor 74m described below.

FIG. 84 shows an N-channel transistor 74m.
FIG. Referring to FIG. 84, N-channel transistor 74m has the same structure as N-channel transistor 74k shown in FIG. 65, and therefore description will not be repeated.

FIG. 85 is a sectional view showing a section taken along line AA 'in FIG. FIG. 86 is a cross-sectional view of FIG.
It is sectional drawing which shows the cross section in B '.

An N-channel transistor 74 shown in FIG.
The embodiment 13 is characterized in that the n ⁺ region 88b is coupled to the internal power supply potential Vcc, and the depletion layer 256b exists in the thirteenth embodiment.
It is different from the case. The other parts are the same as those in the thirteenth embodiment shown in FIG. 66, and the description will not be repeated.

Assuming that the thickness of the depletion layer extending from the n ⁺ region 88b into the P well is W, the electron injection aperture angle α in the x direction (AA ′ direction) is represented by the following equation.

[0399] The ^{α = π / 2-tan -1} ((d T + dd + W-d n) / (L1-dd-W)) ... (15), with reference to FIG. 86, y-direction (B-B ' Direction) is expressed by the following equation.

[0400] ^{β = π / 2-tan -1} ((d T + dd + W-d n) / (L2-dd-W)) ... (16) above, the amount corresponding to the embodiments depletion layer is spread 13, the electron injection aperture angle can be made smaller, so that the undershoot resistance is further improved.

Further, the depletion layer extends from the n ⁺ region existing on the side wall of trench portion 86.
3, the probability of absorbing electrons injected from other places is increased, and the undershoot resistance is improved.

[Modification 1 of the fifteenth embodiment] An N-channel transistor 74 according to a first modification of the fifteenth embodiment is described.
Has a structure shown by an N-channel transistor 74n described below.

FIG. 87 shows an N-channel transistor 74n.
FIG. The plan view of FIG. 87 is different from the plan view of the fifteenth embodiment shown in FIG. 84 in that an N-channel transistor 74n is provided instead of N-channel transistor 74m and a trench portion 94 is provided instead of trench portion 86. . Other structures are the same as those in the plan view shown in FIG. 84, and description thereof will not be repeated.

FIG. 88 is a sectional view showing a section taken along line AA 'in FIG. FIG. 89 is a cross-sectional view of FIG.
It is sectional drawing which shows the cross section in B '.

Referring to FIGS. 88 and 89, the first embodiment
The semiconductor device according to the first modification of the fifth embodiment includes a P-type silicon substrate 120.
A P-well 122 is formed on the N-channel transistor 74, and a trench 94 is formed outside the N-channel transistor 74n.
The trench 94 has an inversely tapered side wall.

The other parts are the same as those in the fifteenth embodiment, and the description will not be repeated. Referring to FIG. 88, the electron injection aperture angle α in the x direction (AA ′ direction) is represented by the following equation.

[0407] ^{α = π / 2-tan -1} ((d T + dd + W-d n) / (L1-LA-dd-W)) ... (17) with reference to FIG. 89, y-direction (B-B ' Direction) is expressed by the following equation.

[0408] ^{β = π / 2-tan -1} ((d T + dd + W-d n) / (L2-LA-dd-W)) ... (18) The semiconductor device of the first modification of the embodiment 15, embodiment As compared with the semiconductor device of the fifteenth aspect, since the trench portion has an inversely tapered shape, the x direction from the n ⁺ region 90 to which the input signal is first applied toward the P-type silicon substrate, Since the electron injection aperture angles α and β in the y direction can be reduced, the undershoot resistance is further improved.

[Sixteenth Embodiment] FIG. 90 shows an undershoot countermeasure element 6 in a semiconductor device of a sixteenth embodiment.
It is a circuit diagram which shows 4f.

The semiconductor device of the sixteenth embodiment differs from the semiconductor device of FIG.
The semiconductor device of the fourteenth embodiment is different from the semiconductor device of the fourteenth embodiment in that an undershoot countermeasure element 64f shown in FIG.

Referring to FIG. 90, undershoot preventing element 64f includes a resistor 72 connected between input node EN and node N1, a source connected to node N1, a gate coupled to ground potential, and a drain connected. Internal power supply potential Vc
c, an N-channel transistor 75 whose substrate is coupled to the substrate potential VBB, and an emitter connected to the node N1.
, A base is coupled to substrate potential VBB, and a collector is coupled to internal power supply potential Vcc.

[0412] The resistor 72 may be a polysilicon resistor or a p ⁺ diffusion resistor. That is, n on a P-type silicon substrate
⁺ Any resistor that does not have a region may be used. However, considering that a waveform with an overshoot equal to or higher than the internal power supply potential Vcc is applied, when a p ⁺ diffusion resistance is used, the potential of the N well where the p ⁺ diffusion resistance is formed is changed to the internal power supply potential. It is necessary to keep it higher than Vcc.

An input signal is applied to node N1 first
N formed on a P-type silicon substrate ⁺Area.

The N-channel transistor 75 of the sixteenth embodiment has a structure shown by an N-channel transistor 75c described below.

FIG. 91 shows an N-channel transistor 75c.
FIG. The plan view of FIG. 91 differs from the plan view of FIG. 77 of the fourteenth embodiment in that an N-channel transistor 75c is provided instead of N-channel transistor 75a. Structures other than the above are similar to those in the plan view of FIG.

FIG. 92 is a sectional view showing a section taken along line AA 'in FIG. FIG. 93 is a cross-sectional view of FIG.
It is sectional drawing which shows the cross section in B '.

Referring to FIGS. 92 and 93, in N channel transistor 75c, n ⁺ region 88b has an internal power supply potential V
cc and is different from the fourteenth embodiment in that depletion layer 256b is present. The other part is shown in FIG. 78,
Since the configuration is the same as that of the fourteenth embodiment shown in FIG. 79, description thereof will not be repeated.

At this time, the electron injection aperture angles α and β in the x direction (AA ′ direction) and the y direction (BB ′ direction) are expressed by the above-described equations (15) and (16), respectively. It is.

As described above, since the electron injection aperture angle can be made smaller than that of the fourteenth embodiment by the extent that the depletion layer is expanded, the undershoot resistance is improved.

Further, since the depletion layer also extends from the n ⁺ region existing on the side wall of trench portion 86, the probability of absorbing electrons injected from other places is higher than in the fourteenth embodiment. Therefore, the undershoot resistance is further improved.

[Modification 1 of Embodiment 16] An N-channel transistor 75 according to Modification 1 of Embodiment 16
Has a structure shown by an N-channel transistor 75d described below.

FIG. 94 shows an N-channel transistor 75d.
FIG. The plan view of FIG. 94 has an N-channel transistor 75d instead of the N-channel transistor 75c in the plan view of the sixteenth embodiment shown in FIG.
The difference is that a trench portion 94 is provided instead of the trench portion 86. The other configuration is the same as the configuration shown in FIG. 91, and therefore description will not be repeated.

FIG. 95 is a sectional view showing a section taken along line AA 'in FIG. FIG. 96 is a cross-sectional view of FIG.
It is sectional drawing which shows the cross section in B '.

Referring to FIGS. 95 and 96, the first embodiment
The semiconductor device according to the first modification of the sixth embodiment includes a P-type silicon substrate 120.
A P-well 122 is formed thereon, and a trench portion 94 is formed outside the N-channel transistor 75d.
The trench 94 has an inversely tapered side wall. Other parts are the same as those in the sixteenth embodiment, and therefore description will not be repeated.

At this time, the electron injection aperture angles α and β in the x direction (AA ′ direction) and the y direction (BB ′ direction) are expressed by the above-described equations (17) and (18), respectively. It is.

In the semiconductor device of the first modification of the sixteenth embodiment, the side wall of the trench portion has an inversely tapered shape as compared with the semiconductor device of the sixteenth embodiment, and n ⁺ to which an input signal is applied first is applied. The electron injection aperture angles in the x and y directions from the region 90 toward the P-type silicon substrate can be reduced. Therefore, undershoot resistance is further improved.

[Embodiment 17] FIG. 97 shows an undershoot preventing element 6 in a semiconductor device of embodiment 17.
It is a circuit diagram which shows the structure of 4g.

The semiconductor device of the seventeenth embodiment includes an N-channel transistor 79 having a different drain potential instead of the N-channel transistor 75 of the undershoot countermeasure element shown in FIG. N-channel transistor 79
Is the internal boosted potential Vpp. Other portions have the same configuration as that of FIG. 76, and therefore description will not be repeated.

In the semiconductor device of the seventeenth embodiment, the internal boosted potential Vpp is coupled to the drain of N-channel transistor 79 as an undershoot countermeasure element, and the potential of the P well is at substrate potential VBB. Therefore, FIG.
1, the drain of the depletion layer 256a has the internal power supply potential V
The electric field existing between the n ⁺ region 90 and the n ⁺ region 88a of the drain portion is further enlarged as compared with the case where the electric field is coupled to cc.

In addition, at the time when electrons are injected, since a channel is formed in N-channel transistor 79, a potential having a large absolute value is applied to node N1 in the negative direction, and this electric field increases. Of the injected electrons, more electrons than in the fourteenth embodiment go to the drain of the N-channel transistor or to the side wall of the trench existing in the drain direction.

Thus, n ⁺ region 88a of the drain portion is formed.
And more electrons are absorbed into the trench side wall existing in the drain direction, so that the undershoot resistance is improved.

Therefore, the potential of the drain of the N-channel transistor having the planar structure and the sectional structure shown in the fourteenth embodiment and the first modification of the fourteenth embodiment is changed from internal power supply potential Vcc to internal boosted potential Vpp. The undershoot resistance is further improved.

[Embodiment 18] FIG. 98 shows an undershoot preventing element 6 in a semiconductor device of an embodiment 18.
It is a circuit diagram which shows the structure of 4h.

In the semiconductor device according to the eighteenth embodiment, the undershoot countermeasure element 64e shown in FIG. 83 has a different potential at the trench portion. That is, the potential of the trench portion is changed from the internal power supply potential Vcc to the internal boosted potential Vpp, so that the parasitic npn bipolar transistor 77
Instead of the parasitic n whose collector potential is Vpp
It has a pn transistor 81.

Since the other portions have the same structure as that of FIG. 83, description thereof will not be repeated. In the semiconductor device of the eighteenth embodiment, the internal boosted potential Vpp is coupled to the trench portion of the undershoot countermeasure element, and the potential of the P well is at the substrate potential VBB.

For this reason, the trench portion shown in FIG.
The depletion layer 256b at the PN junction at the boundary with the well is
The trench portion is further expanded than when it is connected to internal power supply potential Vcc. Therefore, the electron injection aperture angle can be further reduced.

Therefore, the potential of the trench having the planar structure and the sectional structure shown in the fifteenth embodiment and the first modification of the fifteenth embodiment is further changed from internal power supply potential Vcc to internal boosted potential Vpp. The undershoot resistance is improved.

[Embodiment 19] FIG. 99 shows an undershoot preventing element 6 in a semiconductor device according to a nineteenth embodiment.
FIG. 4 is a circuit diagram showing a configuration of 4i.

In the semiconductor device of the nineteenth embodiment, in the undershoot countermeasure element 64f shown in FIG. 90, the drain potential is changed to the internal boosted potential Vpp instead of the N-channel transistor 75 having the drain of the internal power supply potential Vcc.
In that an N-channel transistor 79 is provided. Other portions have the same configuration as that of FIG. 90, and therefore description thereof will not be repeated.

In the semiconductor device of FIG. 19, the internal boosted potential Vpp is coupled to the drain of N-channel transistor 79 as an undershoot countermeasure element, and the potential of the P well is at the substrate potential VBB.

Therefore, the N-channel transistor shown in FIG.
PN contact at boundary between drain and P-well of transistor
The drain of the depletion layer 256a at the combined portion has the internal power supply potential V
Spread more than when tied to cc. Also, n
⁺Region 90 and n of the drain part ⁺Exist between area 88a
The resulting electric field is even greater. Moreover, the electron
At the time of input, the N-channel transistor 79 is charged.
Since the channel is formed, the node N1 is absolutely
This electric field increases as a potential with a higher value is applied.
Become. Then, of the injected electrons,
The number of N-channel transistor
To the trench sidewall existing in the rain or drain direction
I will head. Thereby, n of the drain part⁺region
Many electrons to the trench sidewall existing in the direction of
Because it is absorbed, the undershoot resistance is improved.

Therefore, by changing the potential of the drain of the transistor having the planar structure and the cross-sectional structure shown in the sixteenth embodiment and the first modification of the sixteenth embodiment from internal power supply potential Vcc to internal boosted potential Vpp, Further, undershoot resistance is improved.

[Twentieth Embodiment] FIG. 100 is a circuit diagram showing a configuration of an undershoot countermeasure element 64j in a semiconductor device of a twentieth embodiment.

The semiconductor device of the twentieth embodiment differs from the semiconductor device of the nineteenth embodiment in that the potential of the trench portion of the undershoot countermeasure element 64i shown in FIG. 99 is different.
That is, the potential of the trench portion is changed from the internal power supply potential Vcc to the internal boosted potential Vpp, and the potential of the collector is changed to the internal boosted potential Vpp instead of the parasitic npn bipolar transistor 77 having the internal power supply potential Vcc.
, The parasitic npn bipolar transistor 81. Other portions have the same configuration as that of FIG. 99, and therefore description thereof will not be repeated.

In the semiconductor device of the twentieth embodiment, the internal boosted potential Vpp is applied to the trench of the undershoot prevention element.
And the potential of the P well is at the substrate potential VBB. Therefore, the depletion layer at the PN junction at the boundary between the trench and the P-well has an internal power supply potential V
It is even more widespread than when tied to cc. Therefore, the electron injection aperture angle can be further reduced.

Therefore, the undershoot resistance is further improved by changing the potential of the trench side wall portion of the undershoot countermeasure element shown in the nineteenth embodiment from internal power supply potential Vcc to internal boosted potential Vpp.

[Twenty-First Embodiment] FIG. 101 is a circuit diagram showing a configuration of an undershoot countermeasure element 64k in a semiconductor device of a twenty-first embodiment.

Referring to FIG. 101, undershoot preventing element 64k includes a resistor 72 connected between input node EN and node N1, an emitter connected to node N1, and a base connected to substrate potential VBB. A parasitic npn bipolar transistor 73 having a collector coupled to ground potential Vss.

The resistor 72 is formed by a polysilicon resistor or p ⁺
Diffusion resistance may be used. That is, any resistor may be used as long as it does not have an n ⁺ region on a P-type silicon substrate.
However, considering that a waveform with an overshoot equal to or higher than the internal power supply potential Vcc is applied, when a p ⁺ diffusion resistance is used, the potential of the N well where the p ⁺ diffusion resistance is formed is changed to the internal power supply potential. It is necessary to keep it higher than Vcc.

The input signal is applied to the node N1 first.
N formed on a P-type silicon substrate ⁺Area.

FIG. 102 is a plan view of the parasitic npn bipolar transistor 73a. The semiconductor device of the twenty-first embodiment has a parasitic npn bipolar transistor having a planar structure shown in FIG.

Referring to FIG. 102, n ⁺ region 90 corresponding to node N1 is separated from other elements on the semiconductor substrate by ordinary element isolation regions 82a and 82b such as LOCOS and shallow trenches. Normal element isolation region 82
a and the normal element isolation region 82 b are separated by the trench portion 86. This trench portion 86 is formed so as to surround four sides of n ⁺ region 90. The trench portion 86 is formed generally deeper than the bottom surfaces of the element isolation regions 82a and 82b.

FIG. 103 is a sectional view showing a section taken along line AA 'in FIG. Referring to FIG. 103, in the semiconductor device of the twenty-first embodiment, a P well 122 is formed on a P-type silicon substrate 120, and an n ⁺ region 90 corresponding to node N1 is formed thereon.

There is a normal element isolation region 82b outside n ⁺ region 90, and a trench portion 86 is formed further outside. An n ⁺ polysilicon film 104 is deposited inside trench portion 86.

In the PN junction at the boundary between n ⁺ region 90 and P well 122, in a normal state, when the potential of node N1 is a positive potential, a reverse voltage is applied and electrons are injected into the substrate. There is no. No electrons are injected into the substrate until the potential of the node N1 exceeds the reverse breakdown voltage.

The reverse breakdown voltage is usually 8 V or more,
No problem occurs in the operation of the V-based device. In addition, since the power supply potential suitable for the design rules of the device is used, in the normally used voltage range of each device,
There is no problem even if the reverse breakdown voltage is not considered.

The manufacturing steps are the same as those in FIGS. 68 to 72, and FIG. 103 does not show any MOS transistor. Therefore, description will not be repeated.

Now, consider the case where a negative potential is applied to node N1. Usually, a substrate potential VBB is applied to the P-type silicon substrate. For example, if VBB is -1.
5V.

Here, when an undershoot of −1.5 V or less is applied to node N 1 with pulse width tp, PN at the boundary between n ⁺ region 90 of node N 1 and P well 122 is reduced.
A forward voltage is applied to the junction, and electrons are injected into the P well.

Here, the electron injection aperture angle at which electrons are injected from n ⁺ region 90 toward P well 122 and P type silicon substrate 120 will be considered. _{DT in} FIG. 102 is the trench depth. d _n is the junction depth of the transistor unit. dd is a junction depth formed in the trench portion. L2 is n of the node N1 in the x direction (AA ′ direction).
⁺ The distance from the end of the region 90 to the trench side wall.

At this time, the electron injection aperture angle β in the AA ′ direction in FIG. 102 is expressed by equation (12).

The electron injection aperture angle in the direction perpendicular to the AA ′ direction is represented by the same formula, except that the distance from the node N1 to the trench side wall changes. The injected electrons can be caught on the side wall except for those having an opening angle β or less, so that the undershoot resistance is improved.

Furthermore, unlike the structure including the MOS transistor, only the n ⁺ region 90 corresponding to the node N1 is on the substrate surface, so that the area of the inner element region surrounded by the trench can be reduced. Therefore, the electron injection aperture angle can be reduced, and the undershoot resistance is improved.

Also, the resistor 72 in FIG. 101 functions to alleviate the sudden undershoot of the negative pulse because it makes it difficult for the current to flow. Therefore, since the resistor 72 is located before the node N1, the undershoot resistance is improved.

Further, since the resistor 72 is provided, it is not necessary to increase the area of the node N1 in consideration of the heat generated by the current. If the area of the node N1 can be reduced, L2 in FIG. 103 can be reduced accordingly, so that the electron injection aperture angle β
Can be reduced. Therefore, the undershoot resistance is improved as compared with the case where the resistor 72 is not provided.

Further, n formed on the side wall of the trench portion
^{Since the} ground potential can be supplied also to the ⁺ region, electrons injected from other places can be absorbed, and the undershoot resistance is further improved.

[Modification 1 of Embodiment 21] In Modification 1 of Embodiment 21, the parasitic npn bipolar transistor 73 has a structure shown by a parasitic npn bipolar transistor 73b described below.

FIG. 104 is a plan view of the parasitic npn bipolar transistor 73b. In the first modification of the twenty-first embodiment, trench portion 94 is replaced with trench portion 94.
Having. The other configuration is the same as that in FIG.
Therefore, description thereof will not be repeated.

FIG. 105 is a sectional view taken along the line AA ′ in FIG.
It is sectional drawing which shows the cross section of FIG. Referring to FIG.
The semiconductor device of the first modification of the twenty-first embodiment is a P-type silicon-based semiconductor device.
A P-well 122 is formed on a plate 120, and
N that corresponds to ⁺A region 90 is formed.

There is a normal element isolation region 82b outside the n ⁺ region 90, and a trench portion 94 is formed outside the element isolation region 82b.
An n ⁺ polysilicon film 104 is deposited inside the trench. This trench has an inversely tapered side wall. Other parts are the same as those in the twenty-first embodiment, and description thereof will not be repeated.

At this time, the electron injection aperture angle β in the AA ′ direction is expressed by the above-described equation (14). A-A '
The electron injection aperture angle in the direction perpendicular to the direction is expressed by the same equation, except that the distance from the node N1 to the trench side wall changes.

The semiconductor device of the first modification of the twenty-first embodiment is different from the semiconductor device of the twenty-first embodiment in that the p-type silicon substrate 1 is moved from the n ⁺ region 90 to which an input signal is applied first.
Since the electron injection aperture angle β toward 20 can be reduced,
Further, undershoot resistance is improved.

[Embodiment 22] FIG. 106 is a circuit diagram showing a configuration of an undershoot measure element 64l in a semiconductor device of an embodiment 22.

Referring to FIG. 106, undershoot countermeasure element 64l includes a resistor 72 connected between input node EN and node N1, an emitter connected to node N1, and a base connected to substrate potential VBB. A parasitic npn bipolar transistor 77 having a collector coupled to internal power supply potential Vcc.

The resistor 72 may be a polysilicon resistor or a p ⁺ diffusion resistor. That is, n on a P-type silicon substrate
⁺ Any resistor that does not have a region may be used.

However, considering that a waveform with an overshoot higher than internal power supply potential Vcc is applied,
When the p ⁺ diffusion resistance is used, it is necessary to raise the potential of the N well where the p ⁺ diffusion resistance is formed to an internal power supply potential Vcc or higher.

Here, node N1 is an n ⁺ region formed on a P-type silicon substrate to which an input signal is applied first.

FIG. 107 is a plan view of the parasitic npn bipolar transistor 77a. In the twenty-second embodiment, the parasitic npn bipolar transistor 77 is configured as shown in FIG.
7 has a planar structure like the bipolar transistor 77a shown in FIG.

Referring to FIG. 107, n ⁺ region 90 corresponding to node N1 is separated from other elements on the semiconductor substrate by ordinary element isolation regions 82a and 82b such as LOCOS and shallow trenches. The normal element isolation region 82a and the normal element isolation region 82b are separated by the trench 86. This trench portion 86 has n ⁺
It is formed so as to surround four sides of the region 90. Trench 8
6 is formed to be deeper than the bottom surfaces of the normal element isolation regions 82a and 82b.

FIG. 108 is a sectional view showing a section taken along line AA 'in FIG. Referring to FIG. 108, in the semiconductor device of the twenty-second embodiment, a P well 122 is formed on a P-type silicon substrate 120, and an n ⁺ region 90 corresponding to node N1 is formed thereon.

There is a normal element isolation region 82b outside the n ⁺ region 90, and a trench portion 86 is formed further outside the device isolation region 82b. An n ⁺ polysilicon film 104 is deposited inside the trench portion.

In the PN junction at the boundary between the n ⁺ region 90 and the P well 122, electrons are supplied to the P well until the potential of the node N1 is a positive potential in a normal use state and exceeds the reverse breakdown voltage of the PN junction. Will not be injected into

[0483] By applying the internal power supply potential Vcc to the n ⁺ polysilicon film 104, the n ⁺ region 88b is given an internal power supply potential, P-well from the n ⁺ region 88b 12
2, the depletion layer 256b expands.

At this time, the electron injection aperture angle β in the AA ′ direction in FIG. 107 is expressed by the above-described equation (16).

The electron injection aperture angle in the direction perpendicular to the AA ′ direction is represented by the same equation, except that the distance from the node N1 to the trench side wall changes.

As described above, since the depletion layer is expanded, the electron injection aperture angle can be reduced by that much, as compared with the twenty-first embodiment, and the undershoot resistance is improved.

Further, the depletion layer extends from the n ⁺ region existing on the side wall of trench portion 86, and the probability of absorbing electrons injected from other places is higher than in the twenty-first embodiment. Improves shoot resistance.

[Modification 1 of Embodiment 22] FIG.
Is a plan view of a parasitic npn bipolar transistor 77b.

The semiconductor device of the first modification of the twenty-second embodiment has a planar structure as shown in FIG. 109 as the structure of parasitic npn bipolar transistor 77 shown in FIG.

Referring to FIG. 109, parasitic npn bipolar transistor 77b differs from bipolar transistor 77a shown in FIG. 107 in having trench portion 94 instead of trench portion 86. Other configurations are described in Embodiment 2.
Since it is similar to the parasitic npn bipolar transistor 77a of No. 2, description thereof will not be repeated.

FIG. 110 is a sectional view taken along the line AA ′ in FIG.
It is sectional drawing which shows the cross section of FIG. Referring to FIG.
A semiconductor device according to a first modification of the twenty-second embodiment has a P-type silicon-based
A P-well 122 is formed on a plate 120, and
N that corresponds to ⁺A region 90 is formed. n⁺
Outside the region 90, there is a normal element isolation region 82b,
Further, a trench portion 94 is formed outside thereof, and n⁺Po
A silicon film 104 is deposited inside trench portion 94.
You. The trench 94 has an inversely tapered side wall.
You. Other parts are the same as those in the twenty-second embodiment,
The description will not be repeated.

At this time, the electron injection aperture angle β in the AA ′ direction in FIG. 109 is expressed by the above-described equation (18). Electron injection aperture angle β perpendicular to AA ′ direction
Is expressed by a similar formula, except that the distance from the node N1 to the trench portion side wall changes.

The semiconductor device of the first modification of the twenty-second embodiment differs from the semiconductor device of the twenty-second embodiment in that the p-type silicon substrate 1 is connected to the n ⁺ region 90 to which an input signal is applied first.
Since the electron injection aperture angle toward 20 can be reduced, the undershoot resistance is further improved.

[Twenty-third Embodiment] FIG. 111 is a circuit diagram showing a configuration of an undershoot countermeasure element 64m in a semiconductor device of a twenty-third embodiment.

The semiconductor device of the twenty-third embodiment is shown in FIG.
The semiconductor device of the twenty-second embodiment differs from the semiconductor device of the twenty-second embodiment in that the potential of the trench portion of the undershoot countermeasure element 64l is different. That is, the potential of the trench portion is changed from the internal power supply potential Vcc to the internal boosted potential Vpp, and has a parasitic npn bipolar transistor 81 having a collector potential of the internal boosted potential Vpp instead of the parasitic npn bipolar transistor 77.

Since the other portions have the same structure as in FIG. 106, description thereof will not be repeated. In the semiconductor device of the twenty-third embodiment, the internal boosted potential Vpp is coupled to the trench portion of the undershoot countermeasure element, and the potential of the P well is the substrate potential VBB. Therefore, P at the boundary between trench portion 86 and P well 122 in FIG.
The depletion layer 256b at the N-junction extends further than when the trench is coupled to internal power supply potential Vcc. For this reason, the electron injection aperture angle can be further reduced.

Therefore, by changing the potential of the trench portion having the planar structure and the sectional structure shown in the twenty-second embodiment and the first modification of the twenty-second embodiment from internal power supply potential Vcc to internal boosted potential Vpp, further undershoot occurs. Improves resistance.

[Twenty-fourth Embodiment] FIG. 112 is a circuit diagram showing a configuration of an undershoot countermeasure element 64n in a semiconductor device of a twenty-fourth embodiment.

The semiconductor device of the twenty-fourth embodiment is similar to that of FIG.
The point that the resistor 72 is not provided in the undershoot countermeasure element 64k shown in FIG.
The other parts have the same configuration as that of FIG. 101, and therefore description thereof will not be repeated.

FIG. 113 shows a parasitic npn bipolar transistor.
It is a top view of the resistor 73c. Referring to FIG.
N corresponding to the code N1⁺The area 90 is divided into four, and each of n ⁺
Region 90 is made of a normal element such as LOCOS or shallow trench.
The semiconductor substrate is surrounded on each side by a child isolation region 82b.
It is separated from other elements above. In addition, normal element isolation
The region 82b is surrounded on all sides by a trench portion 86. So
Therefore, the region outside the trench portion 86 is
A region 82a is formed, and is connected to other elements on the semiconductor substrate.
Separate from the undershoot countermeasure element.

[0501] The trench portion 86 is formed in the normal element isolating region 82.
The depth is formed deeper than the bottom surfaces of a and 82b.

FIG. 114 is a sectional view showing a section taken along line AA ′ in FIG. 113. FIG. 114 shows Embodiment 2
Since the structure is similar to that of FIG. 103 described in FIG. 1, description thereof will not be repeated.

In this case, the electron injection aperture angle β is represented by the above-described equation (12). Further, the electron injection aperture angle in the direction perpendicular to the AA 'direction is expressed by the same equation except that the distance from the node N1 to the trench side wall changes.

In the semiconductor device of the twenty-fourth embodiment, since n ⁺ region 90 serving as an electron injection source is divided into four, the electrons injected into each n ⁺ region 90 are averaged to about one quarter. Number. Therefore, it is possible to alleviate a sudden undershoot pulse without any resistance. Further, since each n ⁺ region is surrounded by the trench portion, the electron injection opening angle with respect to each electron injection source can be reduced, so that the undershoot resistance is improved.

[Modification 1 of Embodiment 24] In Modification 1 of Embodiment 24, a parasitic npn bipolar transistor 73 has a structure shown by a parasitic npn bipolar transistor 73d described below.

FIG. 115 is a plan view of the parasitic npn bipolar transistor 73d. Referring to FIG. 115, parasitic npn bipolar transistor 73d differs from parasitic npn bipolar transistor 73c shown in FIG. 113 in having trench portion 94 instead of trench portion 86. Other configurations are the same as those in FIG. 113, and therefore description thereof will not be repeated.

FIG. 116 is a sectional view showing a section taken along line AA 'in FIG. Referring to FIG. 116, this cross-sectional structure is the same as that shown in FIG.
Since the structure is the same as that of the structure 05, the description will not be repeated.

In this case, the electron injection aperture angle β is expressed by the equation (14) described above. In addition, the electron injection aperture angle in the direction perpendicular to the AA 'direction is represented by the same formula, except that the distance from the node N1 to the trench side wall changes.

The semiconductor device of the first modification of the twenty-fourth embodiment is different from the semiconductor device of the twenty-fourth embodiment in that a p-type silicon substrate 1 is formed from n ⁺ region 90 to which an input signal is applied first.
Since the electron injection aperture angle toward 20 can be reduced, the undershoot resistance is further improved.

[Twenty-Fifth Embodiment] FIG. 117 is a circuit diagram showing a configuration of an undershoot measure element 64o in a semiconductor device of a twenty-fifth embodiment.

The semiconductor device of the twenty-fifth embodiment is similar to that of FIG.
The point that the resistor 72 of the undershoot countermeasure element 64l shown in FIG. The other configuration is the same as that of FIG. 106, and therefore description will not be repeated.

FIG. 118 shows a parasitic npn bipolar transistor.
It is a top view of the register 77c. Referring to FIG.
N corresponding to the code N1⁺The area 90 is divided into four, and each of n ⁺
Region 90 is made of a normal element such as LOCOS or shallow trench.
The child isolation region 82b surrounds each side. Further
Then, a trace is formed so as to surround the periphery of each normal element isolation region 82b.
The punch 86 is formed. Furthermore, the periphery of the trench portion 86
A normal element isolation region 82a is formed in the
With other elements formed on the semiconductor substrate
Is separated.

[0513] The trench portion 86 is formed in the normal element isolating region 82.
The depth is formed deeper than the bottom surfaces of a and 82b.

FIG. 119 is a sectional view showing a section taken along line AA ′ in FIG. 118. FIG. 119 shows Embodiment 2
Since it has the same structure as that of FIG. 108 described in FIG. 2, description thereof will not be repeated.

In this case, the electron injection aperture angle β is represented by the above-described equation (16). The electron injection aperture angle in the direction perpendicular to the AA 'direction is represented by the same equation, except that the distance from the node N1 to the trench side wall changes.

As described above, the opening angle of the electron injection can be made smaller than that of the twenty-fourth embodiment by the extent that the depletion layer is expanded, so that the undershoot resistance is improved.

Further, the depletion layer also extends from the n ⁺ region existing on the side wall of trench portion 86, and the probability of absorbing electrons injected from other places is higher than in the twenty-fourth embodiment. Improves resistance.

[Modification 1 of Embodiment 25] In Modification 1 of Embodiment 25, a parasitic npn bipolar transistor 77 has a structure indicated by a parasitic npn bipolar transistor 77d described below.

FIG. 120 is a plan view of the parasitic npn bipolar transistor 77d. Referring to FIG. 120, parasitic npn bipolar transistor 77d is different from parasitic npn bipolar transistor 77c shown in FIG. 118 in that a trench portion 94 is provided instead of trench portion 86. Other structures are the same as those in FIG. 118, and therefore description will not be repeated.

FIG. 121 is a sectional view showing a section taken along line AA ′ in FIG. Since the cross-sectional structure shown in FIG. 121 is the same as that of FIG. 110 described in the first modification of the twenty-second embodiment, description thereof will not be repeated.

In this case, the electron injection aperture angle β is expressed by the equation (18) described above. The electron injection aperture angle in the direction perpendicular to the AA 'direction is expressed by the same formula, except that the distance from the node N1 to the trench side wall changes.

The semiconductor device of the first modification of the twenty-fifth embodiment is different from the semiconductor device of the twenty-fifth embodiment in that the electron injection opening from the n ⁺ region to which an input signal is applied first to the P-type silicon substrate is provided. Since the angle can be reduced, the undershoot resistance is further improved.

[Twenty-sixth Embodiment] FIG. 122 is a circuit diagram showing a configuration of an undershoot countermeasure element 64p in a semiconductor device of a twenty-sixth embodiment.

With reference to FIG. 122, the undershoot countermeasure element 64p in the semiconductor device of the twenty-sixth embodiment has the structure
In undershoot countermeasure element 64o shown in FIG. 117, parasitic npn in which the potential of the collector becomes internal boosted potential Vpp instead of parasitic npn bipolar transistor 77
The difference is that a bipolar transistor 81 is provided. Other structures are the same as those in FIG. 117, and therefore description thereof will not be repeated.

[0525] In the semiconductor device of the twenty-sixth embodiment, the internal boosted potential Vpp is applied to the trench portion of the undershoot prevention element.
Are connected, and the potential of the P well is the substrate potential VBB. Therefore, depletion layer 256b at the PN junction at the boundary between the trench and the P well further expands when the trench is coupled to internal power supply potential Vcc. For this reason, the electron injection aperture angle can be further reduced.

Therefore, by changing the potential of the trench portion having the planar structure and the cross-sectional structure shown in the twenty-fifth embodiment and the first modification of the twenty-fifth embodiment from internal power supply potential Vcc to internal boosted potential Vpp, the undervoltage is further reduced. Improves shoot resistance.

As described above, in the embodiments 24 to 26, the n ⁺ region serving as an electron injection source is divided into four parts. However, at least one n ⁺ region is sufficient. As the number of divisions n (n is a natural number) increases, the number of electrons injected from each of the n ⁺ regions is averaged to about 1 / n, and the undershoot resistance is improved. This is because the number of electrons injected varies depending on the connection between the n ⁺ region and the metal wiring.

The structure of the undershoot countermeasure element described in the first to twenty-sixth embodiments has been described in connection with the P well in contact with the n ⁺ region serving as an electron injection source and serious data destruction and circuit malfunction due to electron injection. The present invention can be applied to all well structures in which a P-well in which a semiconductor element having the following structure is present is connected with a silicon layer (including a substrate) of the same conductivity type.

[Twenty-Seventh Embodiment] FIG. 123 is a circuit diagram of an undershoot countermeasure element used in a semiconductor device of a twenty-seventh embodiment.

The undershoot countermeasure element comprises a resistor 2 connected between input node Vin and output node N2.
92, a drain connected to the node N2, a gate, a source and a potential of the substrate portion set to the ground potential Vss.
And a channel transistor 294.

However, the drain of N channel transistor 294, which is the n ⁺ region to which node N2 is connected, is not on the silicon substrate. The resistor 292 is not a diffusion resistor formed on a silicon substrate, but a polysilicon resistor or the like.

FIG. 124 is a sectional view of the N-channel transistor 294 shown in FIG.

Referring to FIG. 124, a silicon substrate 308
An insulating film 306 is formed thereon, and a gate electrode 304 and a gate oxide film 302 of the N-channel transistor 294 are further formed thereon. Further, on the insulating film 306, an n ⁺ region 2 serving as a drain to which the node N2 is connected is provided.
96, the n ⁺ region 300 and the n ⁺ region 29 which are the source
A p-type region 298 sandwiched between 6,300 is formed.
P-type region 298, n ⁺ region 300 and gate electrode 30
4 is connected to a ground potential.

The structure shown in FIG. 124 is based on SOI (Silicon
On Insulator) structure. A transistor formed with this SOI structure is hereinafter referred to as an SOI transistor.

The N-channel SOI transistor has a partially depleted transistor in which a P-type body region, which is a region where a channel is formed, is depleted only at a surface near a gate oxide film.
There is a fully depleted transistor in which all the P-type body regions are depleted.

The partially depleted transistor can perform threshold control similarly to an N-channel transistor (hereinafter referred to as a bulk transistor) formed on a P-type silicon substrate, and can have an off breakdown voltage equivalent to that of a bulk transistor. it can.

On the other hand, the fully depleted transistor has an SOI
Even if the potential of the P-type body region is not fixed by reducing the thickness of the layer, the same kink-free IV characteristics as those of the bulk transistor can be obtained. However, the off breakdown voltage is lower than that of a bulk transistor.

[0538] Further, this SOI transistor can be formed later after a desired transistor or another device is manufactured by utilizing a bonding technique.

In the twenty-seventh embodiment, a partially depleted transistor is used. Referring to FIG. 124 again, N-channel transistor 294 is off when a positive potential is applied to node N2. Also, n ⁺ region 296
The non-conductive state is maintained until the reverse breakdown voltage of the PN junction at the boundary between the P-type region and the P-type region 298 is exceeded. The N-channel transistor 294 can withstand the overshoot up to the reverse breakdown voltage of the PN junction.

When a negative potential is applied to node N2 of N-channel transistor 294, p-type region 298
Is at the ground potential Vss, a forward current flows through the PN junction at the boundary between the n ⁺ region 296 and the p-type region 298.
Since the electrons flow to the ss side, injection of electrons into the silicon substrate 308 does not occur.

[0541] Therefore, an operation failure due to an undershoot in an input signal to the semiconductor device is unlikely to occur, which is very effective in stabilizing the operation of the semiconductor device.

In FIG. 124, although the ground potential Vss is coupled to the gate electrode 304, a structure in which the potential of the gate electrode 304 is fixed to a negative potential has the same effect.

The structure shown in FIG. 124 can also be realized by using a polysilicon TFT (Thin Film Transistor). Although this TFT has no current driving capability, it is still sufficient for use as an undershoot countermeasure element.

[0544] The operation is the same as that of the SOI transistor, and injection of electrons into the silicon substrate does not occur. Therefore, even if an undershoot occurs on the input signal, an operation failure is unlikely to occur, which is very effective in stabilizing the operation.

In the undershoot countermeasure element of the twenty-seventh embodiment, the negative potential of the undershoot of the input signal is not applied to the silicon substrate. Ground potential Vs
s.

In a deep submicron device, the wiring capacitance is larger than the PN junction capacitance of a transistor or the like. In addition, a transistor in which the potential of the P-type silicon substrate is set to the ground potential Vss can lower the threshold value.
It is very effective for low-voltage devices of the V system or later. The undershoot countermeasure element of the twenty-seventh embodiment is very effective as a low-voltage device because the substrate potential of the transistor in the peripheral circuit can be easily set to the ground potential Vss, and the threshold value of the transistor can be reduced.

[Twenty-eighth Embodiment] FIG. 125 is a circuit diagram of an undershoot countermeasure element according to a twenty-eighth embodiment.

Referring to FIG. 125, the undershoot countermeasure element in the semiconductor device of the twenty-eighth embodiment differs from the undershoot countermeasure element of the twenty-seventh embodiment shown in FIG. 123 in that an N-channel transistor is used instead of N-channel transistor 294. The difference is that a transistor 294a is provided.
Since the potential of the substrate of the N-channel transistor 294a is floating, the N-channel transistor 2
Different from 94.

FIG. 126 is a cross sectional view showing a cross section of N channel transistor 294a in FIG.

Referring to FIG. 126, N in Embodiment 28
Channel transistor 294a is different in that p-type region 298 of n-channel transistor 294 shown in FIG. 124 of the twenty-seventh embodiment is not coupled to the ground potential and is floating.

The other portions have the same structure as the cross sectional view shown in FIG. 124, and therefore the description will not be repeated. The structure shown in FIG. 126 can be made with an SOI structure.

A partially depleted SOI transistor in which the P-type body region is in a floating state cannot be used as a 5V semiconductor device because of its low off-state breakdown voltage, but can be used as a 3V device. A fully depleted transistor can be used for a semiconductor device having a power supply voltage lower than the 3 V system.

Now, this transistor is connected to node N2
It is in a non-conductive state when a potential is applied. This place
The P-type body region is floating
Where n ⁺PN at the boundary between region 296 and p-type region 298
The junction does not go forward.

Therefore, this transistor can withstand the overshoot up to the off breakdown voltage of this transistor. Although the off-state breakdown voltage changes depending on the gate length, the off-state breakdown voltage of the N-channel SOI transistor when the gate length is 0.6 μm is about 5 V.

On the other hand, the N-channel transistor 294
When a negative voltage is applied to the node N2 of a, a voltage is applied between the n ⁺ region 296 of the node N2 and the gate electrode 304.

When the absolute value of the negative potential further increases, a voltage higher than the threshold is applied and N-channel transistor 29
4a becomes conductive.

At this time, electrons are supplied to n ⁺ region 2 of node N2.
Since electrons flow from 96 to the ground node coupled to n ⁺ region 300, no electrons are injected into P-type silicon substrate 308.

Therefore, no malfunction occurs due to the application of undershoot, which is very effective.

In FIG. 126, although the ground potential Vss is coupled to the gate electrode 304, a structure in which the potential of the gate electrode 304 is fixed to a negative potential has the same effect.

The structure shown in FIG. 126 can also be realized by using a polysilicon TFT. The operation is S
As in the case of the OI transistor, injection of electrons into the P-type silicon substrate does not occur. Therefore, even if an undershoot occurs on the input signal, an operation failure is unlikely to occur, which is very effective in stabilizing the operation.

[Twenty-Ninth Embodiment] FIG. 127 is a circuit diagram of an undershoot countermeasure element in a semiconductor device of a twenty-ninth embodiment.

Referring to FIG. 127, the undershoot countermeasure element of the twenty-ninth embodiment has a resistance 312 connected between input node Vin and node N3, a gate coupled to ground potential, and a source connected to node N3. N-channel transistor 316 and N-channel transistor 3
16 and a resistor 314 connected between the drain and the node supplied with the internal power supply potential Vcc. However, the N-channel transistor 3 connected to the node N3
16 n ⁺ region is a source region of a no n ⁺ region on the silicon substrate.

The resistors 312 and 314 are not diffused resistors formed on a silicon substrate but may be polysilicon resistors or the like.

[0564] N-channel transistor 316 is an SOI transistor. Transistors in which the potential of the P-type body region is floating among the partially depleted transistors cannot be used as a 5V semiconductor device because they have a low off-state breakdown voltage, but can be used as a 3V device. A fully depleted transistor can be used for a semiconductor device having a lower power supply voltage of the 3V system.

This transistor is non-conductive when a positive potential is applied to the node N3. Since the P-type body region is floating, the node N
The PN junction at the boundary between the n ⁺ region of the source portion to which the transistor 3 is connected and the P-type body region does not become forward. Therefore, even if an overshoot up to the off breakdown voltage of this transistor is applied to node N3, it can withstand.

The off-breakdown voltage varies depending on the gate length. When the gate length is 0.6 μm, the off-breakdown voltage of the N-channel SOI transistor is about 5 V. On the other hand, when a negative voltage is applied to the node N3 of this transistor, the node N3
A voltage is applied between the n ⁺ region of the source portion connected to the gate electrode and the gate electrode. When the absolute value of the negative potential further increases, N
A voltage higher than the threshold value of the channel transistor 316 is applied, and the N-channel transistor 316 is turned on.
At this time, electrons enter the P-type body region of N-channel transistor 316 from the n ⁺ region connected to node N3, and are absorbed by the drain portion of N-channel transistor 316 coupled to internal power supply potential Vcc.

At this time, since the resistors 312 and 314 are provided, the current does not suddenly flow through the N-channel transistor 316, and the N-channel transistor 316 immediately becomes non-conductive when no undershoot is applied. Return.

As described above, in the twenty-ninth embodiment, the resistance 3
12 and 314 do not use a diffusion resistor formed on a silicon substrate.
Since the semiconductor device does not have a diffusion region formed on the substrate, no electrons are injected into the P-type silicon substrate, and even if an undershoot is applied to an input signal, a malfunction does not easily occur. Very effective for stabilization. The undershoot countermeasure element according to the twenty-ninth embodiment can also be configured using a polysilicon TFT.

The operation is the same as that of the SOI transistor, and injection of electrons into the silicon substrate does not occur. Therefore, even if an undershoot occurs on the input signal, an operation failure is unlikely to occur, which is very effective in stabilizing the operation.

[Embodiment 30] FIG. 128 is a circuit diagram of an undershoot countermeasure element used in a semiconductor device of an embodiment 30.

Referring to FIG. 128, the undershoot countermeasure element in the thirtieth embodiment differs from the undershoot countermeasure element in the twenty-ninth embodiment shown in FIG. 127 in having an N-channel transistor 317 instead of N-channel transistor 316. Are different in that

[0572] The N-channel transistor 317 shown in FIG.
7 is different from the N-channel transistor 316 shown in FIG. 7 in that the P-type region between the drain and the source is fixed to the ground potential Vss.

[0573] As the N-channel transistor 317, SO
An I transistor can be used. N-channel transistor 317 is off when a positive potential is applied to node N3.

The N-channel transistor 317 remains in the non-conductive state until the applied potential exceeds the reverse breakdown voltage of the PN junction at the boundary between the N ⁺ region and the P-type body region connected to the node N3 of the N-channel transistor 317. Hold. N-channel transistor 317 can withstand the overshoot up to the reverse breakdown voltage of the PN junction.

When a negative potential is applied to node N3, the P-type body region is at ground potential Vss, so that the boundary between the n ⁺ diffusion region to which node N3 is connected and the P-type body region is connected. The forward current flows because the bias applied to the PN junction becomes forward, but flows directly to the node to which the ground potential Vss is connected without passing through the P-type silicon substrate. Does not occur.

In the twenty-seventh embodiment, the depletion layer extends toward the n ⁺ region and P-type body region of N-channel transistor 317 coupled to internal power supply potential Vcc and resistor 314 to absorb the injected electrons. The electrons are absorbed earlier than the undershoot countermeasure element, and the N-channel transistor 317 is quickly turned off.

[0577] Therefore, when an undershoot is applied to an input signal to the semiconductor device, an operation failure hardly occurs, which is very effective in stabilizing the operation of the semiconductor device.

This N-channel transistor 317 can also be constituted by a polysilicon TFT. The operation is similar to that of the SOI transistor, and injection of electrons into the P-type silicon substrate does not occur. Therefore, even when the undershoot is applied to the input signal, an operation failure is unlikely to occur, which is very effective in stabilizing the operation.

[Thirty-First Embodiment] FIG. 129 is a circuit diagram of an undershoot countermeasure element used in a semiconductor device of a thirty-first embodiment.

This undershoot countermeasure element includes a resistor 31 connected between input node Vin and node NP2.
8 and a P-channel transistor 320 whose gate and source are connected to node NP2 and whose drain is coupled to ground potential.

[0583] The N-type region between the drain and source of P-channel transistor 320 is coupled to internal power supply potential Vcc, and the p ⁺ region of P-channel transistor 320 connected to node NP2 is located on the silicon substrate. There is no p ⁺ region. The resistor 318 is not a diffusion resistor formed on a silicon substrate but a polysilicon resistor or the like.

FIG. 130 is a sectional view of the P-channel transistor 320 shown in FIG.

Referring to FIG. 130, silicon substrate 334
An insulating film 332 is formed thereon, and a gate electrode 330 and a gate oxide film 328 of the P-channel transistor 320 are further formed thereon. Further, an N-type body region is formed on insulating film 332 above gate electrode 330 with a gate oxide film 328 therebetween.
On both sides of 24, p ⁺ regions 322 and 326 are formed. Gate electrode 330 and p ⁺ region 322 are connected to node NP2, N type body region 324 is coupled to internal power supply potential Vcc, and p ⁺ region 326 is coupled to ground potential Vss.

In the P-channel SOI transistor, the gate electrode is formed of p ⁺ polysilicon, and the gate electrode is formed of n ⁺
It may be formed of polysilicon. In the case of the p ⁺ polysilicon gate electrode, similarly to the N-channel SOI transistor, a partially depleted transistor in which the N-type body region is depleted only on the surface near the surface gate oxide film, and a complete depletion in which the N-type body region is completely depleted Transistor.

However, even with a partially depleted transistor, a P-channel SOI transistor can provide IV characteristics without kink.

On the other hand, in the case of an n ⁺ polysilicon gate electrode, it becomes the same as the buried channel of the bulk transistor. In this case, a channel is easily formed.

When a positive potential is applied to node NP2, the potential of p ⁺ region 322 of P channel transistor 320, which is a partially depleted transistor, is changed to the internal power supply potential V
It is in a non-conductive state up to cc. When the potential of p ⁺ region 322 exceeds internal power supply potential Vcc, p ⁺ region 322
The potential difference applied to the PN junction at the boundary between the N-type body region 324 and the N-type body region 324 becomes forward, and a current flows to a node coupled to the internal power supply potential Vcc connected to the N-type body region 324.

Also, holes are absorbed in p ⁺ region 326 to which ground potential Vss is coupled. in this case,
Since the current is suppressed by the resistor 318 shown in FIG. 129, a large current does not flow into the node NP2 even if the input signal has an overshoot having a peak potential higher than the internal power supply potential Vcc. Therefore, there is no problem because the P-channel transistor 320 is not destroyed.

In order to reduce the current density at this time, it is possible to cope with this by increasing the transistor width of the P-channel transistor 320.

On the other hand, when a negative potential is applied to node NP2 and a potential equal to or lower than the threshold value of P-channel transistor 320 is applied, P-channel transistor 320 is rendered conductive and connected to p ⁺ region 326. The current flows to the node supplied with the ground potential Vss.

Also, even if a negative potential having a larger absolute value is applied, p ⁺ region 322 and N type body region 324 are always maintained.
And the potential difference applied to the PN junction between the PN junction and the PN junction is in the opposite direction.
Reference numeral 20 performs a transistor operation.

Therefore, even if the undershoot potential applied to the input signal exceeds the breakdown voltage of the PN junction, the ground potential V
Electrons escape to the p ⁺ region 326 coupled to ss, and no electrons are injected into the P-type silicon substrate.

[0593] Therefore, when an undershoot occurs in an input signal to the semiconductor device, an operation failure hardly occurs, which is very effective in stabilizing the operation of the semiconductor device.

The structure shown in FIG. 130 can also be realized by using a polysilicon TFT.

The operation is the same as that of the SOI transistor, and no electron is injected into the P-type silicon substrate.

Therefore, even if an undershoot occurs on an input signal, an operation failure is unlikely to occur, which is very effective in stabilizing the operation.

[Thirty-second Embodiment] FIG. 131 is a circuit diagram of an undershoot countermeasure element used in a semiconductor device of a thirty-second embodiment.

Referring to FIG. 131, the undershoot preventing element includes a P-channel transistor 320a instead of P-channel transistor 320 of the undershoot preventing element of the thirty-first embodiment. P-channel transistor 320a differs from that of the thirty-first embodiment in that the N-type body region is floating.

FIG. 132 is a cross sectional view showing a cross section of P channel transistor 320a shown in FIG.

Referring to FIG. 132, a P-channel transistor 3 used in the semiconductor device of the thirty-second embodiment
20a indicates that the N-type body region 324 has the internal power supply potential Vcc.
This embodiment is different from the thirty-first embodiment in that it is floating instead of being connected to Other structures are the same as the cross-sectional structure shown in FIG. 130, and therefore description thereof will not be repeated.

The structure shown in FIG. 132 can be formed by an SOI structure. Of the SOI transistors, partially depleted transistors having an N-type body region floating have a low off-state breakdown voltage, and thus cannot be used as a 5V semiconductor device but can be used as a 3V device. A fully depleted transistor can be used for a semiconductor device having a power supply voltage lower than 3 V.

P-channel transistor 320a is non-conductive when a positive potential is applied to node NP2, and the potential applied to internal power supply potential Vcc as in the case shown in FIG. There is no such restriction.

This is because the N-type body region 324 is floating, so that a forward potential difference is not applied to the PN junction at the boundary between the p ⁺ region 322 and the N-type body region 324.

Therefore, P-channel transistor 32
An input voltage up to the off breakdown voltage of 0a can be handled.

The off-breakdown voltage varies depending on the gate length. In a P-channel SOI transistor having a gate length of 0.6 μm, the off-breakdown voltage is about 5 V.

On the other hand, when a negative potential is applied to node NP2 and a potential lower than the threshold value of P-channel transistor 320a is applied, P-channel transistor 320
a becomes conductive, and electrons escape toward the p ⁺ region to which the ground potential Vss is coupled.

Even if a negative potential having a larger absolute value is applied, a voltage higher than the reverse breakdown voltage is not applied to the PN junction at the boundary between p ⁺ region 322 and N-type body region 324, and P-channel transistor 320a Operates as a transistor.

The P-channel transistor 320a operates as an undershoot within a range where the gate oxide film 328 does not break down, and electrons are not injected into the silicon substrate. Therefore, an operation failure when an undershoot is applied to an input signal to the semiconductor device hardly occurs, which is very effective in stabilizing the operation of the semiconductor device.

The structure shown in FIG. 132 can also be realized by using a polysilicon TFT.

The operation is the same as that of the SOI transistor, and injection of electrons into the silicon substrate does not occur. Therefore, even if an undershoot occurs on the input signal, an operation failure is unlikely to occur, which is very effective in stabilizing the operation.

[Thirty-third Embodiment] FIG. 133 is a block diagram of an input protection circuit in a semiconductor device according to a thirty-third embodiment.

An input buffer used in the semiconductor device of the thirty-third embodiment has a terminal 34 for receiving an external signal.
2 and a node N11 which is an internal node for transmitting a signal externally input from the terminal 342 to the terminal 342 to the inside.
And an undershoot countermeasure element 344 connected between nodes N11 and N12, and an inverter 348 connected to the input of node N12. This input buffer is further connected to node N11 and connected to node N11.
Anti-surge device 34 that absorbs positive surge applied to
6 inclusive. An output of the inverter 348 becomes an output signal IOUT to an internal block of the semiconductor device.

This input buffer differs from the input buffer 10 in the first embodiment described with reference to FIG. 2 in the position where the positive surge suppression element is connected. The positive surge suppression element is connected to a node transmitting a signal from the input terminal to the undershoot prevention element, and is not connected to a node transmitting a signal from the undershoot prevention element to the inverter. The undershoot countermeasure element described in the first to thirty-second embodiments described above is different from the undershoot countermeasure element 344.
All can be used as.

In this configuration, since the positive surge suppression element absorbs the positive surge input to the external terminal, no positive surge is applied to the undershoot prevention element. Therefore, it is necessary to consider the resistance of the undershoot prevention element to the positive surge. There is no.

Here, the anti-surge element is for protecting internal elements such as the inverter 348 when a surge in the positive direction due to static electricity is mainly applied. The anti-shooting element is input to the input terminal. The main purpose is to prevent the internal circuit from malfunctioning when an undershoot occurs on the signal to be performed.

Although the inverter has been described here, other types of input buffers such as a reference voltage comparison type input buffer may be used.

Therefore, with the configuration shown in FIG. 133, the size of the undershoot countermeasure element using the P-channel transistor can be determined only by the undershoot countermeasure, thereby facilitating the design.

That is, it is not necessary to increase the resistance for suppressing the current due to overshoot, and it is not necessary to take measures to reduce the current density by increasing the size of the transistor. It becomes possible to.

Therefore, the chip size of the semiconductor device can be reduced, which is advantageous in terms of cost.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0621]

According to the semiconductor device of the present invention, a trench is provided on the side of the impurity region into which electrons are injected, and the migration of electrons is hindered by the side wall. Can be reduced, and the undershoot resistance is improved.

According to the semiconductor device of the fifth and sixth aspects, in addition to the effect of the semiconductor device of the first aspect, a potential in a positive direction is applied to the impurity region provided on the trench side wall. A depletion layer extends at the boundary between the provided impurity region and the well. The electrons are further captured by the depletion layer, and the electron injection aperture angle is further reduced, so that the undershoot resistance is further improved.

The semiconductor device according to any one of claims 7 to 9 has the following advantages. In addition to the effects of the semiconductor device according to claim 1, by changing the shape of the trench portion, the opening angle of electron injection is further reduced. Shoot resistance is further improved.

[0624] The semiconductor device according to the tenth to twelfth aspects,
In addition to the effect of the semiconductor device according to the first aspect, the region sandwiched by the trench portions can be narrowed, and the opening angle of electron injection can be further reduced, so that the undershoot resistance is further improved.

[0625] The semiconductor device according to claims 13 and 14 is
In addition to the effects achieved by the semiconductor device according to claim 10,
In order to apply a positive potential to the impurity region provided on the trench sidewall, a depletion layer extends at the boundary between the impurity region provided on the trench sidewall and the well. The electrons are further captured by the depletion layer, and the electron injection aperture angle is further reduced, so that the undershoot resistance is further improved.

[0626] In the semiconductor device according to the fifteenth and sixteenth aspects,
In addition to the effects achieved by the semiconductor device according to claim 10,
By changing the shape of the trench portion, the electron injection opening angle is further narrowed, so that the undershoot resistance is further improved.

[0627] The semiconductor device according to the seventeenth to nineteenth aspects,
In addition to the effect of the semiconductor device according to the first aspect, the region sandwiched by the trench portions can be narrowed, and the opening angle of electron injection can be further reduced, so that the undershoot resistance is further improved.

[0628] The semiconductor device according to the twentieth and twenty-first aspects,
In addition to the effects achieved by the semiconductor device according to claim 17,
In order to apply a positive potential to the impurity region provided on the trench sidewall, a depletion layer extends at the boundary between the impurity region provided on the trench sidewall and the well. The electrons are further captured by the depletion layer, and the electron injection aperture angle is further reduced, so that the undershoot resistance is further improved.

The semiconductor device according to the twenty-second to twenty-fourth aspects,
In addition to the effects achieved by the semiconductor device according to claim 17,
By changing the shape of the trench portion, the electron injection opening angle is further narrowed, so that the undershoot resistance is further improved.

The semiconductor device according to the twenty-fifth aspect has, in addition to the effect of the semiconductor device according to the first aspect, the current absorbed by the undershoot countermeasure element is limited, so that thermal destruction is less likely to occur, and the undershoot countermeasure is prevented. The region sandwiched between the trench portions of the element can be narrowed, and the opening angle of electron injection can be further reduced, so that the undershoot resistance is further improved.

The semiconductor device according to the twenty-sixth aspect has, in addition to the effect of the semiconductor device according to the first aspect, a destruction of the semiconductor device when a positive surge is applied since it has a positive surge protection element. Can be.

[0632] The semiconductor device according to the twenty-seventh to twenty-ninth aspects,
Since there is an undershoot countermeasure element separated by a silicon substrate and an oxide film, electrons are not injected into the silicon substrate, and operation failure when an undershoot is applied to an input signal to a semiconductor device is unlikely to occur. This is very effective in stabilizing the operation of the semiconductor device.

The semiconductor device according to claim 30 can be used even when the power supply voltage is high because the channel formation region is set to the internal power supply potential, in addition to the effect of the semiconductor device according to claim 27.

The semiconductor device according to claim 31 to 33,
Since there is an undershoot countermeasure element separated by a silicon substrate and an oxide film, electrons are not injected into the silicon substrate, and operation failure when an undershoot is applied to an input signal to a semiconductor device is unlikely to occur. This is very effective in stabilizing the operation of the semiconductor device.

[0635] The semiconductor device according to claim 34, 35,
Since there is an undershoot countermeasure element separated by a silicon substrate and an oxide film, electrons are not injected into the silicon substrate, and operation failure when an undershoot is applied to an input signal to a semiconductor device is unlikely to occur. This is very effective in stabilizing the operation of the semiconductor device.

[0636] In the semiconductor device according to the thirty-sixth aspect, in addition to the effect of the semiconductor device according to the thirty-fourth aspect, since the channel formation region is set to the ground potential, the injected electrons are absorbed quickly by the function of the depletion layer. Therefore, electrons are not injected into the silicon substrate, and an operation failure when an undershoot is applied to an input signal to the semiconductor device hardly occurs, which is very effective in stabilizing the operation of the semiconductor device. .

The semiconductor device according to claim 37, 38,
In addition to the effects achieved by the semiconductor device according to claim 27,
Since the device has a positive surge countermeasure element, it is possible to prevent the semiconductor device from being destroyed when a positive surge is applied.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram illustrating a configuration of a semiconductor device 1 according to a first embodiment.

FIG. 2 is a block diagram for describing a configuration of an input buffer 10 in FIG.

FIG. 3 is a circuit diagram showing an example of a positive surge suppression element 66 in FIG.

4 is an undershoot countermeasure element 64 in FIG.
FIG. 3 is a circuit diagram showing the configuration of FIG.

FIG. 5 is a plan view of an N-channel transistor 74a according to the first embodiment.

FIG. 6 is a cross-sectional view showing a cross-sectional structure taken along line AA ′ of FIG. 5;

FIG. 7 is a sectional view showing a first step of forming the structure of FIG. 6;

FIG. 8 is a sectional view showing a second step of forming the structure of FIG. 6;

FIG. 9 is a sectional view showing a third step of forming the structure of FIG. 6;

FIG. 10 is a sectional view showing a fourth step of forming the structure of FIG. 6;

FIG. 11 is a sectional view showing a fifth step of forming the structure of FIG. 6;

FIG. 12 is a sectional view showing a sixth step for forming the structure of FIG. 6;

FIG. 13 is a sectional view showing a seventh step for forming the structure of FIG. 6;

FIG. 14 is a cross-sectional view showing a first step of forming a trench portion in the LOCOS isolation structure.

FIG. 15 is a cross-sectional view showing a second step of forming a trench portion in the LOCOS isolation structure.

FIG. 16 is a plan view of an N-channel transistor 74b in the semiconductor device of the second embodiment.

FIG. 17 is a sectional view showing an AA ′ section in FIG. 16;

FIG. 18 is a cross-sectional view showing a first step of forming the structure shown in FIG.

FIG. 19 is a sectional view illustrating a second step of forming the structure illustrated in FIG. 17;

20 is a cross-sectional view showing a third step of forming the structure shown in FIG.

FIG. 21 is a sectional view showing a fourth step of forming the structure shown in FIG. 17;

FIG. 22 is a sectional view showing a fifth step of forming the structure shown in FIG. 17;

FIG. 23 is a sectional view illustrating a sixth step of forming the structure illustrated in FIG. 17;

FIG. 24 is a cross-sectional view showing a seventh step for forming the structure shown in FIG. 17;

FIG. 25 is a plan view of an N-channel transistor 74c in the semiconductor device of the third embodiment.

26 is a cross-sectional view showing a cross-sectional structure taken along line AA ′ of FIG.

FIG. 27 is a plan view of an N-channel transistor 74d according to a first modification of the third embodiment.

28 is a cross-sectional view showing a cross-sectional structure taken along line AA ′ of FIG. 27.

FIG. 29 is a plan view of an N-channel transistor 74e in the semiconductor device of the fourth embodiment.

30 is a sectional view showing a structure of a section taken along line BB ′ of FIG. 29;

FIG. 31 is a sectional view showing an AA ′ section in FIG. 29;

FIG. 32 is a plan view of an N-channel transistor 74f in the semiconductor device of the fifth embodiment.

FIG. 33 is a sectional view showing a BB ′ section in FIG. 32;

FIG. 34 is a sectional view showing a section taken along the line AA ′ in FIG. 32;

FIG. 35 is a plan view of an N-channel transistor 74g in the semiconductor device of the sixth embodiment.

FIG. 36 is a cross-sectional view showing a BB ′ cross section in FIG. 35;

FIG. 37 is a sectional view showing an AA ′ section in FIG. 35;

FIG. 38 is a plan view of an N-channel transistor 74h in a semiconductor device according to a first modification of the sixth embodiment.

FIG. 39 is a cross-sectional view showing a BB ′ cross section in FIG. 38;

40 is a sectional view showing a section taken along the line AA ′ in FIG. 38.

FIG. 41 is a circuit diagram showing an undershoot countermeasure element in the semiconductor device of the seventh embodiment.

FIG. 42 is a plan view of an N-channel transistor 252a according to the seventh embodiment.

FIG. 43 is a sectional view showing a section taken along AA ′ in FIG. 42;

FIG. 44 is a plan view of an N-channel transistor 252b according to a first modification of the seventh embodiment.

FIG. 45 is a sectional view showing a section taken along the line AA ′ in FIG. 44;

FIG. 46 is a plan view of an N-channel transistor 252c in the semiconductor device of the eighth embodiment.

FIG. 47 is a sectional view showing a section taken along the line AA ′ in FIG. 46;

FIG. 48 is a plan view showing a planar structure of an N-channel transistor 252d in the semiconductor device of Modification 1 of Embodiment 8.

FIG. 49 is a sectional view showing a section taken along line AA ′ in FIG. 48;

FIG. 50 is a plan view showing a planar structure of an N-channel transistor 252e in the semiconductor device of the ninth embodiment.

FIG. 51 is a sectional view showing a BB ′ section in FIG. 50;

FIG. 52 is a sectional view showing a section taken along the line AA ′ in FIG. 50;

FIG. 53 is a plan view showing a planar structure of an N-channel transistor 252f in the semiconductor device of Modification 1 of Embodiment 9;

FIG. 54 is a sectional view showing a section taken along line BB ′ in FIG. 53;

FIG. 55 is a sectional view showing an AA ′ section in FIG. 53;

FIG. 56 is a plan view of an N-channel transistor 252g in the semiconductor device of the tenth embodiment.

FIG. 57 is a sectional view showing a BB ′ section in FIG. 56;

FIG. 58 is a sectional view showing a section taken along the line AA ′ in FIG. 56;

FIG. 59 is a plan view showing a planar structure of an N-channel transistor 252h in a semiconductor device of Modification 1 of Embodiment 10.

FIG. 60 is a cross-sectional view showing a BB ′ cross section in FIG. 59.

FIG. 61 is a sectional view showing a section taken along the line AA ′ in FIG. 59;

FIG. 62 is a circuit diagram of an undershoot countermeasure element in the semiconductor device of the eleventh embodiment.

FIG. 63 is a circuit diagram of an undershoot countermeasure element in the semiconductor device of the twelfth embodiment.

FIG. 64 is a circuit diagram of an undershoot countermeasure element in the semiconductor device of the thirteenth embodiment.

65. N-channel transistor 7 in FIG. 64
FIG. 21 is a plan view of an N-channel transistor 74k which is a structural example of No. 4.

FIG. 66 is a cross sectional view showing a cross sectional structure taken along line AA ′ of FIG. 65.

FIG. 67 is a cross-sectional view showing a structure of a cross section taken along line BB ′ of FIG. 65;

FIG. 68 is a cross-sectional view showing a first step of forming the structure shown in FIG. 17;

FIG. 69 is a cross-sectional view showing a second step of forming the structure shown in FIG. 17;

FIG. 70 is a sectional view showing a third step of forming the structure shown in FIG. 17;

FIG. 71 is a cross-sectional view showing a fourth step of forming the structure shown in FIG. 17;

FIG. 72 is a sectional view showing a fifth step of forming the structure shown in FIG. 17;

FIG. 73 is a plan view of an N-channel transistor 74l in a semiconductor device according to a first modification of the thirteenth embodiment;

FIG. 74 is a cross-sectional view showing a structure taken along the line AA ′ of FIG. 73.

FIG. 75 is a cross-sectional view showing a structure of a BB ′ cross-section in FIG. 73;

FIG. 76 is a circuit diagram showing an undershoot countermeasure element in the semiconductor device of the fourteenth embodiment.

FIG. 77 is a plan view of an N-channel transistor 75a.

FIG. 78 is a cross-sectional view showing a cross section along AA ′ in FIG. 77;

FIG. 79 is a cross-sectional view showing a cross section taken along line BB ′ in FIG. 77;

FIG. 80 is a plan view of an N-channel transistor 75b.

FIG. 81 is a cross-sectional view showing a cross section taken along AA ′ in FIG. 80.

FIG. 82 is a sectional view showing a section taken along line BB ′ in FIG. 80;

FIG. 83 is a circuit diagram showing an undershoot measure element 64e in the semiconductor device of the fifteenth embodiment.

FIG. 84 is a plan view of an N-channel transistor 74m.

FIG. 85 is a cross-sectional view showing a cross section taken along AA ′ in FIG. 84.

86 is a sectional view showing a section taken along line BB ′ in FIG. 84.

FIG. 87 is a plan view of an N-channel transistor 74n.

FIG. 88 is a cross-sectional view showing a cross section taken along AA ′ in FIG. 87.

FIG. 89 is a sectional view showing a section taken along line BB ′ in FIG. 87;

FIG. 90 is a circuit diagram showing an undershoot measure element 64f in the semiconductor device of the sixteenth embodiment.

FIG. 91 is a plan view of an N-channel transistor 75c.

FIG. 92 is a cross-sectional view showing a cross section taken along AA ′ in FIG. 91.

93 is a sectional view showing a section taken along line BB ′ in FIG. 91.

FIG. 94 is a plan view of an N-channel transistor 75d.

FIG. 95 is a cross-sectional view showing a cross section taken along AA ′ in FIG. 94.

FIG. 96 is a cross-sectional view showing a cross section taken along line BB ′ in FIG. 94;

FIG. 97 is a circuit diagram showing a configuration of an undershoot measure element 64g in the semiconductor device of the seventeenth embodiment.

FIG. 98 is a circuit diagram showing a configuration of an undershoot measure element 64h in the semiconductor device of the eighteenth embodiment.

FIG. 99 is a circuit diagram showing a configuration of an undershoot countermeasure element 64i in the semiconductor device of the nineteenth embodiment.

FIG. 100 is a circuit diagram showing a configuration of an undershoot measure element 64j in the semiconductor device of the twentieth embodiment.

FIG. 101 is a circuit diagram showing a configuration of an undershoot measure element 64k in a semiconductor device of a twenty-first embodiment.

FIG. 102: Parasitic npn bipolar transistor 73
It is a top view of a.

FIG. 103 is a cross-sectional view showing a cross section taken along AA ′ in FIG. 102;

FIG. 104: parasitic npn bipolar transistor 73
It is a top view of b.

FIG. 105 is a sectional view showing a section taken along AA ′ in FIG. 104;

FIG. 106 is a circuit diagram showing a configuration of an undershoot measure element 64l in the semiconductor device of the twenty-second embodiment.

FIG. 107 shows a parasitic npn bipolar transistor 77
It is a top view of a.

FIG. 108 is a cross-sectional view showing a cross section taken along AA ′ in FIG. 107.

FIG. 109 shows a parasitic npn bipolar transistor 77
It is a top view of b.

110 is a sectional view showing a section taken along AA ′ in FIG. 109.

FIG. 111 is a circuit diagram showing a configuration of an undershoot countermeasure element 64m in the semiconductor device of Embodiment 23.

FIG. 112 is a circuit diagram showing a configuration of an undershoot countermeasure element 64n in the semiconductor device of the twenty-fourth embodiment.

FIG. 113: Parasitic npn bipolar transistor 73
It is a top view of c.

FIG. 114 is a cross-sectional view showing a cross section taken along AA ′ in FIG. 113.

FIG. 115 shows a parasitic npn bipolar transistor 73
It is a top view of d.

FIG. 116 is a cross-sectional view showing a cross section taken along the line AA ′ in FIG. 115.

FIG. 117 is a circuit diagram showing a configuration of an undershoot measure element 64o in the semiconductor device of the twenty-fifth embodiment.

FIG. 118 shows a parasitic npn bipolar transistor 77
It is a top view of c.

119 is a cross-sectional view showing a cross section taken along AA ′ in FIG. 118.

FIG. 120 shows a parasitic npn bipolar transistor 77
It is a top view of d.

FIG. 121 is a cross-sectional view showing a cross section taken along AA ′ in FIG. 120.

FIG. 122 is a circuit diagram showing a configuration of an undershoot countermeasure element 64p in the semiconductor device of Embodiment 26.

FIG. 123 is a circuit diagram of an undershoot countermeasure element in a semiconductor device according to a twenty-seventh embodiment.

124 is a sectional view showing a section of the N-channel transistor 294 shown in FIG. 123;

FIG. 125 is a circuit diagram of an undershoot countermeasure element in the semiconductor device according to the twenty-eighth embodiment.

126 is a cross-sectional view showing a cross section of the N-channel transistor 294a shown in FIG. 125.

FIG. 127 is a circuit diagram of an undershoot countermeasure element in the semiconductor device of the twenty-ninth embodiment.

FIG. 128 is a circuit diagram of an undershoot countermeasure element in the semiconductor device of the thirtieth embodiment.

FIG. 129 is a circuit diagram of an undershoot countermeasure element in the semiconductor device of Embodiment 31.

130 is a cross-sectional view showing a cross section of P-channel transistor 320 shown in FIG. 129.

FIG. 131 is a circuit diagram of an undershoot countermeasure element in a semiconductor device according to a thirty-second embodiment.

132 is a cross-sectional view showing a cross section of P-channel transistor 320a shown in FIG. 131.

FIG. 133 is a block diagram of an input buffer in a semiconductor device according to a thirty-third embodiment.

FIG. 134 is an input protection circuit described in JP-A-61-232658.

135 is a cross-sectional view for describing a cross-sectional structure of resistor 502 shown in FIG.

FIG. 136 is an example of an input waveform input to the semiconductor device from the outside.

FIG. 137 is a cross-sectional view showing a part of an input protection circuit and a cross section of a memory cell portion;

FIG. 138 is a plan view of a transistor having a conventional structure.

FIG. 139 is a cross-sectional view showing a cross section taken along XX ′ in FIG. 138;

140 is a cross-sectional view showing a cross section taken along line YY 'in FIG. 138.

[Explanation of symbols]

Reference Signs List 1 semiconductor device, 54 step-down power supply circuit, 56 VBB generation circuit, 58 step-up power supply circuit, 10, 12, 14 input buffer, 34 memory cell array, 62 terminals, 64
Undershoot protection device, 66 Positive surge protection device, 68 inverter, 70 junction diode, 72
Resistance, 74, 74a to 74n, 75, 75c to 75d,
79, 252a to 252h N-channel transistors,
84, 206, 220, 236 Gate electrode, 88, 8
8a, 88b, 90, 202, 204, 218, 22
4,234,240 n ⁺ region, 86,208,22
6,244 trench, 120 P-type silicon substrate,
122 P well, 104,174 polysilicon, 1
02,176 insulating film, 222,238,210,82
Normal element isolation region, 242, 246 Trench, 7
3,77,81 npn bipolar transistor, 29
2,312,318 resistance, 294,294a, 31
6,317 N-channel transistors, N1, N2, N
P2, N11, N12 nodes, 296,300 n ⁺ regions, 322,326 p ⁺ regions, 298 P-type body regions, 324 N-type body regions, 302,328 Gate oxide films, 304,330 Gate electrodes, 306,332
Insulating film, 308,334 Silicon substrate, 342 terminal, 346 Positive surge suppression element, 344 Undershoot prevention element, 348 Inverter.

Claims (38)

[Claims] 1. A semiconductor device formed on a main surface of a semiconductor substrate of a first conductivity type, comprising: a ground terminal receiving a ground potential applied from outside the semiconductor device; and a ground terminal input from outside the semiconductor device. An input terminal receiving an input signal, an internal node electrically coupled to the input terminal, an internal circuit performing a predetermined operation in response to a signal on the internal node, and a potential of the input terminal being the ground potential. Undershoot countermeasure means for making the potential of the internal node equal to or higher than the first potential at the time of an undershoot input lower than or equal to a lower first potential; A switching element coupled to form a path capable of conducting between the internal node and a first constant potential; From the switching element during undershoot inputs and a trench portion that inhibits electron migration injected into the semiconductor substrate, the semiconductor device. 2. The second conductivity type MOS transistor formed on the main surface and coupled to form a path capable of conducting between the internal node and the first constant potential. Wherein the MOS transistor comprises: a second conductivity type first impurity region connected to the internal node; a second conductivity type second impurity region coupled to the first constant potential; A gate electrode interposed between the first impurity region and the second impurity region, the gate electrode being located on the main surface, wherein the trench has a depth greater than a junction depth of the first impurity region. The semiconductor device according to claim 1, wherein the semiconductor device is deeply in contact with the second impurity region. 3. The semiconductor according to claim 2, wherein a gate of said MOS transistor is coupled to said ground potential, said first conductivity type is P-type, and said second conductivity type is N-type. apparatus. 4. The semiconductor device according to claim 2, wherein said first constant potential is said ground potential. 5. The semiconductor device according to claim 2, further comprising a power supply terminal receiving a power supply potential applied from outside, wherein said first constant potential is a potential according to said power supply potential. 6. A power supply terminal receiving an externally applied power supply potential, and a boosting means for receiving the power supply potential and boosting the internal boosted potential, wherein the first constant potential is the internal boosted potential. The semiconductor device according to claim 2. 7. The second impurity region surrounds the gate electrode and the first impurity region on the main surface, and the opening of the trench portion has the second impurity region on the main surface. 3. The semiconductor device according to claim 2, wherein the semiconductor device surrounds the semiconductor device. 8. The semiconductor device according to claim 2, wherein said second impurity region includes a third impurity region formed on a side wall of said trench portion. 9. The trench portion is opened such that an angle formed between a side wall in contact with the second impurity region and a main surface of the semiconductor substrate is less than 90 °, and a bottom surface is wider than the opening portion. The semiconductor device according to claim 2. 10. The switching element is formed on the main surface, is connected to the internal node, and has a second conductivity type first impurity region; and on the main surface, an opening of the trench. An element isolation portion formed between the first impurity region, in contact with the first impurity region, and formed deeper than a junction depth of the first impurity region; A second impurity region of a second conductivity type formed on a side wall of the trench portion deeper than a bottom of the portion and coupled to the first constant potential, wherein the second impurity region is formed on the main surface. 2. The semiconductor device according to claim 1, wherein a junction depth is smaller than a distance between said trench portion and said first impurity region. 11. The semiconductor device according to claim 10, wherein said first conductivity type is P-type, and said second conductivity type is N-type. 12. The semiconductor device according to claim 10, wherein said first constant potential is said ground potential. 13. The semiconductor device according to claim 10, further comprising a power supply terminal receiving a power supply potential applied from the outside, wherein said first constant potential is a potential according to said power supply potential. 14. A power supply terminal receiving an externally applied power supply potential, and a boosting means for receiving the power supply potential and boosting it to an internal boosted potential, wherein the first constant potential is the internal boosted potential. The semiconductor device according to claim 10. 15. The device according to claim 10, wherein the device isolation portion surrounds the first impurity region on the main surface, and an opening of the trench portion surrounds the device isolation portion on the main surface. Semiconductor device. 16. The semiconductor device according to claim 10, wherein said trench portion is opened such that an angle formed between a side wall and a main surface of said semiconductor substrate is less than 90 °, and a bottom surface is wider than said opening portion. . 17. The second conductivity type MOS transistor formed on the main surface and coupled to form a path capable of conducting between the internal node and the first constant potential. And an element isolation portion formed between the opening of the trench portion and the MOS transistor on the main surface, wherein the MOS transistor has a junction depth smaller than a bottom of the element isolation portion, A second impurity-type first impurity region connected to the internal node; a second conductivity-type second impurity region coupled to the first constant potential; 2. The semiconductor device according to claim 1, further comprising: a gate electrode located on the main surface sandwiched between the second impurity region and the second impurity region, wherein the second impurity region is in contact with the element isolation portion on the main surface. Semiconductor device. 18. The gate of the MOS transistor,
The semiconductor device according to claim 17, wherein the first conductivity type is P-type, and the second conductivity type is N-type. 19. The semiconductor device according to claim 17, wherein said first constant potential is said ground potential. 20. The semiconductor device according to claim 17, further comprising a power supply terminal receiving a power supply potential applied from outside, wherein said first constant potential is a potential according to said power supply potential. 21. A power supply terminal receiving an externally applied power supply potential, and a boosting unit receiving the power supply potential and boosting the internal boosted potential, wherein the first constant potential is the internal boosted potential. The semiconductor device according to claim 17. 22. The semiconductor device according to claim 17, wherein said isolation portion surrounds said MOS transistor on said main surface, and an opening of said trench portion surrounds said isolation portion on said main surface. . 23. The semiconductor device according to claim 17, wherein said switching element further includes a third impurity region formed on a side wall of said trench portion and coupled to a second constant potential. 24. The semiconductor device according to claim 2, wherein the trench is opened such that an angle formed between a side wall and a main surface of the semiconductor substrate is less than 90 °, and a bottom surface is wider than the opening. . 25. The semiconductor device according to claim 1, further comprising a resistor connected between said input terminal and said internal node. 26. A countermeasure against a positive surge which is connected to the internal node and makes the potential of the internal node equal to or lower than the second potential when the potential of the input terminal is equal to or higher than a second potential higher than the ground potential. The semiconductor device according to claim 1, further comprising a unit. 27. A semiconductor device formed on a semiconductor substrate, comprising: a ground terminal receiving a ground potential applied from outside the semiconductor device; and an input terminal receiving an input signal input from outside the semiconductor device. A first internal node connected to the input terminal; and a first internal node receiving a signal on the first internal node and transmitting the signal to a second internal node, wherein the input potential is lower than the ground potential.
Undershoot countermeasure means for making the potential of the second internal node equal to or higher than the first potential when the potential of the second internal node becomes equal to or lower than the potential of the second internal node; An internal circuit formed on a semiconductor substrate, wherein the undershoot countermeasure means comprises: a resistor connected between the first internal node and the second internal node; and a second internal node. A MOS transistor of a first conductivity type coupled to form a path capable of conducting with a constant potential, wherein the MOS transistor is connected to a semiconductor layer electrically separated by an insulating layer from the semiconductor substrate. A first formed and connected to the second internal node
A first impurity region of a conductivity type, a second impurity region of a first conductivity type formed in the semiconductor layer and coupled to the constant potential, and a channel formed in the semiconductor layer; A semiconductor device having a second conductivity type channel formation region sandwiched between a first impurity region and the second impurity region, and a gate electrode provided adjacent to the channel formation region. 28. The gate electrode is connected to the second internal node, the first conductivity type is P-type, the second conductivity type is N-type, and the constant potential is 28. The semiconductor device according to claim 27, which is at a ground potential. 29. The semiconductor device according to claim 28, wherein said MOS transistor has said channel formation region floating. 30. The semiconductor device according to claim 28, further comprising a power supply terminal receiving an externally applied power supply potential, wherein said MOS transistor has a potential corresponding to said power supply potential in said channel formation region. 31. The gate electrode is coupled to the ground potential, the first conductivity type is N-type, the second conductivity type is P-type, and the constant potential is the ground potential. 28. The semiconductor device according to claim 27. 32. The semiconductor device according to claim 31, wherein the channel formation region of the MOS transistor is floated. 33. The semiconductor device according to claim 31, wherein the channel formation region of the MOS transistor is set to the ground potential. 34. The gate electrode is coupled to the ground potential, the first conductivity type is N-type, the second conductivity type is P-type, and the constant potential is equal to the power supply potential. 28. The semiconductor device according to claim 27, which has a corresponding potential. 35. The semiconductor device according to claim 34, wherein said MOS transistor has said channel formation region floating. 36. The semiconductor device according to claim 34, wherein said MOS transistor has said channel formation region set to said ground potential. 37. When the potential of the input terminal is connected to the first internal node and the potential of the input terminal becomes a second potential higher than the ground potential, the potential of the first internal node is lower than or equal to the second potential. 28. The semiconductor device according to claim 27, further comprising a positive surge countermeasure for reducing the surge. 38. When the potential of the input terminal is connected to the second internal node and the potential of the input terminal becomes a second potential higher than the ground potential, the potential of the second internal node is lower than or equal to the second potential. 28. The semiconductor device according to claim 27, further comprising a positive surge countermeasure for reducing the surge.