JPH0354866B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS type semiconductor integrated circuit device provided with a MOS transistor for forward substrate bias voltage clamping.

[Conventional technology]

In current MOS type semiconductor integrated circuits, especially MOS dynamic RAM, attempts are made to unify the power supply, and the substrate voltage is generally generated by a substrate bias voltage generation circuit provided on the semiconductor substrate (chip). It has become

FIG. 1 shows the relationship between the substrate voltage and power supply voltage in a MOS type semiconductor integrated circuit incorporating a conventional substrate bias voltage generation circuit.

In Figure 1, if the substrate voltage is V _BB and the power supply voltage is V _CC , the relationship between the two is clear from Figure 1. When the power supply voltage V _CC is relatively low, the substrate voltage V _BB is equal to the power supply voltage V The negative voltage becomes deeper in proportion to _CC , but becomes shallower as the power supply voltage V _CC rises, and may become a positive voltage when it becomes very high.
The reason for this is that when the power supply voltage V _CC rises and current consumption increases, the hole current in the semiconductor substrate due to impact ionization increases, and the charging current from the substrate bias voltage generation circuit cannot compensate for this. . The power supply voltage within the operation compensation area for semiconductor integrated circuits
This situation will not occur if it is used at V _CC , but if a high voltage is applied to the semiconductor integrated circuit due to mishandling or other reasons, the substrate voltage will rise to the extent that the pn junction is forward biased. There is a risk of permanent damage to the semiconductor integrated circuit.

Figures 2a and b show the waveform of the power supply voltage V CC and the substrate voltage _V when a semiconductor integrated circuit with a built-in substrate bias voltage generation circuit is powered on when a relatively large capacitance is formed between the power supply line and the substrate. _Figure 2a shows the relationship between the power supply voltage _VCC and time, and Figure 2b shows the relationship between the substrate voltage _VBB and time. It takes some time for the substrate bias voltage generation circuit to generate a sufficient voltage after the power is turned on. Therefore, the supply voltage
When V _CC rises steeply, there is a period when the substrate voltage V _BB becomes positive due to capacitive coupling between the power supply line and the semiconductor substrate, as shown in FIGS. 2a and 2b. If this substrate voltage V _BB rises significantly, there is a possibility of permanent destruction of the semiconductor integrated circuit, and even if destruction does not occur, there is a drawback that an extremely large inrush power supply current will flow.

[Summary of the invention]

This invention was made to improve the above-mentioned drawbacks, and includes a MOS type semiconductor integrated circuit with a built-in substrate bias voltage generation circuit, the drain and gate of which are connected to the semiconductor substrate, and the source of which is connected to ground. For forward body bias voltage clamp
By providing a MOS transistor, it is possible to prevent the substrate voltage from becoming positive, making it highly reliable.
The present invention provides a MOS type semiconductor integrated circuit device. The present invention will be explained below using the drawings.

[Embodiments of the invention]

FIG. 4 shows an embodiment of the invention, and FIG. 3 shows an equivalent circuit of the invention.

In Fig. 3, when the voltage of the semiconductor substrate becomes positive and exceeds the threshold voltage of the forward substrate bias voltage clamping MOS transistor T (this threshold voltage is V _TH ), the forward substrate bias voltage clamping occurs. The MOS transistor T becomes conductive, discharging the semiconductor substrate, and suppressing the rise in substrate voltage. Therefore, to make this invention more effective, for forward body bias voltage clamping
To set the threshold voltage V _TH of the MOS transistor T to the lowest possible value within the range of 0 volts or more and below the built-in potential of the pn junction, and for forward substrate bias voltage clamping to quickly discharge the semiconductor substrate. The purpose is to increase the channel width of the MOS transistor T.

FIG. 4 shows the present invention implemented in a MOS dynamic RAM having a one-transistor/one-capacitor type memory structure. In Figure 4, 1 is
Semiconductor substrate which is the chip of MOS dynamic RAM, 2 is the bonding pad of the ground terminal, 3
is the bonding pad of the output terminal of the substrate bias voltage generation circuit, and this bonding pad 3 is
The semiconductor substrate 1 is connected to a die frame (not shown) of a package to which the semiconductor substrate 1 is die-bonded, and a substrate voltage is applied to the semiconductor substrate 1. Reference numeral 4 designates a ground wiring that goes around the outer periphery of the semiconductor substrate 1, and 5 designates an output wiring of the substrate bias voltage generation circuit that goes around the outer periphery of the semiconductor substrate 1 as well. 6 is a memory cell array area, 7 is a memory peripheral circuit area, and 8 is a forward substrate bias voltage clamping transistor area forming a forward substrate bias voltage clamping MOS transistor T.

A one-transistor/one-capacitor type memory cell is generally manufactured using a multilayer polysilicon process. For example, when using a two-layer polysilicon process, the first polysilicon constitutes the memory cell plate, and the second polysilicon constitutes the transfer gate of the memory cell and the gate of the peripheral circuit transistor.
The first polysilicon gate oxide film is extremely thin to increase the storage capacity of the memory cell. Therefore, if a transistor is constructed using the first polysilicon for the gate, a transistor with a low threshold voltage V _TH of the forward substrate bias voltage clamping MOS transistor T can be created without special ion implantation. Obtainable.
For example, if the gate oxide film of the first polysilicon is 160
~200Å, second polysilicon gate oxide is 350Å
~400 Å, the threshold voltage V _TH of the second polysilicon gate transistor with a channel length of about 2 μm is
If it is about 0.5V, the threshold voltage of the first polysilicon gate transistor with a channel length of about 3μm
V _TH will be about 0.1 to 0.2V. Furthermore, for various reasons, the ground wiring 4 and the output wiring 5 of the substrate bias voltage generation circuit are wired so as to go around the outer periphery of the semiconductor substrate 1. In the forward substrate bias voltage clamping transistor region 8 shown in the shaded area in FIG. The first polysilicon gate transistor provides a forward substrate bias voltage clamp with a very low threshold voltage V _TH and a very large channel.
It is possible to configure the MOS transistor T without adding any special process and without increasing the chip area.

〔Effect of the invention〕

As explained above, the present invention includes a substrate bias voltage generation circuit on a semiconductor substrate of a MOS type semiconductor integrated circuit, and has a forward substrate bias voltage generation circuit having a drain and a gate connected to the semiconductor substrate, and a source connected to the ground. Since it is a MOS type semiconductor integrated circuit device equipped with a voltage clamping MOS transistor, there is an advantage that the substrate voltage can be prevented from becoming positive and a highly reliable MOS type semiconductor integrated circuit can be obtained.

[Brief explanation of drawings]

Figure 1 is a diagram showing the relationship between the substrate voltage and power supply voltage in a MOS type semiconductor integrated circuit with a built-in conventional substrate bias voltage generation circuit, and Figure 2 is a diagram showing the power supply voltage when the semiconductor integrated circuit shown in Figure 1 is powered on. The diagrams show waveforms and substrate voltage waveforms. Figure 2a is a voltage waveform diagram showing the relationship between power supply voltage and time, Figure 2b is a voltage waveform diagram showing the relationship between substrate voltage and time, and Figure 3 is a voltage waveform diagram showing the relationship between substrate voltage and time. FIG. 4 is an equivalent circuit diagram for explaining the present invention, and is a configuration diagram showing an embodiment of the present invention. In the figure, 1 is the semiconductor substrate, 2 is the bonding pad for the ground terminal, 3 is the bonding pad for the output terminal of the substrate bias voltage generation circuit, 4 is the ground wiring, 5 is the wiring for the output of the substrate bias voltage generation circuit, 6 is a memory cell array area, 7 is a peripheral circuit area of the memory, 8 is a transistor area for clamping forward substrate bias voltage, and T is a MOS transistor for clamping forward substrate bias voltage. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A forward substrate bias voltage clamping circuit including a substrate bias voltage generation circuit on a semiconductor substrate of a MOS type semiconductor integrated circuit, a drain and a gate connected to the semiconductor substrate, and a source connected to ground. Features a MOS transistor
MOS type semiconductor integrated circuit device. 2 When the threshold voltage of the forward substrate bias voltage clamping MOS transistor is 0 volts or more,
Claim 1, characterized in that the built-in potential of the p-n junction is lower than the built-in potential of the p-n junction.
MOS type semiconductor integrated circuit device. 3 A MOS type semiconductor integrated circuit is a MOS dynamic RAM with a one-transistor/one-capacitor type memory cell structure using a multilayer polysilicon process, and its memory cell plate and the gate of the forward substrate bias voltage clamping MOS transistor are the same. MOS according to claim 1, characterized in that the MOS is composed of a layer of polysilicon.
type semiconductor integrated circuit device.