JP3003407B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a structure of an input / output unit.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit device,
A potential of about 5 V is used as a power supply potential (V _CC ). In the case of a P-type silicon substrate, a negative potential −V _BB (−3 V) is applied by a ground potential (OV) or a back bias generator (BBG). ), And the potential is set to −V _BB potential. In particular, in the case of a DRAM, in order to prevent the charge serving as information stored in the memory cell capacitor from leaking to the bit line side via the cell transistor during the standby period due to floating of the potential of the word line, the potential of the cell transistor is reduced. It must have large off margin by increasing the threshold had been set therefore the substrate potential -V _BB. However, the fine gate oxide film advances in processing technology is thinned, it is necessary to use by lowering the power supply voltage applied for maintaining reliability becomes after 16M DRAM for the gate oxide film of the ultra-thin, V _CC At about 3V. Therefore, the substrate potential is changed from -V _BB to the ground potential to compensate for the access speed equivalent to the conventional one, the threshold value of the transistor in the peripheral circuit is reduced, and the double well structure is used to prevent leakage of electric charge in the cell part. Has been proposed in which only the cell portion is formed in a P-well and the P-well potential is set to a -V _BB potential.

FIG. 3 is a schematic sectional view of a DRAM having a double well structure. Reference numeral 1 denotes a P-type silicon substrate, which is ohmically connected to a P ⁺ -type diffusion layer 5 connected to a ground potential terminal, and is fixed at the ground potential. Reference numeral 2 denotes an N well formed deep in the substrate, which is connected to a power supply potential end and has an N ⁺ type diffusion layer 6.
The V _CC potential has ohmic contact with. 4 is deep N
P is connected to the back-bias generator BBG for generating -V _BB potentials are P-well formed in the well 2 ⁺
It is ohmic-connected to the mold diffusion layer 7 and has a potential of -V _BB .
The N ⁺ type diffusion layer 8 is an active region for forming a memory cell. The cell region is formed in the P well 4 and is separated from the P type silicon substrate 1 by the deep N well 2. N ⁺ type diffusion layer 9 formed on the surface of P type silicon substrate 1 in input / output circuit region A becomes an active region for forming an N channel MOS transistor. 10
Is a P ⁺ -type diffusion layer formed on the N-well, and becomes an active region for forming a P-channel MOS transistor. Reference numeral 11 denotes an N ⁺ -type diffusion layer connected to the power supply terminal, which is ohmically connected to the N well 3 and connects the N well 3 to V
_Works to fix to _CC potential.

[0004]

In the above-described conventional semiconductor integrated circuit device, the substrate potential is set to the ground potential, so that the N ⁺ type diffusion layer 12 has a higher potential than the negative potential −V _BB.
, The reverse bias voltage between them decreases, and the junction capacitance increases. For this reason, the input / output terminal capacity is increased, which causes problems such as a possibility of exceeding the limit capacity and a delay in access speed in the input / output unit.

Further, since the substrate potential is set to be shallower than the negative potential to the ground potential, the margin for latch-up is reduced, and the substrate potential caused by the minority carriers injected into the substrate due to noise from the input / output terminals is reduced. There is also a problem that the risk of occurrence of latch-up increases due to the fluctuation.

[0006]

According to the present invention, there is provided a semiconductor integrated circuit device comprising a reverse conductive member provided on a surface portion of a semiconductor substrate of one conductivity type.
Type channel MOS transistor and one conductivity type semiconductor
Provided on the surface portion of the first reverse-conducting type well formed in the substrate
C including the obtained one conductivity type channel MOS transistor
A peripheral circuit MOS structure, and an internal circuit formed on the deeper than the first opposite conductivity type wells second opposite conductivity type well,
The second third of the reverse of the opposite conductivity type well substantially the same depth
Is formed on the conductive well and input-output circuit comprising an input protection circuit and an output circuit, the first collector of said Ichishirubeden type semiconductor substrate
And means for biasing the source potential, and means for biasing the opposite conductivity type <br/> well of the first and third to the second power supply potential, said first
A method of biasing the second well of the opposite conductivity type to the third power supply potential.
A semiconductor integrated circuit device comprising:
Reverse conductivity type channel MOS transistor included in power circuit
Is formed in the third well of the opposite conductivity type and is connected to a fourth power supply.
On the surface of the well of one conductivity type
And the third reverse conductivity type well and the one conductivity type well.
Reverse bias between the third reverse conductivity type well and the third reverse conductivity type well.
Greater than the reverse bias between the first conductivity type semiconductor substrate
Specifically, when one conductivity type is a P-type,
In this case, the first power supply potential is the ground potential,
The power supply potential is a positive power supply potential, and the fourth power supply potential is a negative power supply potential.
In the case of the source potential and one conductivity type is N-type,
The first power supply potential is a positive power supply potential, and the second power supply potential is
The ground potential, the third power supply potential is a negative power supply potential,
Is a positive power supply voltage higher than the first power supply potential.
It is a place .

[0007]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic sectional view showing a DRAM having a double well structure according to a first embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a P-type silicon substrate, which is fixed at a ground potential by a P ⁺ -type diffusion layer 5. Reference numeral 2-1 denotes a deep second N well formed at a depth of about 7 to 8 μm from the surface of the P-type silicon substrate, and similarly, 2-2 denotes a deep third N well, which are memory cell array regions C and The N ⁺ -type diffusion layers 6-1 and 6-2 formed in the input / output circuit area A and having a power supply potential V _{CC of} about 3 V are fixed to the V _CC potential. 4-1 and 4-2 are the second and third N wells 2-1 and 4-2, respectively.
2-2, a first and second P wells formed at a depth of about 2 to 3 μm from the substrate surface, and a back bias generator BB for generating a negative potential −V _{BB of} about −1 to −3 V
-V _BB by P ⁺ type diffusion layers 7-1 and 7-2 connected to G
It is fixed to the potential. Reference numeral 8 denotes an N ⁺ type diffusion layer which is an active region formed in the first P well 4-1, and constitutes a memory cell array region C, which constitutes a cell transistor and a cell capacitor. Similarly, in the N ⁺ type diffusion layer, components such as an input resistor, a protection circuit, and an output transistor in the output circuit region A are provided. Reference numeral 3 denotes a first N well formed on the surface of the P-type silicon substrate 1 to a depth of about 2 to 3 μm, which is fixed to the V _CC potential by an N ⁺ type diffusion layer 11 connected to a power supply terminal. The P ⁺ -type diffusion layer 10 serving as an active region of the P-channel MOS transistor formed in the N-well 1 and the N ⁺ -type diffusion layer 9 of the N-channel MOS transistor formed directly on the P-type silicon substrate 1 are formed in the peripheral circuit region 13. Placed in

In this embodiment, the N ⁺ diffusion layer 12 which is the active region of the input / output circuit region forms a PN junction with the second P well 4-2 back-biased to the potential −V _BB , so As compared with the case where a junction is formed on a P-type silicon substrate having a ground potential as described above, the junction capacitance can be reduced by the extent that the depletion layer spreads. For example, the junction capacitance, which was conventionally 2 pF, becomes about 1.4 pF when -V _BB = 1 V, and about 1 pF when -V _BB = -3 V.
It can be reduced to 0 to 70%.

Further, since the well potential is deepened, a margin for latch-up is increased, and noise from the input / output terminal causes the N ⁺ type diffusion layer 12 to pass through the second P well 4−.
Latch-up tolerance is increased with respect to fluctuations in the well potential due to minority carriers injected into the semiconductor laser 2. Furthermore, minority carriers injected into the second P well 4-2 are injected into the substrate due to the guard ring effect of the deep third N well 2-2 fixed at the _Vcc potential. Since the minority carrier can be completely ignored, there is no danger of latch-up due to input / output terminal noise in the peripheral circuit area B.

FIG. 2 is a schematic sectional view showing a second embodiment of the present invention.

This embodiment is suitable for a CMOS circuit in which a P-well is formed in an N-type silicon substrate. In the figure, reference numeral 1a denotes an N-type silicon substrate, which is fixed at a VCC potential which is a power supply potential of about 3 V by an N + type diffusion layer 5a. 2a-1, 2a-2
Are deep second and third P wells formed at a depth of about 7 to 8 μm from the surface of the N-type silicon substrate 1a, and are formed in the memory cell array region C and the input / output circuit region A. In the memory cell array region, the second P well 2a-1
The N + -type diffusion layer 8a connected to the negative potential terminal serves as an active region of a cell transistor or a capacitor. Further, in the input / output circuit region A, the P + type diffusion layer 6 serving as the ground potential is provided.
It is fixed to the ground potential by a-2. Reference numeral 4a denotes an N well having a depth of about 2 to 3 μm formed in the input / output circuit area A, and a boot circuit VBOO for generating a potential higher than a power supply potential.
The boot potential is fixed at about 4 to 5 V by the N + type diffusion layer 7a connected to T. Reference numeral 12a denotes a P + type diffusion layer connected to the input / output pad 13, and constitutes an active area such as an input resistor, an input protection, and an output circuit. Reference numeral 3a denotes a P well having a depth of about 2 to 3 μm formed in the N-type silicon substrate 1a, which is fixed to the ground potential by the P + -type diffusion layer 11a serving as the ground potential. N + type diffusion layer 10a formed in P well 3a and P + type
The active element in the peripheral circuit region B is constituted by the + type diffusion layer 9a. In this embodiment, no double well is used in the memory cell array region.

[0014]

As described above, the semiconductor integrated circuit device of the present invention has a double well in which the input / output circuit region is formed in the second conductivity type well formed in the semiconductor substrate of the first conductivity type. since you are deep potential than has the structure, further the potential of the first conductivity type well substrate,
The junction capacitance can be reduced, and access delay in the input / output unit can be prevented. In addition, the latch-up margin in the input / output unit can be increased, and the occurrence of latch-up in the internal circuit due to noise from the input / output terminal can be prevented.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a first embodiment of the present invention.

FIG. 2 is a schematic sectional view showing a second embodiment of the present invention.

FIG. 3 is a schematic sectional view showing a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 1a N-type silicon substrate 2-1 and 2-2 Deep N well 2a-1 and 2a-2 Deep P well 3 N well 3a P well 4-1 and 4-2 P well 4-1 and 4 -2 N well 5,7-1,7-2,10 P ⁺ type diffusion layer 6,6-1,6-2,9,11 N ⁺ type diffusion layer 5a, 7a-1,7a-2,10a, 12a N ⁺ type diffusion layer 6a-1, 6a-2, 7a, 9a, 11a P ⁺ type diffusion layer 13 Input / output pad

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/8238 H01L 21/8242 H01L 27/092 H01L 27/10

Claims (2)

(57) [Claims] A first conductivity type channel MOS transistor provided on a surface of a one conductivity type semiconductor substrate;
Surface portion of first reverse conductivity type well formed on semiconductor substrate
A one conductivity type channel MOS transistor provided with a peripheral circuit of a CMOS structure including a first opposite conductivity type c <br/> internal circuit formed deeper than the E le second opposite conductivity type well and an input-output circuit including a second opposite conductivity type well and formed in the third of the opposite conductivity type well substantially the same depth input protection circuit and an output circuit, the Ichishirubeden type semiconductor substrate first
Means for biasing the first power source potential, the reverse of the first and third
Means for biasing the conductivity type well to a second power supply potential ;
Biasing the second reverse conductivity type well to a third power supply potential;
A semiconductor integrated circuit device comprising:
Reverse conductivity type channel MOS transistor included in the entry output circuit
The transistor is formed in the third well of the opposite conductivity type and formed in the fourth well.
At the surface of one conductivity type well biased to the power supply potential
And the third opposite conductivity type well and the one conductivity type well are provided.
The reverse bias between the third reverse conductivity type well and the
Than the reverse bias between the substrate and the one conductivity type semiconductor substrate.
A semiconductor integrated circuit device which is large . 2. The method according to claim 1 , wherein the first conductivity type is P-type.
Is the ground potential, and the second and third power supply potentials are positive.
The power supply potential and the fourth power supply potential are negative power supply potentials.
When the one conductivity type is N-type, the first power supply potential
Is a positive power supply potential, the second power supply potential is a ground potential,
The third power supply potential is a negative power supply potential, and the fourth power supply potential is
2. The semiconductor integrated circuit device according to claim 1, wherein the positive power supply potential is higher than the first power supply potential .